From 6c106a79c63ea3168016304a1518cdf23dd3b683 Mon Sep 17 00:00:00 2001
From: Marcin Bukat <marcin.bukat@gmail.com>
Date: Sun, 15 Jun 2014 11:08:51 +0200
Subject: Rework reg description file for rk27xx

Change-Id: I3fc1c6c70c828dca285479eaa168328a2a8fdf2c
---
 utils/regtools/desc/regs-rk27xx.xml | 1250 +++++++++++++++++------------------
 1 file changed, 601 insertions(+), 649 deletions(-)

(limited to 'utils')

diff --git a/utils/regtools/desc/regs-rk27xx.xml b/utils/regtools/desc/regs-rk27xx.xml
index b58571aef8..d7e9b8b361 100644
--- a/utils/regtools/desc/regs-rk27xx.xml
+++ b/utils/regtools/desc/regs-rk27xx.xml
@@ -23,21 +23,15 @@ KIND, either express or implied.
     <addr name="TIMER2" addr="0x18000020" />
       <reg name="TMRnLR">
         <formula string="n*0x10" />
-        <addr name="TMR0LR" addr="0x00" />
-        <addr name="TMR1LR" addr="0x10" />
-        <addr name="TMR2LR" addr="0x20" />
+        <addr name="LR" addr="0x00" />
       </reg>
       <reg name="TMRnCVR">
         <formula string="0x04+n*0x10" />
-        <addr name="TMR0CVR" addr="0x04" />
-        <addr name="TMR1CVR" addr="0x14" />
-        <addr name="TMR2CVR" addr="0x24" />
+        <addr name="CVR" addr="0x04" />
       </reg>
       <reg name="TMRnCON">
         <formula string="0x08+n*0x10" />
-        <addr name="TMR0CON" addr="0x08" />
-        <addr name="TMR1CON" addr="0x18" />
-        <addr name="TMR2CON" addr="0x28" />
+        <addr name="CON" addr="0x08" />
       </reg>
   </dev>
   <dev name="UART" long_name="UART" desc="UART" version="1.0">
@@ -45,403 +39,341 @@ KIND, either express or implied.
     <addr name="UART1" addr="0x18008000" />
       <reg name="UARTn_RBR" addr="0x00">
         <formula string="n*0x4000" />
-        <addr name="UART0_RBR" addr="0x00" />
-        <addr name="UART1_RBR" addr="0x4000" />
+        <addr name="RBR" addr="0x00" />
       </reg>
       <reg name="UARTn_THR" addr="0x00">
         <formula string="n*0x4000" />
-        <addr name="UART0_THR" addr="0x00" />
-        <addr name="UART1_THR" addr="0x4000" />
+        <addr name="THR" addr="0x00" />
       </reg>
       <reg name="UARTn_DLL" addr="0x00">
         <formula string="n*0x4000" />
-        <addr name="UART0_DLL" addr="0x00" />
-        <addr name="UART1_DLL" addr="0x4000" />
+        <addr name="DLL" addr="0x00" />
       </reg>
       <reg name="UARTn_DLH" addr="0x04">
         <formula string="0x04+n*0x4000" />
-        <addr name="UART0_DLH" addr="0x04" />
-        <addr name="UART1_DLH" addr="0x4004" />
+        <addr name="DLH" addr="0x04" />
       </reg>
       <reg name="UARTn_IER" addr="0x04">
         <formula string="0x04+n*0x4000" />
-        <addr name="UART0_IER" addr="0x04" />
-        <addr name="UART1_IER" addr="0x4004" />
+        <addr name="IER" addr="0x04" />
       </reg>
       <reg name="UARTn_IIR" addr="0x08">
         <formula string="0x08+n*0x4000" />
-        <addr name="UART0_IIR" addr="0x08" />
-        <addr name="UART1_IIR" addr="0x4008" />
+        <addr name="IIR" addr="0x08" />
       </reg>
       <reg name="UARTn_FCR" addr="0x08">
         <formula string="0x08+n*0x4000" />
-        <addr name="UART0_FCR" addr="0x08" />
-        <addr name="UART1_FCR" addr="0x4008" />
+        <addr name="FCR" addr="0x08" />
       </reg>
       <reg name="UARTn_LCR" addr="0x0c">
         <formula string="0x0c+n*0x4000" />
-        <addr name="UART0_LCR" addr="0x0c" />
-        <addr name="UART1_LCR" addr="0x400c" />
+        <addr name="LCR" addr="0x0c" />
       </reg>
       <reg name="UARTn_MCR" addr="0x10">
         <formula string="0x10+n*0x4000" />
-        <addr name="UART0_MCR" addr="0x10" />
-        <addr name="UART1_MCR" addr="0x4010" />
+        <addr name="MCR" addr="0x10" />
       </reg>
       <reg name="UARTn_LSR" addr="0x14">
         <formula string="0x14+n*0x4000" />
-        <addr name="UART0_LSR" addr="0x14" />
-        <addr name="UART1_LSR" addr="0x4014" />
+        <addr name="LSR" addr="0x14" />
       </reg>
       <reg name="UARTn_MSR" addr="0x18">
         <formula string="0x18+n*0x4000" />
-        <addr name="UART0_MSR" addr="0x18" />
-        <addr name="UART1_MSR" addr="0x4018" />
+        <addr name="MSR" addr="0x18" />
       </reg>
   </dev>
   <dev name="GPIO" long_name="GPIO" desc="GPIO" version="1.0">
     <addr name="GPIO0" addr="0x1800c000" />
-      <reg name="GPIO_PADR" addr="0x00">
-      </reg>
-      <reg name="GPIO_PACON" addr="0x04">
-      </reg>
-      <reg name="GPIO_PBDR" addr="0x08">
-      </reg>
-      <reg name="GPIO_PBCON" addr="0x0c">
-      </reg>
-      <reg name="GPIO_PCDR" addr="0x10">
-      </reg>
-      <reg name="GPIO_PCCON" addr="0x14">
-      </reg>
-      <reg name="GPIO_PDDR" addr="0x18">
-      </reg>
-      <reg name="GPIO_PDCON" addr="0x1c">
-      </reg>
-      <reg name="GPIO_TEST" addr="0x20">
-      </reg>
-      <reg name="GPIO_IEA" addr="0x24">
-      </reg>
-      <reg name="GPIO_IEB" addr="0x28">
-      </reg>
-      <reg name="GPIO_IEC" addr="0x2c">
-      </reg>
-      <reg name="GPIO_IED" addr="0x30">
-      </reg>
-      <reg name="GPIO_ISA" addr="0x34">
-      </reg>
-      <reg name="GPIO_ISB" addr="0x38">
-      </reg>
-      <reg name="GPIO_ISC" addr="0x3c">
-      </reg>
-      <reg name="GPIO_ISD" addr="0x40">
-      </reg>
-      <reg name="GPIO_IBEA" addr="0x44">
-      </reg>
-      <reg name="GPIO_IBEB" addr="0x48">
-      </reg>
-      <reg name="GPIO_IBEC" addr="0x4c">
-      </reg>
-      <reg name="GPIO_IBED" addr="0x50">
-      </reg>
-      <reg name="GPIO_IEVA" addr="0x54">
-      </reg>
-      <reg name="GPIO_IEVB" addr="0x58">
-      </reg>
-      <reg name="GPIO_IEVC" addr="0x5c">
-      </reg>
-      <reg name="GPIO_IEVD" addr="0x60">
-      </reg>
-      <reg name="GPIO_ICA" addr="0x64">
-      </reg>
-      <reg name="GPIO_ICB" addr="0x68">
-      </reg>
-      <reg name="GPIO_ICC" addr="0x6c">
-      </reg>
-      <reg name="GPIO_ICD" addr="0x70">
-      </reg>
-      <reg name="GPIO_ISR" addr="0x74">
-      </reg>
+      <reg name="PADR" addr="0x00"></reg>
+      <reg name="PACON" addr="0x04"></reg>
+      <reg name="PBDR" addr="0x08"></reg>
+      <reg name="PBCON" addr="0x0c"></reg>
+      <reg name="PCDR" addr="0x10"></reg>
+      <reg name="PCCON" addr="0x14"></reg>
+      <reg name="PDDR" addr="0x18"></reg>
+      <reg name="PDCON" addr="0x1c"></reg>
+      <reg name="TEST" addr="0x20"></reg>
+      <reg name="IEA" addr="0x24"></reg>
+      <reg name="IEB" addr="0x28"></reg>
+      <reg name="IEC" addr="0x2c"></reg>
+      <reg name="IED" addr="0x30"></reg>
+      <reg name="ISA" addr="0x34"></reg>
+      <reg name="ISB" addr="0x38"></reg>
+      <reg name="ISC" addr="0x3c"></reg>
+      <reg name="ISD" addr="0x40"></reg>
+      <reg name="IBEA" addr="0x44"></reg>
+      <reg name="IBEB" addr="0x48"></reg>
+      <reg name="IBEC" addr="0x4c"></reg>
+      <reg name="IBED" addr="0x50"></reg>
+      <reg name="IEVA" addr="0x54"></reg>
+      <reg name="IEVB" addr="0x58"></reg>
+      <reg name="IEVC" addr="0x5c"></reg>
+      <reg name="IEVD" addr="0x60"></reg>
+      <reg name="ICA" addr="0x64"></reg>
+      <reg name="ICB" addr="0x68"></reg>
+      <reg name="ICC" addr="0x6c"></reg>
+      <reg name="ICD" addr="0x70"></reg>
+      <reg name="ISR" addr="0x74"></reg>
   </dev>
   <dev name="WDT" long_name="Watchdog" desc="Watchdog" version="1.0">
     <addr name="WDT" addr="0x18010000" />
-      <reg name="WDTLR" addr="0x00">
-      </reg>
-      <reg name="WDTCVR" addr="0x04">
-      </reg>
-      <reg name="WDTCON" addr="0x08">
-      </reg>
+      <reg name="LR" addr="0x00"></reg>
+      <reg name="CVR" addr="0x04"></reg>
+      <reg name="CON" addr="0x08"></reg>
   </dev>
   <dev name="RTC" long_name="Real time clock" desc="Real time clock" version="1.0">
     <addr name="RTC" addr="0x18014000" />
-      <reg name="RTC_TIME" addr="0x00">
-      </reg>
-      <reg name="RTC_DATE" addr="0x04">
-      </reg>
-      <reg name="RTC_TALARM" addr="0x08">
-      </reg>
-      <reg name="RTC_DALARM" addr="0x0c">
-      </reg>
-      <reg name="RTC_CTRL" addr="0x10">
-      </reg>
-      <reg name="RTC_RESET" addr="0x14">
-      </reg>
-      <reg name="RTC_PWOFF" addr="0x18">
-      </reg>
-      <reg name="RTC_PWFAIL" addr="0x1c">
-      </reg>
+      <reg name="TIME" addr="0x00"></reg>
+      <reg name="DATE" addr="0x04"></reg>
+      <reg name="TALARM" addr="0x08"></reg>
+      <reg name="DALARM" addr="0x0c"></reg>
+      <reg name="CTRL" addr="0x10"></reg>
+      <reg name="RESET" addr="0x14"></reg>
+      <reg name="PWOFF" addr="0x18"></reg>
+      <reg name="PWFAIL" addr="0x1c"></reg>
   </dev>
   <dev name="SPI" long_name="Serial peripherial interface" desc="Serial peripherial interface" version="1.0">
      <addr name="SPI" addr="0x18018000" />
-       <reg name="SPI_TXR" addr="0x00">
-       </reg>
-       <reg name="SPI_RXR" addr="0x00">
-       </reg>
-       <reg name="SPI_IER" addr="0x04">
-       </reg>
-       <reg name="SPI_FCR" addr="0x08">
-       </reg>
-       <reg name="SPI_FWCR" addr="0x0c">
-       </reg>
-       <reg name="SPI_DLYCR" addr="0x10">
-       </reg>
-       <reg name="SPI_TXCR" addr="0x14">
-       </reg>
-       <reg name="SPI_RXCR" addr="0x18">
-       </reg>
-       <reg name="SPI_SSCR" addr="0x1c">
-       </reg>
-       <reg name="SPI_ISR" addr="0x20">
-       </reg>
+       <reg name="TXR" addr="0x00"></reg>
+       <reg name="RXR" addr="0x00"></reg>
+       <reg name="IER" addr="0x04"></reg>
+       <reg name="FCR" addr="0x08"></reg>
+       <reg name="FWCR" addr="0x0c"></reg>
+       <reg name="DLYCR" addr="0x10"></reg>
+       <reg name="TXCR" addr="0x14"></reg>
+       <reg name="RXCR" addr="0x18"></reg>
+       <reg name="SSCR" addr="0x1c"></reg>
+       <reg name="ISR" addr="0x20"></reg>
   </dev>
   <dev name="SCU" long_name="System control unit" desc="System control unit" version="1.0">
     <addr name="SCU" addr="0x1801c000" />
-    <reg name="SCU_ID" addr="0x00">
-      <field name="SOC_ID" bitrange="31:0">
-        <value name="REVISION_A" value="0xa1000604" />
-        <value name="REVISION_B" value="0xa100027b" />
-      </field>
-    </reg>
-    <reg name="SCU_REMAP" addr="0x04">
-      <field name="MEM_REMAP" bitrange="31:0">
-        <value name="IRAM_0x000000" value="0xdeadbeef" />
-        <value name="ROM_0x000000" value="0x00000000" />
-      </field>
-    </reg>
-    <reg name="SCU_PLLCON1" addr="0x08">
-      <field name="ARM_PLL_TEST_CONTROL" bitrange="25:25">
-        <value name="TEST" value="0x01" />
-        <value name="NORMAL" value="0x00" />
-      </field>
-      <field name="ARM_PLL_SATURATION" bitrange="24:24">
-        <value name="ENABLE" value="0x01" />
-        <value name="DISABLE" value="0x00" />
-      </field>
-      <field name="ARM_PLL_FAST_LOCK" bitrange="23:23">
-        <value name="ENABLE" value="0x01" />
-        <value name="DISABLE" value="0x00" />
-      </field>
-      <field name="ARM_PLL_POWERDOWN" bitrange="22:22">
-         <value name="PLL_OFF" value="0x01" />
-         <value name="PLL_ON" value="0x00" />
-      </field>
-      <field name="ARM_PLL_CLKR" bitrange="21:16"></field>
-      <field name="ARM_PLL_CLKF" bitrange="15:4"></field>
-      <field name="ARM_PLL_CLKOD" bitrange="3:1"></field>
-      <field name="ARM_PLL_BYPASS" bitrange="0:0">
-        <value name="ENABLE" value="0x01" />
-        <value name="DISABLE" value="0x00" />
-      </field>
-    </reg>
-    <reg name="SCU_PLLCON2" addr="0x0c">
-      <field name="DSP_PLL_TEST_CONTROL" bitrange="25:25">
-        <value name="TEST" value="0x01" />
-        <value name="NORMAL" value="0x00" />
-      </field>
-      <field name="DSP_PLL_SATURATION" bitrange="24:24">
-        <value name="ENABLE" value="0x01" />
-        <value name="DISABLE" value="0x00" />
-      </field>
-      <field name="DSP_PLL_FAST_LOCK" bitrange="23:23">
-        <value name="ENABLE" value="0x01" />
-        <value name="DISABLE" value="0x00" />
-      </field>
-      <field name="DSP_PLL_POWERDOWN" bitrange="22:22">
-         <value name="PLL_OFF" value="0x01" />
-         <value name="PLL_ON" value="0x00" />
-      </field>
-      <field name="DSP_PLL_CLKR" bitrange="21:16"></field>
-      <field name="DSP_PLL_CLKF" bitrange="15:4"></field>
-      <field name="DSP_PLL_CLKOD" bitrange="3:1"></field>
-      <field name="DSP_PLL_BYPASS" bitrange="0:0">
-        <value name="ENABLE" value="0x01" />
-        <value name="DISABLE" value="0x00" />
-      </field>
-    </reg>
-    <reg name="SCU_PLLCON3" addr="0x10">
-      <field name="CODEC_PLL_TEST_CONTROL" bitrange="25:25">
-        <value name="TEST" value="0x01" />
-        <value name="NORMAL" value="0x00" />
-      </field>
-      <field name="CODEC_PLL_SATURATION" bitrange="24:24">
-        <value name="ENABLE" value="0x01" />
-        <value name="DISABLE" value="0x00" />
-      </field>
-      <field name="CODEC_PLL_FAST_LOCK" bitrange="23:23">
-        <value name="ENABLE" value="0x01" />
-        <value name="DISABLE" value="0x00" />
-      </field>
-      <field name="CODEC_PLL_POWERDOWN" bitrange="22:22">
-         <value name="PLL_OFF" value="0x01" />
-         <value name="PLL_ON" value="0x00" />
-      </field>
-      <field name="CODEC_PLL_CLKR" bitrange="21:16"></field>
-      <field name="CODEC_PLL_CLKF" bitrange="15:4"></field>
-      <field name="CODEC_PLL_CLKOD" bitrange="3:1"></field>
-      <field name="CODEC_PLL_BYPASS" bitrange="0:0">
-        <value name="ENABLE" value="0x01" />
-        <value name="DISABLE" value="0x00" />
-      </field>
-    </reg>
-    <reg name="SCU_DIVCON1" addr="0x14">
-      <field name="USB_PHY_CLK" bitrange="31:31">
-        <value name="12MHz" value="0x01" />
-        <value name="24MHz" value="0x00" />
-      </field>
-      <field name="VIP_SENSOR_CLK" bitrange="30:29">
-        <value name="27MHz" value="0x02" />
-        <value name="48MHz" value="0x01" />
-        <value name="24MHz" value="0x00" />
-      </field>
-      <field name="LCDC_CLK" bitrange="28:28">
-        <value name="LCDC_CLK_DIV_OUT" value="0x01" />
-        <value name="EXT_SOC_27MHz" value="0x00" />
-      </field>
-      <field name="LCDC_CLK_DIV" bitrange="27:20"></field>
-      <field name="LCDC_CLK_DIV_SRC" bitrange="19:18">
-        <value name="CODEC_PLL" value="0x02" />
-        <value name="DSP_PLL" value="0x01" />
-        <value name="ARM_PLL" value="0x00" />
-      </field>
-      <field name="LSADC_CLK_DIV" bitrange="17:10"></field>
-      <field name="CODEC_CLK_SRC" bitrange="9:9">
-        <value name="12MHz_OSC" value="0x01" />
-        <value name="CODEC_CLK_DIV_OUT" value="0x00" />
-      </field>
-      <field name="CODEC_CLK_DIV" bitrange="8:5"></field>
-      <field name="PCLK_CLK_DIV" bitrange="4:3">
-        <value name="HCLK/PCLK_4:1" value="0x02" />
-        <value name="HCLK/PCLK_2:1" value="0x01" />
-        <value name="HCLK/PCLK_1:1" value="0x00" />
-      </field>
-      <field name="ARM_CLK_DIV" bitrange="2:2">
-        <value name="ARMPLL/ARMCLK_2:1" value="0x01" />
-        <value name="ARMPLL/ARMCLK_1:1" value="0x00" />
-      </field>
-      <field name="DSP_SLOW_MODE" bitrange="1:1">
-        <value name="ENABLE" value="0x01" />
-        <value name="DISABLE" value="0x00" />
-      </field>
-      <field name="ARM_SLOW_MODE" bitrange="0:0">
-        <value name="ENABLE" value="0x01" />
-        <value name="DISABLE" value="0x00" />
-      </field>
-    </reg>
-    <reg name="SCU_CLKCFG" addr="0x18">
-      <field name="WDT_PCLK" bitrange="31:31">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="RTC_PCLK" bitrange="30:30">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="PWM_PCLK" bitrange="29:29">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="TIMER_PCLK" bitrange="28:28">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="GPIO_PCLK" bitrange="27:27">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="HSADC_PCLK" bitrange="26:26">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="HSADC_HCLK" bitrange="25:25">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="LSADC_CLK" bitrange="24:24">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="LSADC_PCLK" bitrange="23:23">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="SD_CLK" bitrange="22:22">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="SPI_CLK" bitrange="21:21">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="I2C_CLK" bitrange="20:20">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="UART1_CLK" bitrange="19:19">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="UART0_CLK" bitrange="18:18">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="I2S_PCLK" bitrange="17:17">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="I2S_CLK" bitrange="16:16">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="VIP_CLK" bitrange="15:15">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="VIP_HCLK" bitrange="14:14">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="LCDC_CLK" bitrange="13:13">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="LCDC_HCLK" bitrange="12:12">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="IRAM_HCLK" bitrange="11:11">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="A2A_HCLK" bitrange="10:10">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="NANDC_HCLK" bitrange="9:9">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
-      </field>
-      <field name="UDC_CLK" bitrange="6:6">
-        <value name="GATE" value="0x01" />
-        <value name="UNGATE" value="0x00" />
+      <reg name="ID" addr="0x00">
+        <field name="SOC_ID" bitrange="31:0">
+          <value name="REVISION_A" value="0xa1000604" />
+          <value name="REVISION_B" value="0xa100027b" />
+        </field>
+      </reg>
+      <reg name="REMAP" addr="0x04">
+        <field name="MEM_REMAP" bitrange="31:0">
+          <value name="IRAM_0x000000" value="0xdeadbeef" />
+          <value name="ROM_0x000000" value="0x00000000" />
+        </field>
+      </reg>
+      <reg name="PLLCON1" addr="0x08">
+        <field name="ARM_PLL_TEST_CONTROL" bitrange="25:25">
+          <value name="TEST" value="0x01" />
+          <value name="NORMAL" value="0x00" />
+        </field>
+        <field name="ARM_PLL_SATURATION" bitrange="24:24">
+          <value name="ENABLE" value="0x01" />
+          <value name="DISABLE" value="0x00" />
+        </field>
+        <field name="ARM_PLL_FAST_LOCK" bitrange="23:23">
+          <value name="ENABLE" value="0x01" />
+          <value name="DISABLE" value="0x00" />
+        </field>
+        <field name="ARM_PLL_POWERDOWN" bitrange="22:22">
+          <value name="PLL_OFF" value="0x01" />
+          <value name="PLL_ON" value="0x00" />
+        </field>
+        <field name="ARM_PLL_CLKR" bitrange="21:16"></field>
+        <field name="ARM_PLL_CLKF" bitrange="15:4"></field>
+        <field name="ARM_PLL_CLKOD" bitrange="3:1"></field>
+        <field name="ARM_PLL_BYPASS" bitrange="0:0">
+          <value name="ENABLE" value="0x01" />
+          <value name="DISABLE" value="0x00" />
+        </field>
+      </reg>
+      <reg name="PLLCON2" addr="0x0c">
+        <field name="DSP_PLL_TEST_CONTROL" bitrange="25:25">
+          <value name="TEST" value="0x01" />
+          <value name="NORMAL" value="0x00" />
+        </field>
+        <field name="DSP_PLL_SATURATION" bitrange="24:24">
+          <value name="ENABLE" value="0x01" />
+          <value name="DISABLE" value="0x00" />
+        </field>
+        <field name="DSP_PLL_FAST_LOCK" bitrange="23:23">
+          <value name="ENABLE" value="0x01" />
+          <value name="DISABLE" value="0x00" />
+        </field>
+        <field name="DSP_PLL_POWERDOWN" bitrange="22:22">
+          <value name="PLL_OFF" value="0x01" />
+          <value name="PLL_ON" value="0x00" />
+        </field>
+        <field name="DSP_PLL_CLKR" bitrange="21:16"></field>
+        <field name="DSP_PLL_CLKF" bitrange="15:4"></field>
+        <field name="DSP_PLL_CLKOD" bitrange="3:1"></field>
+        <field name="DSP_PLL_BYPASS" bitrange="0:0">
+          <value name="ENABLE" value="0x01" />
+          <value name="DISABLE" value="0x00" />
+        </field>
+      </reg>
+      <reg name="PLLCON3" addr="0x10">
+        <field name="CODEC_PLL_TEST_CONTROL" bitrange="25:25">
+          <value name="TEST" value="0x01" />
+          <value name="NORMAL" value="0x00" />
+        </field>
+        <field name="CODEC_PLL_SATURATION" bitrange="24:24">
+          <value name="ENABLE" value="0x01" />
+          <value name="DISABLE" value="0x00" />
+        </field>
+        <field name="CODEC_PLL_FAST_LOCK" bitrange="23:23">
+          <value name="ENABLE" value="0x01" />
+          <value name="DISABLE" value="0x00" />
+        </field>
+        <field name="CODEC_PLL_POWERDOWN" bitrange="22:22">
+           <value name="PLL_OFF" value="0x01" />
+           <value name="PLL_ON" value="0x00" />
+        </field>
+        <field name="CODEC_PLL_CLKR" bitrange="21:16"></field>
+        <field name="CODEC_PLL_CLKF" bitrange="15:4"></field>
+        <field name="CODEC_PLL_CLKOD" bitrange="3:1"></field>
+        <field name="CODEC_PLL_BYPASS" bitrange="0:0">
+          <value name="ENABLE" value="0x01" />
+          <value name="DISABLE" value="0x00" />
+        </field>
+      </reg>
+      <reg name="DIVCON1" addr="0x14">
+        <field name="USB_PHY_CLK" bitrange="31:31">
+          <value name="12MHz" value="0x01" />
+          <value name="24MHz" value="0x00" />
+        </field>
+        <field name="VIP_SENSOR_CLK" bitrange="30:29">
+          <value name="27MHz" value="0x02" />
+          <value name="48MHz" value="0x01" />
+          <value name="24MHz" value="0x00" />
+        </field>
+        <field name="LCDC_CLK" bitrange="28:28">
+          <value name="LCDC_CLK_DIV_OUT" value="0x01" />
+          <value name="EXT_SOC_27MHz" value="0x00" />
+        </field>
+        <field name="LCDC_CLK_DIV" bitrange="27:20"></field>
+        <field name="LCDC_CLK_DIV_SRC" bitrange="19:18">
+          <value name="CODEC_PLL" value="0x02" />
+          <value name="DSP_PLL" value="0x01" />
+          <value name="ARM_PLL" value="0x00" />
+        </field>
+        <field name="LSADC_CLK_DIV" bitrange="17:10"></field>
+        <field name="CODEC_CLK_SRC" bitrange="9:9">
+          <value name="12MHz_OSC" value="0x01" />
+          <value name="CODEC_CLK_DIV_OUT" value="0x00" />
+        </field>
+        <field name="CODEC_CLK_DIV" bitrange="8:5"></field>
+        <field name="PCLK_CLK_DIV" bitrange="4:3">
+          <value name="HCLK/PCLK_4:1" value="0x02" />
+          <value name="HCLK/PCLK_2:1" value="0x01" />
+          <value name="HCLK/PCLK_1:1" value="0x00" />
+        </field>
+        <field name="ARM_CLK_DIV" bitrange="2:2">
+          <value name="ARMPLL/ARMCLK_2:1" value="0x01" />
+          <value name="ARMPLL/ARMCLK_1:1" value="0x00" />
+        </field>
+        <field name="DSP_SLOW_MODE" bitrange="1:1">
+          <value name="ENABLE" value="0x01" />
+          <value name="DISABLE" value="0x00" />
+        </field>
+        <field name="ARM_SLOW_MODE" bitrange="0:0">
+          <value name="ENABLE" value="0x01" />
+          <value name="DISABLE" value="0x00" />
+        </field>
+      </reg>
+      <reg name="CLKCFG" addr="0x18">
+        <field name="WDT_PCLK" bitrange="31:31">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="RTC_PCLK" bitrange="30:30">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="PWM_PCLK" bitrange="29:29">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="TIMER_PCLK" bitrange="28:28">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="GPIO_PCLK" bitrange="27:27">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="HSADC_PCLK" bitrange="26:26">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="HSADC_HCLK" bitrange="25:25">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="LSADC_CLK" bitrange="24:24">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="LSADC_PCLK" bitrange="23:23">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="SD_CLK" bitrange="22:22">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="SPI_CLK" bitrange="21:21">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="I2C_CLK" bitrange="20:20">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="UART1_CLK" bitrange="19:19">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="UART0_CLK" bitrange="18:18">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="I2S_PCLK" bitrange="17:17">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="I2S_CLK" bitrange="16:16">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="VIP_CLK" bitrange="15:15">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="VIP_HCLK" bitrange="14:14">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="LCDC_CLK" bitrange="13:13">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="LCDC_HCLK" bitrange="12:12">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="IRAM_HCLK" bitrange="11:11">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="A2A_HCLK" bitrange="10:10">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="NANDC_HCLK" bitrange="9:9">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
+        </field>
+        <field name="UDC_CLK" bitrange="6:6">
+          <value name="GATE" value="0x01" />
+          <value name="UNGATE" value="0x00" />
       </field>
       <field name="UHC_CLK" bitrange="5:5">
         <value name="GATE" value="0x01" />
@@ -468,7 +400,7 @@ KIND, either express or implied.
         <value name="UNGATE" value="0x00" />
       </field>
     </reg>
-    <reg name="SCU_RSTCFG" addr="0x1c">
+    <reg name="RSTCFG" addr="0x1c">
       <field name="ARM_RST" bitrange="12:12">
         <value name="ASSERT" value="0x01" />
         <value name="DEASSERT" value="0x00" />
@@ -522,7 +454,7 @@ KIND, either express or implied.
         <value name="DEASSERT" value="0x00" />
       </field>
     </reg>
-    <reg name="SCU_PWM" addr="0x20">
+    <reg name="PWM" addr="0x20">
       <field name="PLL_LOCK_PERIOD" bitrange="31:16"></field>
       <field name="EXT_WAKEUP_PIN_POLARITY" bitrange="6:6">
         <value name="NEGATIVE" value="0x01" />
@@ -545,8 +477,8 @@ KIND, either express or implied.
         <value name="NORMAL" value="0x00" />
       </field>
     </reg>
-    <reg name="SCU_CPUPD" addr="0x24"></reg>
-    <reg name="SCU_CHIPCFG" addr="0x28">
+    <reg name="CPUPD" addr="0x24"></reg>
+    <reg name="CHIPCFG" addr="0x28">
       <field name="NOR_FLASH_BUSWIDTH" bitrange="19:19">
         <value name="8BIT" value="0x01" />
         <value name="16BIT" value="0x00" />
@@ -563,7 +495,7 @@ KIND, either express or implied.
         <value name="USB_PHY_UDC" value="0x00" />
       </field>
     </reg>
-    <reg name="SCU_STATUS" addr="0x2c">
+    <reg name="STATUS" addr="0x2c">
       <field name="DSPSYSCLKVALID" bitrange="4:4">
         <value name="VALID" value="0x01" />
         <value name="UNSTABLE" value="0x00" />
@@ -585,7 +517,7 @@ KIND, either express or implied.
         <value name="UNSTABLE" value="0x00" />
       </field>
     </reg>
-    <reg name="SCU_IOMUXA_CON" addr="0x30">
+    <reg name="IOMUXA_CON" addr="0x30">
       <field name="I2S_CODEC_EXT_SEL" bitrange="19:19">
         <value name="PIN" value="0x01" />
         <value name="INTERNAL_CODEC" value="0x00" />
@@ -646,7 +578,7 @@ KIND, either express or implied.
         <value name="GPIOA0" value="0x00" />
       </field>
     </reg>
-    <reg name="SCU_IOMUXB_CON" addr="0x34">
+    <reg name="IOMUXB_CON" addr="0x34">
       <field name="VIP_HSADC_SEL" bitrange="22:22">
         <value name="HSADC" value="0x01" />
         <value name="VIP" value="0x00" />
@@ -739,50 +671,50 @@ KIND, either express or implied.
   </dev>
   <dev name="I2C" long_name="I2C controller" desc="I2C controller" version="1.0">
     <addr name="I2C" addr="0x18020000" />
-    <reg name="I2C_MTXR" addr="0x00"></reg>
-    <reg name="I2C_MRXR" addr="0x04"></reg>
-    <reg name="I2C_STXR" addr="0x08"></reg>
-    <reg name="I2C_SRXR" addr="0x0c"></reg>
-    <reg name="I2C_SADDR" addr="0x10"></reg>
-    <reg name="I2C_IER" addr="0x14"></reg>
-    <reg name="I2C_ISR" addr="0x18"></reg>
-    <reg name="I2C_LCMR" addr="0x1c"></reg>
-    <reg name="I2C_LSR" addr="0x20"></reg>
-    <reg name="I2C_CONR" addr="0x24"></reg>
-    <reg name="I2C_OPR" addr="0x28"></reg>
+      <reg name="MTXR" addr="0x00"></reg>
+      <reg name="MRXR" addr="0x04"></reg>
+      <reg name="STXR" addr="0x08"></reg>
+      <reg name="SRXR" addr="0x0c"></reg>
+      <reg name="SADDR" addr="0x10"></reg>
+      <reg name="IER" addr="0x14"></reg>
+      <reg name="ISR" addr="0x18"></reg>
+      <reg name="LCMR" addr="0x1c"></reg>
+      <reg name="LSR" addr="0x20"></reg>
+      <reg name="CONR" addr="0x24"></reg>
+      <reg name="OPR" addr="0x28"></reg>
   </dev>
   <dev name="SD" long_name="SD controller" desc="SD controller" version="1.0">
     <addr name="SD" addr="0x18024000" />
-    <reg name="MMU_CTRL" addr="0x00"></reg>
-    <reg name="MMU_PNRI" addr="0x04"></reg>
-    <reg name="CUR_PNRI" addr="0x08"></reg>
-    <reg name="MMU_PNRII" addr="0x0c"></reg>
-    <reg name="CUR_PNRII" addr="0x10"></reg>
-    <reg name="MMU_ADDR" addr="0x14"></reg>
-    <reg name="CUR_ADDR" addr="0x18"></reg>
-    <reg name="MMU_DATA" addr="0x1c"></reg>
-    <reg name="SD_CTRL" addr="0x20"></reg>
-    <reg name="SD_INT" addr="0x24"></reg>
-    <reg name="SD_CARD" addr="0x28"></reg>
-    <reg name="SD_CMDREST" addr="0x30"></reg>
-    <reg name="SD_CMDRES" addr="0x34"></reg>
-    <reg name="SD_DATAT" addr="0x3c"></reg>
-    <reg name="SD_CMD" addr="0x40"></reg>
-    <reg name="SD_RES3" addr="0x44"></reg>
-    <reg name="SD_RES2" addr="0x48"></reg>
-    <reg name="SD_RES1" addr="0x4c"></reg>
-    <reg name="SD_RES0" addr="0x50"></reg>
+      <reg name="MMU_CTRL" addr="0x00"></reg>
+      <reg name="MMU_PNRI" addr="0x04"></reg>
+      <reg name="CUR_PNRI" addr="0x08"></reg>
+      <reg name="MMU_PNRII" addr="0x0c"></reg>
+      <reg name="CUR_PNRII" addr="0x10"></reg>
+      <reg name="MMU_ADDR" addr="0x14"></reg>
+      <reg name="CUR_ADDR" addr="0x18"></reg>
+      <reg name="MMU_DATA" addr="0x1c"></reg>
+      <reg name="CTRL" addr="0x20"></reg>
+      <reg name="INT" addr="0x24"></reg>
+      <reg name="CARD" addr="0x28"></reg>
+      <reg name="CMDREST" addr="0x30"></reg>
+      <reg name="CMDRES" addr="0x34"></reg>
+      <reg name="DATAT" addr="0x3c"></reg>
+      <reg name="CMD" addr="0x40"></reg>
+      <reg name="RES3" addr="0x44"></reg>
+      <reg name="RES2" addr="0x48"></reg>
+      <reg name="RES1" addr="0x4c"></reg>
+      <reg name="RES0" addr="0x50"></reg>
   </dev>
   <dev name="I2S" long_name="I2S controller" desc="I2S controller" version="1.0">
     <addr name="I2S" addr="0x18028000" />
-    <reg name="I2S_OPR" addr="0x00"></reg>
-    <reg name="I2S_TXR" addr="0x04"></reg>
-    <reg name="I2S_RXR" addr="0x08"></reg>
-    <reg name="I2S_TXCTL" addr="0x0c"></reg>
-    <reg name="I2S_RXCTL" addr="0x10"></reg>
-    <reg name="I2S_FIFOSTS" addr="0x14"></reg>
-    <reg name="I2S_IER" addr="0x18"></reg>
-    <reg name="I2S_ISR" addr="0x1c"></reg>
+      <reg name="OPR" addr="0x00"></reg>
+      <reg name="TXR" addr="0x04"></reg>
+      <reg name="RXR" addr="0x08"></reg>
+      <reg name="TXCTL" addr="0x0c"></reg>
+      <reg name="RXCTL" addr="0x10"></reg>
+      <reg name="FIFOSTS" addr="0x14"></reg>
+      <reg name="IER" addr="0x18"></reg>
+      <reg name="ISR" addr="0x1c"></reg>
   </dev>
   <dev name="PWM" long_name="PWM timer" desc="PWM timer" version="1.0">
     <addr name="PWM0" addr="0x1802c000" />
@@ -791,123 +723,111 @@ KIND, either express or implied.
     <addr name="PWM3" addr="0x1802c030" />
     <reg name="PWMTn_CNTR">
       <formula string="n*0x10" />
-      <addr name="PWMT0_CNTR" addr="0x00" />
-      <addr name="PWMT1_CNTR" addr="0x10" />
-      <addr name="PWMT2_CNTR" addr="0x20" />
-      <addr name="PWMT3_CNTR" addr="0x30" />
+      <addr name="CNTR" addr="0x00" />
     </reg>
     <reg name="PWMTn_HRC">
       <formula string="n*0x10 + 0x04" />
-      <addr name="PWMT0_HRC" addr="0x04" />
-      <addr name="PWMT1_HRC" addr="0x14" />
-      <addr name="PWMT2_HRC" addr="0x24" />
-      <addr name="PWMT3_HRC" addr="0x34" />
+      <addr name="HRC" addr="0x04" />
     </reg>
     <reg name="PWMTn_LRC">
       <formula string="n*0x10 + 0x08" />
-      <addr name="PWMT0_LRC" addr="0x08" />
-      <addr name="PWMT1_LRC" addr="0x18" />
-      <addr name="PWMT2_LRC" addr="0x28" />
-      <addr name="PWMT3_LRC" addr="0x38" />
+      <addr name="LRC" addr="0x08" />
     </reg>
     <reg name="PWMTn_CTRL">
       <formula string="n*0x10 + 0x0c" />
-      <addr name="PWMT0_CTRL" addr="0x0c" />
-      <addr name="PWMT1_CTRL" addr="0x1c" />
-      <addr name="PWMT2_CTRL" addr="0x2c" />
-      <addr name="PWMT3_CTRL" addr="0x3c" />
+      <addr name="CTRL" addr="0x0c" />
     </reg>
   </dev>
   <dev name="ADC" long_name="ADC" desc="4 channels 10-bit SAR A/D converter" version="1.0">
     <addr name="ADC" addr="0x18030000" />
-    <reg name="ADC_DATA" addr="0x00"></reg>
-    <reg name="ADC_STAT" addr="0x04"></reg>
-    <reg name="ADC_CTRL" addr="0x08"></reg>
+    <reg name="DATA" addr="0x00"></reg>
+    <reg name="STAT" addr="0x04"></reg>
+    <reg name="CTRL" addr="0x08"></reg>
   </dev>
   <dev name="GPIO" long_name="GPIO" desc="GPIO" version="1.0">
     <addr name="GPIO1" addr="0x18038000" />
-    <reg name="GPIO_PEDR" addr="0x00"></reg>
-    <reg name="GPIO_PECON" addr="0x04"></reg>
-    <reg name="GPIO_PFDR" addr="0x08"></reg>
-    <reg name="GPIO_PFCON" addr="0x0c"></reg>
-    <reg name="GPIO1_TEST" addr="0x20"></reg>
-    <reg name="GPIO_IEE" addr="0x24"></reg>
-    <reg name="GPIO_IEF" addr="0x28"></reg>
-    <reg name="GPIO_ISE" addr="0x34"></reg>
-    <reg name="GPIO_ISF" addr="0x38"></reg>
-    <reg name="GPIO_IBEE" addr="0x44"></reg>
-    <reg name="GPIO_IBEF" addr="0x48"></reg>
-    <reg name="GPIO_IEVE" addr="0x54"></reg>
-    <reg name="GPIO_IEVF" addr="0x58"></reg>
-    <reg name="GPIO_ICE" addr="0x64"></reg>
-    <reg name="GPIO_ICF" addr="0x68"></reg>
-    <reg name="GPIO1_ISR" addr="0x74"></reg>
+    <reg name="PEDR" addr="0x00"></reg>
+    <reg name="PECON" addr="0x04"></reg>
+    <reg name="PFDR" addr="0x08"></reg>
+    <reg name="PFCON" addr="0x0c"></reg>
+    <reg name="_TEST" addr="0x20"></reg>
+    <reg name="IEE" addr="0x24"></reg>
+    <reg name="IEF" addr="0x28"></reg>
+    <reg name="ISE" addr="0x34"></reg>
+    <reg name="ISF" addr="0x38"></reg>
+    <reg name="IBEE" addr="0x44"></reg>
+    <reg name="IBEF" addr="0x48"></reg>
+    <reg name="IEVE" addr="0x54"></reg>
+    <reg name="IEVF" addr="0x58"></reg>
+    <reg name="ICE" addr="0x64"></reg>
+    <reg name="ICF" addr="0x68"></reg>
+    <reg name="ISR" addr="0x74"></reg>
   </dev>
   <dev name="INTC" long_name="Interrupt controller" desc="Interrupt controller" version="1.0">
     <addr name="INTC" addr="0x18080000" />
     <reg name="INTC_SCRn">
       <formula string="n*0x04" />
-      <addr name="INTC_SCR0" addr="0x00" />
-      <addr name="INTC_SCR1" addr="0x04" />
-      <addr name="INTC_SCR2" addr="0x08" />
-      <addr name="INTC_SCR3" addr="0x0c" />
-      <addr name="INTC_SCR4" addr="0x10" />
-      <addr name="INTC_SCR5" addr="0x14" />
-      <addr name="INTC_SCR6" addr="0x18" />
-      <addr name="INTC_SCR7" addr="0x1c" />
-      <addr name="INTC_SCR8" addr="0x20" />
-      <addr name="INTC_SCR9" addr="0x24" />
-      <addr name="INTC_SCR10" addr="0x28" />
-      <addr name="INTC_SCR11" addr="0x2c" />
-      <addr name="INTC_SCR12" addr="0x30" />
-      <addr name="INTC_SCR13" addr="0x34" />
-      <addr name="INTC_SCR14" addr="0x38" />
-      <addr name="INTC_SCR15" addr="0x3c" />
-      <addr name="INTC_SCR16" addr="0x40" />
-      <addr name="INTC_SCR17" addr="0x44" />
-      <addr name="INTC_SCR18" addr="0x48" />
-      <addr name="INTC_SCR19" addr="0x4c" />
-      <addr name="INTC_SCR20" addr="0x50" />
-      <addr name="INTC_SCR21" addr="0x54" />
-      <addr name="INTC_SCR22" addr="0x58" />
-      <addr name="INTC_SCR23" addr="0x5c" />
-      <addr name="INTC_SCR24" addr="0x60" />
-      <addr name="INTC_SCR25" addr="0x64" />
-      <addr name="INTC_SCR26" addr="0x68" />
-      <addr name="INTC_SCR27" addr="0x6c" />
-      <addr name="INTC_SCR28" addr="0x70" />
-      <addr name="INTC_SCR29" addr="0x74" />
-      <addr name="INTC_SCR30" addr="0x78" />
-      <addr name="INTC_SCR31" addr="0x7c" />
+      <addr name="SCR0" addr="0x00" />
+      <addr name="SCR1" addr="0x04" />
+      <addr name="SCR2" addr="0x08" />
+      <addr name="SCR3" addr="0x0c" />
+      <addr name="SCR4" addr="0x10" />
+      <addr name="SCR5" addr="0x14" />
+      <addr name="SCR6" addr="0x18" />
+      <addr name="SCR7" addr="0x1c" />
+      <addr name="SCR8" addr="0x20" />
+      <addr name="SCR9" addr="0x24" />
+      <addr name="SCR10" addr="0x28" />
+      <addr name="SCR11" addr="0x2c" />
+      <addr name="SCR12" addr="0x30" />
+      <addr name="SCR13" addr="0x34" />
+      <addr name="SCR14" addr="0x38" />
+      <addr name="SCR15" addr="0x3c" />
+      <addr name="SCR16" addr="0x40" />
+      <addr name="SCR17" addr="0x44" />
+      <addr name="SCR18" addr="0x48" />
+      <addr name="SCR19" addr="0x4c" />
+      <addr name="SCR20" addr="0x50" />
+      <addr name="SCR21" addr="0x54" />
+      <addr name="SCR22" addr="0x58" />
+      <addr name="SCR23" addr="0x5c" />
+      <addr name="SCR24" addr="0x60" />
+      <addr name="SCR25" addr="0x64" />
+      <addr name="SCR26" addr="0x68" />
+      <addr name="SCR27" addr="0x6c" />
+      <addr name="SCR28" addr="0x70" />
+      <addr name="SCR29" addr="0x74" />
+      <addr name="SCR30" addr="0x78" />
+      <addr name="SCR31" addr="0x7c" />
     </reg>
-    <reg name="INTC_ISR" addr="0x104"></reg>
-    <reg name="INTC_IPR" addr="0x108"></reg>
-    <reg name="INTC_IMR" addr="0x10c"></reg>
-    <reg name="INTC_IECR" addr="0x114"></reg>
-    <reg name="INTC_ICCR" addr="0x118"></reg>
-    <reg name="INTC_ISCR" addr="0x11c"></reg>
-    <reg name="INTC_TEST" addr="0x124"></reg>
+    <reg name="ISR" addr="0x104"></reg>
+    <reg name="IPR" addr="0x108"></reg>
+    <reg name="IMR" addr="0x10c"></reg>
+    <reg name="IECR" addr="0x114"></reg>
+    <reg name="ICCR" addr="0x118"></reg>
+    <reg name="ISCR" addr="0x11c"></reg>
+    <reg name="TEST" addr="0x124"></reg>
   </dev>
   <dev name="ARB" long_name="AHB bus arbiter" desc="AHB bus arbiter" version="1.0">
     <addr name="ARB" addr="0x18084000" />
-    <reg name="ARB_MODE" addr="0x00"></reg>
-    <reg name="ARB_PRIOn">
+    <reg name="MODE" addr="0x00"></reg>
+    <reg name="PRIOn">
       <formula string="n*0x04 + 0x04" />
-      <addr name="ARB_PRIO1" addr="0x04" />
-      <addr name="ARB_PRIO2" addr="0x08" />
-      <addr name="ARB_PRIO3" addr="0x0c" />
-      <addr name="ARB_PRIO4" addr="0x10" />
-      <addr name="ARB_PRIO5" addr="0x14" />
-      <addr name="ARB_PRIO6" addr="0x18" />
-      <addr name="ARB_PRIO7" addr="0x1c" />
-      <addr name="ARB_PRIO8" addr="0x20" />
-      <addr name="ARB_PRIO9" addr="0x24" />
-      <addr name="ARB_PRIO10" addr="0x28" />
-      <addr name="ARB_PRIO11" addr="0x2c" />
-      <addr name="ARB_PRIO12" addr="0x30" />
-      <addr name="ARB_PRIO13" addr="0x34" />
-      <addr name="ARB_PRIO14" addr="0x38" />
-      <addr name="ARB_PRIO15" addr="0x3c" />
+      <addr name="PRIO1" addr="0x04" />
+      <addr name="PRIO2" addr="0x08" />
+      <addr name="PRIO3" addr="0x0c" />
+      <addr name="PRIO4" addr="0x10" />
+      <addr name="PRIO5" addr="0x14" />
+      <addr name="PRIO6" addr="0x18" />
+      <addr name="PRIO7" addr="0x1c" />
+      <addr name="PRIO8" addr="0x20" />
+      <addr name="PRIO9" addr="0x24" />
+      <addr name="PRIO10" addr="0x28" />
+      <addr name="PRIO11" addr="0x2c" />
+      <addr name="PRIO12" addr="0x30" />
+      <addr name="PRIO13" addr="0x34" />
+      <addr name="PRIO14" addr="0x38" />
+      <addr name="PRIO15" addr="0x3c" />
     </reg>
   </dev>
   <dev name="MAILBOX" long_name="CPU-DSP mailbox" desc="CPU-DSP mailbox" version="1.0">
@@ -946,62 +866,62 @@ KIND, either express or implied.
   </dev>
   <dev name="HDMA" long_name="AHB DMA" desc="AHB DMA" version="1.0">
     <addr name="HDMA" addr="0x18090000" />
-    <reg name="HDMA_CON0" addr="0x00"></reg>
-    <reg name="HDMA_CON1" addr="0x04"></reg>
-    <reg name="HDMA_ISRC0" addr="0x08"></reg>
-    <reg name="HDMA_IDST0" addr="0x0C"></reg>
-    <reg name="HDMA_ICNT0" addr="0x10"></reg>
-    <reg name="HDMA_ISRC1" addr="0x14"></reg>
-    <reg name="HDMA_IDST1" addr="0x18"></reg>
-    <reg name="HDMA_ICNT1" addr="0x1C"></reg>
-    <reg name="HDMA_CSRC0" addr="0x20"></reg>
-    <reg name="HDMA_CDST0" addr="0x24"></reg>
-    <reg name="HDMA_CCNT0" addr="0x28"></reg>
-    <reg name="HDMA_CSRC1" addr="0x2C"></reg>
-    <reg name="HDMA_CDST1" addr="0x30"></reg>
-    <reg name="HDMA_CCNT1" addr="0x34"></reg>
-    <reg name="HDMA_ISR" addr="0x38"></reg>
-    <reg name="HDMA_DSR" addr="0x3C"></reg>
-    <reg name="HDMA_ISCNT0" addr="0x40"></reg>
-    <reg name="HDMA_IPNCNTD0" addr="0x44"></reg>
-    <reg name="HDMA_IADDR_BS0" addr="0x48"></reg>
-    <reg name="HDMA_ISCNT1" addr="0x4C"></reg>
-    <reg name="HDMA_IPNCNTD1" addr="0x50"></reg>
-    <reg name="HDMA_IADDR_BS1" addr="0x54"></reg>
-    <reg name="HDMA_CSCNT0" addr="0x58"></reg>
-    <reg name="HDMA_CPNCNTD0" addr="0x5C"></reg>
-    <reg name="HDMA_CADDR_BS0" addr="0x60"></reg>
-    <reg name="HDMA_CSCNT1" addr="0x64"></reg>
-    <reg name="HDMA_CPNCNTD1" addr="0x68"></reg>
-    <reg name="HDMA_CADDR_BS1" addr="0x6C"></reg>
-    <reg name="HDMA_PACNT0" addr="0x70"></reg>
-    <reg name="HDMA_PACNT1" addr="0x74"></reg>
+    <reg name="CON0" addr="0x00"></reg>
+    <reg name="CON1" addr="0x04"></reg>
+    <reg name="ISRC0" addr="0x08"></reg>
+    <reg name="IDST0" addr="0x0C"></reg>
+    <reg name="ICNT0" addr="0x10"></reg>
+    <reg name="ISRC1" addr="0x14"></reg>
+    <reg name="IDST1" addr="0x18"></reg>
+    <reg name="ICNT1" addr="0x1C"></reg>
+    <reg name="CSRC0" addr="0x20"></reg>
+    <reg name="CDST0" addr="0x24"></reg>
+    <reg name="CCNT0" addr="0x28"></reg>
+    <reg name="CSRC1" addr="0x2C"></reg>
+    <reg name="CDST1" addr="0x30"></reg>
+    <reg name="CCNT1" addr="0x34"></reg>
+    <reg name="ISR" addr="0x38"></reg>
+    <reg name="DSR" addr="0x3C"></reg>
+    <reg name="ISCNT0" addr="0x40"></reg>
+    <reg name="IPNCNTD0" addr="0x44"></reg>
+    <reg name="IADDR_BS0" addr="0x48"></reg>
+    <reg name="ISCNT1" addr="0x4C"></reg>
+    <reg name="IPNCNTD1" addr="0x50"></reg>
+    <reg name="IADDR_BS1" addr="0x54"></reg>
+    <reg name="CSCNT0" addr="0x58"></reg>
+    <reg name="CPNCNTD0" addr="0x5C"></reg>
+    <reg name="CADDR_BS0" addr="0x60"></reg>
+    <reg name="CSCNT1" addr="0x64"></reg>
+    <reg name="CPNCNTD1" addr="0x68"></reg>
+    <reg name="CADDR_BS1" addr="0x6C"></reg>
+    <reg name="PACNT0" addr="0x70"></reg>
+    <reg name="PACNT1" addr="0x74"></reg>
   </dev>
   <dev name="A2A_DMA" long_name="AHB-to-AHB bridge" desc="AHB-to-AHB bridge with DMA" version="1.0">
     <addr name="A2A_DMA" addr="0x18094000" />
-    <reg name="A2A_CON0" addr="0x00"></reg>
-    <reg name="A2A_ISRC0" addr="0x04"></reg>
-    <reg name="A2A_IDST0" addr="0x08"></reg>
-    <reg name="A2A_ICNT0" addr="0x0C"></reg>
-    <reg name="A2A_CSRC0" addr="0x10"></reg>
-    <reg name="A2A_CDST0" addr="0x14"></reg>
-    <reg name="A2A_CCNT0" addr="0x18"></reg>
-    <reg name="A2A_CON1" addr="0x1C"></reg>
-    <reg name="A2A_ISRC1" addr="0x20"></reg>
-    <reg name="A2A_IDST1" addr="0x24"></reg>
-    <reg name="A2A_ICNT1" addr="0x28"></reg>
-    <reg name="A2A_CSRC1" addr="0x2C"></reg>
-    <reg name="A2A_CDST1" addr="0x30"></reg>
-    <reg name="A2A_CCNT1" addr="0x34"></reg>
-    <reg name="A2A_INT_STS" addr="0x38"></reg>
-    <reg name="A2A_DMA_STS" addr="0x3C"></reg>
-    <reg name="A2A_ERR_ADR0" addr="0x40"></reg>
-    <reg name="A2A_ERR_OP0" addr="0x44"></reg>
-    <reg name="A2A_ERR_ADR1" addr="0x48"></reg>
-    <reg name="A2A_ERR_OP1" addr="0x4C"></reg>
-    <reg name="A2A_LCNT0" addr="0x50"></reg>
-    <reg name="A2A_LCNT1" addr="0x54"></reg>
-    <reg name="A2A_DOMAIN" addr="0x58"></reg>
+    <reg name="CON0" addr="0x00"></reg>
+    <reg name="ISRC0" addr="0x04"></reg>
+    <reg name="IDST0" addr="0x08"></reg>
+    <reg name="ICNT0" addr="0x0C"></reg>
+    <reg name="CSRC0" addr="0x10"></reg>
+    <reg name="CDST0" addr="0x14"></reg>
+    <reg name="CCNT0" addr="0x18"></reg>
+    <reg name="CON1" addr="0x1C"></reg>
+    <reg name="ISRC1" addr="0x20"></reg>
+    <reg name="IDST1" addr="0x24"></reg>
+    <reg name="ICNT1" addr="0x28"></reg>
+    <reg name="CSRC1" addr="0x2C"></reg>
+    <reg name="CDST1" addr="0x30"></reg>
+    <reg name="CCNT1" addr="0x34"></reg>
+    <reg name="INT_STS" addr="0x38"></reg>
+    <reg name="DMA_STS" addr="0x3C"></reg>
+    <reg name="ERR_ADR0" addr="0x40"></reg>
+    <reg name="ERR_OP0" addr="0x44"></reg>
+    <reg name="ERR_ADR1" addr="0x48"></reg>
+    <reg name="ERR_OP1" addr="0x4C"></reg>
+    <reg name="LCNT0" addr="0x50"></reg>
+    <reg name="LCNT1" addr="0x54"></reg>
+    <reg name="DOMAIN" addr="0x58"></reg>
   </dev>
   <dev name="UDC" long_name="USB 2.0 Device Controller" desc="USB 2.0 Device Controller" version="1.0">
     <addr name="UDC" addr="0x180a0000" />
@@ -1138,32 +1058,62 @@ KIND, either express or implied.
     <reg name="BCHST" addr="0xD0"></reg>
     <reg name="FLASH_DATAn">
       <formula string="0x200*n+0x200" />
-      <addr name="FLASH_DATA0" addr="0x200" />
-      <addr name="FLASH_DATA1" addr="0x400" />
-      <addr name="FLASH_DATA2" addr="0x600" />
-      <addr name="FLASH_DATA3" addr="0x800" />
+      <addr name="DATA0" addr="0x200" />
+      <addr name="DATA1" addr="0x400" />
+      <addr name="DATA2" addr="0x600" />
+      <addr name="DATA3" addr="0x800" />
     </reg>
-    <reg name="FLASH_ADDRn">
+    <reg name="ADDRn">
       <formula string="0x200*n+0x204" />
-      <addr name="FLASH_ADDR0" addr="0x204" />
-      <addr name="FLASH_ADDR1" addr="0x404" />
-      <addr name="FLASH_ADDR2" addr="0x604" />
-      <addr name="FLASH_ADDR3" addr="0x804" />
+      <addr name="ADDR0" addr="0x204" />
+      <addr name="ADDR1" addr="0x404" />
+      <addr name="ADDR2" addr="0x604" />
+      <addr name="ADDR3" addr="0x804" />
     </reg>
     <reg name="FLASH_CMDn">
       <formula string="0x200*n+0x208" />
-      <addr name="FLASH_CMD0" addr="0x208" />
-      <addr name="FLASH_CMD1" addr="0x408" />
-      <addr name="FLASH_CMD2" addr="0x608" />
-      <addr name="FLASH_CMD3" addr="0x808" />
+      <addr name="CMD0" addr="0x208" />
+      <addr name="CMD1" addr="0x408" />
+      <addr name="CMD2" addr="0x608" />
+      <addr name="CMD3" addr="0x808" />
     </reg>
     <reg name="PAGE_BUF" addr="0xA00"></reg>
     <reg name="SPARE_BUF" addr="0x1200"></reg>
   </dev>
   <dev name="LCDC" long_name="LCD Interface Controller" desc="LCD Interface Controller" version="1.0">
     <addr name="LCDC" addr="0x186e8000" />
-    <reg name="LCDC_CTRL" addr="0x00"></reg>
-    <reg name="MCU_CTRL" addr="0x04"></reg>
+    <reg name="LCDC_CTRL" addr="0x00">
+      <field name="STOP" bitrange="0:0"></field>
+      <field name="ENABLE" bitrange="1:1">
+        <value name="ENABLE" value="1"/>
+        <value name="DISABLE" value="0"/>
+      </field>
+      <field name="RGB_DUMMY" bitrange="3:2">
+        <value name="PARALLEL" value="0"/>
+        <value name="RESERVED" value="1"/>
+        <value name="SERIAL_UPS501" value="2"/>
+        <value name="SERIAL_UPS502" value="3"/>
+      </field>
+      <field name="EVEN_EN" bitrange="4:4"></field>
+      <field name="START_EVEN" bitrange="5:5"></field>
+      <field name="RGB24B" bitrange="6:6"></field>
+      <field name="MCU" bitrange="7:7"></field>
+      <field name="YMIX" bitrange="8:8"></field>
+      <field name="ALPHA" bitrange="11:9"></field>
+      <field name="UVBUFEXCH" bitrange="12:12"></field>
+      <field name="ALPHA_24B" bitrange="13:13"></field>
+      <field name="RESERVED" bitrange="15:14"></field>
+    </reg>
+    <reg name="MCU_CTRL" addr="0x04">
+      <field name="BYPASS" bitrange="0:0"></field>
+      <field name="BUFF_START" bitrange="1:1"></field>
+      <field name="RESERVED0" bitrange="4:2"></field>
+      <field name="LCD_RS" bitrange="5:5"></field>
+      <field name="ALPHA_BUF_EN" bitrange="6:6"></field>
+      <field name="RESERVED1" bitrange="7:7"></field>
+      <field name="ALPHA_BASE" bitrange="14:8"></field>
+      <field name="RESERVED2" bitrange="15:15"></field>
+    </reg>
     <reg name="HOR_PERIOD" addr="0x08"></reg>
     <reg name="VERT_PERIOD" addr="0x0C"></reg>
     <reg name="HOR_PW" addr="0x10"></reg>
@@ -1199,132 +1149,134 @@ KIND, either express or implied.
     <reg name="LCD_BUFF" addr="0x2000"></reg>
   </dev>
   <dev name="HSADC" long_name="High Speed ADC" desc="High Speed ADC" version="1.0">
-    <reg name="HSADC_DATA" addr="0x00"></reg>
-    <reg name="HSADC_CTRL" addr="0x04"></reg>
-    <reg name="HSADC_IER" addr="0x08"></reg>
-    <reg name="HSADC_ISR" addr="0x0C"></reg>
+    <addr name="HSADC" addr="0x186ec000" />
+      <reg name="DATA" addr="0x00"></reg>
+      <reg name="CTRL" addr="0x04"></reg>
+      <reg name="IER" addr="0x08"></reg>
+      <reg name="ISR" addr="0x0C"></reg>
   </dev>
   <dev name="DWDMA" long_name="DMA Controller" desc="DMA Controller" version="1.0">
+    <addr name="DWDMA" addr="0x186f0000" />
     <reg name="DWDMA_SARn">
       <formula string="n*0x58+0x00" />
-      <addr name="DWDMA_SAR0" addr="0x00" />
-      <addr name="DWDMA_SAR1" addr="0x58" />
-      <addr name="DWDMA_SAR2" addr="0xb0" />
-      <addr name="DWDMA_SAR3" addr="0x108" />
+      <addr name="SAR0" addr="0x00" />
+      <addr name="SAR1" addr="0x58" />
+      <addr name="SAR2" addr="0xb0" />
+      <addr name="SAR3" addr="0x108" />
     </reg>
     <reg name="DWDMA_DARn">
       <formula string="n*0x58+0x08" />
-      <addr name="DWDMA_DAR0" addr="0x08" />
-      <addr name="DWDMA_DAR1" addr="0x60" />
-      <addr name="DWDMA_DAR2" addr="0xb8" />
-      <addr name="DWDMA_DAR3" addr="0x110" />
+      <addr name="DAR0" addr="0x08" />
+      <addr name="DAR1" addr="0x60" />
+      <addr name="DAR2" addr="0xb8" />
+      <addr name="DAR3" addr="0x110" />
     </reg>
     <reg name="DWDMA_LLPn">
       <formula string="n*0x58+0x10" />
-      <addr name="DWDMA_LLP0" addr="0x10" />
-      <addr name="DWDMA_LLP1" addr="0x68" />
-      <addr name="DWDMA_LLP2" addr="0xc0" />
-      <addr name="DWDMA_LLP3" addr="0x118" />
+      <addr name="LLP0" addr="0x10" />
+      <addr name="LLP1" addr="0x68" />
+      <addr name="LLP2" addr="0xc0" />
+      <addr name="LLP3" addr="0x118" />
     </reg>
     <reg name="DWDMA_CTL_Ln">
       <formula string="n*0x58+0x18" />
-      <addr name="DWDMA_CTL_L0" addr="0x18" />
-      <addr name="DWDMA_CTL_L1" addr="0x70" />
-      <addr name="DWDMA_CTL_L2" addr="0xc8" />
-      <addr name="DWDMA_CTL_L3" addr="0x120" />
+      <addr name="CTL_L0" addr="0x18" />
+      <addr name="CTL_L1" addr="0x70" />
+      <addr name="CTL_L2" addr="0xc8" />
+      <addr name="CTL_L3" addr="0x120" />
     </reg>
     <reg name="DWDMA_CTL_Hn">
       <formula string="n*0x58+0x1c" />
-      <addr name="DWDMA_CTL_H0" addr="0x1c" />
-      <addr name="DWDMA_CTL_H1" addr="0x74" />
-      <addr name="DWDMA_CTL_H2" addr="0xcc" />
-      <addr name="DWDMA_CTL_H3" addr="0x124" />
+      <addr name="CTL_H0" addr="0x1c" />
+      <addr name="CTL_H1" addr="0x74" />
+      <addr name="CTL_H2" addr="0xcc" />
+      <addr name="CTL_H3" addr="0x124" />
     </reg>
     <reg name="DWDMA_SSTATn">
       <formula string="n*0x58+0x20" />
-      <addr name="DWDMA_SSTAT0" addr="0x20" />
-      <addr name="DWDMA_SSTAT1" addr="0x78" />
-      <addr name="DWDMA_SSTAT2" addr="0xd0" />
-      <addr name="DWDMA_SSTAT3" addr="0x128" />
+      <addr name="SSTAT0" addr="0x20" />
+      <addr name="SSTAT1" addr="0x78" />
+      <addr name="SSTAT2" addr="0xd0" />
+      <addr name="SSTAT3" addr="0x128" />
     </reg>
     <reg name="DWDMA_DSTATn">
       <formula string="n*0x58+0x28" />
-      <addr name="DWDMA_DSTAT0" addr="0x28" />
-      <addr name="DWDMA_DSTAT1" addr="0x80" />
-      <addr name="DWDMA_DSTAT2" addr="0xd8" />
-      <addr name="DWDMA_DSTAT3" addr="0x130" />
+      <addr name="DSTAT0" addr="0x28" />
+      <addr name="DSTAT1" addr="0x80" />
+      <addr name="DSTAT2" addr="0xd8" />
+      <addr name="DSTAT3" addr="0x130" />
     </reg>
     <reg name="DWDMA_SSTATARn">
       <formula string="n*0x58+0x30" />
-      <addr name="DWDMA_SSTATAR0" addr="0x30" />
-      <addr name="DWDMA_SSTATAR1" addr="0x88" />
-      <addr name="DWDMA_SSTATAR2" addr="0xe0" />
-      <addr name="DWDMA_SSTATAR3" addr="0x138" />
+      <addr name="SSTATAR0" addr="0x30" />
+      <addr name="SSTATAR1" addr="0x88" />
+      <addr name="SSTATAR2" addr="0xe0" />
+      <addr name="SSTATAR3" addr="0x138" />
     </reg>
     <reg name="DWDMA_DSTATARn">
       <formula string="n*0x58+0x38" />
-      <addr name="DWDMA_DSTATAR0" addr="0x38" />
-      <addr name="DWDMA_DSTATAR1" addr="0x90" />
-      <addr name="DWDMA_DSTATAR2" addr="0xe8" />
-      <addr name="DWDMA_DSTATAR3" addr="0x140" />
+      <addr name="DSTATAR0" addr="0x38" />
+      <addr name="DSTATAR1" addr="0x90" />
+      <addr name="DSTATAR2" addr="0xe8" />
+      <addr name="DSTATAR3" addr="0x140" />
     </reg>
     <reg name="DWDMA_CFG_Ln">
       <formula string="n*0x58+0x40" />
-      <addr name="DWDMA_CFG_L0" addr="0x40" />
-      <addr name="DWDMA_CFG_L1" addr="0x98" />
-      <addr name="DWDMA_CFG_L2" addr="0xf0" />
-      <addr name="DWDMA_CFG_L3" addr="0x148" />
+      <addr name="CFG_L0" addr="0x40" />
+      <addr name="CFG_L1" addr="0x98" />
+      <addr name="CFG_L2" addr="0xf0" />
+      <addr name="CFG_L3" addr="0x148" />
     </reg>
     <reg name="DWDMA_CFG_Hn">
       <formula string="n*0x58+0x44" />
-      <addr name="DWDMA_CFG_H0" addr="0x44" />
-      <addr name="DWDMA_CFG_H1" addr="0x9c" />
-      <addr name="DWDMA_CFG_H2" addr="0xf4" />
-      <addr name="DWDMA_CFG_H3" addr="0x14c" />
+      <addr name="CFG_H0" addr="0x44" />
+      <addr name="CFG_H1" addr="0x9c" />
+      <addr name="CFG_H2" addr="0xf4" />
+      <addr name="CFG_H3" addr="0x14c" />
     </reg>
     <reg name="DWDMA_SGRn">
       <formula string="n*0x58+0x48" />
-      <addr name="DWDMA_SGR0" addr="0x48" />
-      <addr name="DWDMA_SGR1" addr="0xa0" />
-      <addr name="DWDMA_SGR2" addr="0xf8" />
-      <addr name="DWDMA_SGR3" addr="0x150" />
+      <addr name="SGR0" addr="0x48" />
+      <addr name="SGR1" addr="0xa0" />
+      <addr name="SGR2" addr="0xf8" />
+      <addr name="SGR3" addr="0x150" />
     </reg>
     <reg name="DWDMA_DSRn">
       <formula string="n*0x58+0x50" />
-      <addr name="DWDMA_DSR0" addr="0x50" />
-      <addr name="DWDMA_DSR1" addr="0xa8" />
-      <addr name="DWDMA_DSR2" addr="0x100" />
-      <addr name="DWDMA_DSR3" addr="0x158" />
+      <addr name="DSR0" addr="0x50" />
+      <addr name="DSR1" addr="0xa8" />
+      <addr name="DSR2" addr="0x100" />
+      <addr name="DSR3" addr="0x158" />
     </reg>
-    <reg name="DWDMA_RAW_TFR" addr="0x2C0"></reg>
-    <reg name="DWDMA_RAW_BLOCK" addr="0x2C8"></reg>
-    <reg name="DWDMA_RAW_SRCTRAN" addr="0x2D0"></reg>
-    <reg name="DWDMA_RAW_DSTTRAN" addr="0x2D8"></reg>
-    <reg name="DWDMA_RAW_ERR" addr="0x2E0"></reg>
-    <reg name="DWDMA_STATUS_TFR" addr="0x2E8"></reg>
-    <reg name="DWDMA_STATUS_BLOCK" addr="0x2F0"></reg>
-    <reg name="DWDMA_STATUS_SRCTRAN" addr="0x2F8"></reg>
-    <reg name="DWDMA_STATUS_DSTTRAN" addr="0x300"></reg>
-    <reg name="DWDMA_STATUS_ERR" addr="0x308"></reg>
-    <reg name="DWDMA_MASK_TFR" addr="0x310"></reg>
-    <reg name="DWDMA_MASK_BLOCK" addr="0x318"></reg>
-    <reg name="DWDMA_MASK_SRCTRAN" addr="0x320"></reg>
-    <reg name="DWDMA_MASK_DSTTRAN" addr="0x328"></reg>
-    <reg name="DWDMA_MASK_ERR" addr="0x330"></reg>
-    <reg name="DWDMA_CLEAR_TFR" addr="0x338"></reg>
-    <reg name="DWDMA_CLEAR_BLOCK" addr="0x340"></reg>
-    <reg name="DWDMA_CLEAR_SRCTRAN" addr="0x348"></reg>
-    <reg name="DWDMA_CLEAR_DSTTRAN" addr="0x350"></reg>
-    <reg name="DWDMA_CLEAR_ERR" addr="0x358"></reg>
-    <reg name="DWDMA_STATUS_INT" addr="0x360"></reg>
-    <reg name="DWDMA_REQ_SRC" addr="0x368"></reg>
-    <reg name="DWDMA_REQ_DST" addr="0x370"></reg>
-    <reg name="DWDMA_S_REQ_SRC" addr="0x378"></reg>
-    <reg name="DWDMA_S_REQ_DST" addr="0x380"></reg>
-    <reg name="DWDMA_L_REQ_SRC" addr="0x388"></reg>
-    <reg name="DWDMA_L_REQ_DST" addr="0x390"></reg>
-    <reg name="DWDMA_DMA_CFG" addr="0x398"></reg>
-    <reg name="DWDMA_DMA_CHEN" addr="0x3A0"></reg>
+    <reg name="RAW_TFR" addr="0x2C0"></reg>
+    <reg name="RAW_BLOCK" addr="0x2C8"></reg>
+    <reg name="RAW_SRCTRAN" addr="0x2D0"></reg>
+    <reg name="RAW_DSTTRAN" addr="0x2D8"></reg>
+    <reg name="RAW_ERR" addr="0x2E0"></reg>
+    <reg name="STATUS_TFR" addr="0x2E8"></reg>
+    <reg name="STATUS_BLOCK" addr="0x2F0"></reg>
+    <reg name="STATUS_SRCTRAN" addr="0x2F8"></reg>
+    <reg name="STATUS_DSTTRAN" addr="0x300"></reg>
+    <reg name="STATUS_ERR" addr="0x308"></reg>
+    <reg name="MASK_TFR" addr="0x310"></reg>
+    <reg name="MASK_BLOCK" addr="0x318"></reg>
+    <reg name="MASK_SRCTRAN" addr="0x320"></reg>
+    <reg name="MASK_DSTTRAN" addr="0x328"></reg>
+    <reg name="MASK_ERR" addr="0x330"></reg>
+    <reg name="CLEAR_TFR" addr="0x338"></reg>
+    <reg name="CLEAR_BLOCK" addr="0x340"></reg>
+    <reg name="CLEAR_SRCTRAN" addr="0x348"></reg>
+    <reg name="CLEAR_DSTTRAN" addr="0x350"></reg>
+    <reg name="CLEAR_ERR" addr="0x358"></reg>
+    <reg name="STATUS_INT" addr="0x360"></reg>
+    <reg name="REQ_SRC" addr="0x368"></reg>
+    <reg name="REQ_DST" addr="0x370"></reg>
+    <reg name="S_REQ_SRC" addr="0x378"></reg>
+    <reg name="S_REQ_DST" addr="0x380"></reg>
+    <reg name="L_REQ_SRC" addr="0x388"></reg>
+    <reg name="L_REQ_DST" addr="0x390"></reg>
+    <reg name="DMA_CFG" addr="0x398"></reg>
+    <reg name="DMA_CHEN" addr="0x3A0"></reg>
   </dev>
   <dev name="CACHE" long_name="CACHE Controller" desc="CACHE Controller" version="1.0">
     <addr name="CACHE" addr="0xEFFF0000" />
-- 
cgit v1.2.3