From 357ffb3c46a6c371fd84b56acd6f69cb6aad9bb8 Mon Sep 17 00:00:00 2001 From: Nicolas Pennequin Date: Mon, 5 May 2008 10:32:46 +0000 Subject: Convert the whole codebase to UTF-8, except docs/COMMITTERS and tools/creative.c, which need checking. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17369 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/coldfire/iaudio/m3/adc-m3.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'firmware/target/coldfire/iaudio/m3/adc-m3.c') diff --git a/firmware/target/coldfire/iaudio/m3/adc-m3.c b/firmware/target/coldfire/iaudio/m3/adc-m3.c index 5997f2419a..9f5bf04a64 100644 --- a/firmware/target/coldfire/iaudio/m3/adc-m3.c +++ b/firmware/target/coldfire/iaudio/m3/adc-m3.c @@ -25,8 +25,8 @@ #define ADC_I2C_ADDR 0xa0 -/* The M3 ADC is hooked exclusively to the secondary I²C bus, and requires - * very slow transfers (I²C clock <= 16kHz). So we start one 4-byte read +/* The M3 ADC is hooked exclusively to the secondary I²C bus, and requires + * very slow transfers (I²C clock <= 16kHz). So we start one 4-byte read * transfer each tick, and handle it via an ISR. At 11MHz, one transfer * takes too long to be started every tick, but it seems we have to live * with that. */ @@ -92,7 +92,7 @@ unsigned short adc_read(int channel) void adc_init(void) { - MFDR2 = 0x1f; /* I²C clock = SYSCLK / 3840 */ + MFDR2 = 0x1f; /* I²C clock = SYSCLK / 3840 */ MBCR2 = IEN; /* Enable interface */ MBSR2 = 0; /* Clear flags */ MBCR2 = (IEN|IIEN); /* Enable interrupts */ @@ -105,7 +105,7 @@ void adc_init(void) sleep(1); /* Ensure valid readings when adc_init returns */ } -/* The ADC (most probably the PIC12F675) obviously has a slow and buggy I²C +/* The ADC (most probably the PIC12F675) obviously has a slow and buggy I²C * implementation. If a transfer is stopped prematurely, it often locks up * and doesn't react anymore until the unit is power cycled. */ -- cgit v1.2.3