From 3ae6fbc600d30cd385b17135464774d4739405e1 Mon Sep 17 00:00:00 2001 From: Aidan MacDonald Date: Wed, 22 Sep 2021 11:24:03 +0100 Subject: x1000: default to sending 0 samples on underflow Previously it used the last sample, which turns out to be broken. The AIC appears to send out a random non-zero sample continously after boot -- probably because the last sample is uninitialized by the hardware. Disabling playback is supposed to make it send zero samples irregardless of the LSMP bit according to the docs, but it doesn't seem to work this way. - Change eliminates the white noise heard on the M3K after boot. - Change has no adverse effects on the Q1. - Leave Eros Q on the old setting since sending zeros exacerbates clicking due to DAC's automute feature. Change-Id: I9996793fc34f4475b19700d076b11505353b3836 --- firmware/target/mips/ingenic_x1000/erosqnative/audiohw-erosqnative.c | 1 + firmware/target/mips/ingenic_x1000/pcm-x1000.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/firmware/target/mips/ingenic_x1000/erosqnative/audiohw-erosqnative.c b/firmware/target/mips/ingenic_x1000/erosqnative/audiohw-erosqnative.c index 7bb985650c..52265c9580 100644 --- a/firmware/target/mips/ingenic_x1000/erosqnative/audiohw-erosqnative.c +++ b/firmware/target/mips/ingenic_x1000/erosqnative/audiohw-erosqnative.c @@ -42,6 +42,7 @@ void audiohw_init(void) gpio_set_level(GPIO_ISL54405_MUTE, 1); gpio_set_level(GPIO_PCM5102A_XMIT, 0); + aic_set_play_last_sample(true); aic_set_external_codec(true); aic_set_i2s_mode(AIC_I2S_MASTER_MODE); audiohw_set_frequency(HW_FREQ_48); diff --git a/firmware/target/mips/ingenic_x1000/pcm-x1000.c b/firmware/target/mips/ingenic_x1000/pcm-x1000.c index ce2fbb17a9..ef54d45e62 100644 --- a/firmware/target/mips/ingenic_x1000/pcm-x1000.c +++ b/firmware/target/mips/ingenic_x1000/pcm-x1000.c @@ -58,7 +58,7 @@ void pcm_play_dma_init(void) /* Configure AIC with some sane defaults */ jz_writef(AIC_CFG, RST(1)); jz_writef(AIC_I2SCR, STPBK(1)); - jz_writef(AIC_CFG, MSB(0), LSMP(1), ICDC(0), AUSEL(1), BCKD(0), SYNCD(0)); + jz_writef(AIC_CFG, MSB(0), LSMP(0), ICDC(0), AUSEL(1), BCKD(0), SYNCD(0)); jz_writef(AIC_CCR, ENDSW(0), ASVTSU(0)); jz_writef(AIC_I2SCR, RFIRST(0), ESCLK(0), AMSL(0)); jz_write(AIC_SPENA, 0); -- cgit v1.2.3