// SPDX-License-Identifier: BSD-3-Clause /* * SC7180 SoC device tree source * * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include / { interrupt-parent = <&intc>; #address-cells = <2>; #size-cells = <2>; chosen { }; aliases { mmc1 = &sdhc_1; mmc2 = &sdhc_2; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; i2c7 = &i2c7; i2c8 = &i2c8; i2c9 = &i2c9; i2c10 = &i2c10; i2c11 = &i2c11; spi0 = &spi0; spi1 = &spi1; spi3 = &spi3; spi5 = &spi5; spi6 = &spi6; spi8 = &spi8; spi10 = &spi10; spi11 = &spi11; }; clocks { xo_board: xo-board { compatible = "fixed-clock"; clock-frequency = <38400000>; #clock-cells = <0>; }; sleep_clk: sleep-clk { compatible = "fixed-clock"; clock-frequency = <32764>; #clock-cells = <0>; }; }; reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; hyp_mem: memory@80000000 { reg = <0x0 0x80000000 0x0 0x600000>; no-map; }; xbl_mem: memory@80600000 { reg = <0x0 0x80600000 0x0 0x200000>; no-map; }; aop_mem: memory@80800000 { reg = <0x0 0x80800000 0x0 0x20000>; no-map; }; aop_cmd_db_mem: memory@80820000 { reg = <0x0 0x80820000 0x0 0x20000>; compatible = "qcom,cmd-db"; no-map; }; sec_apps_mem: memory@808ff000 { reg = <0x0 0x808ff000 0x0 0x1000>; no-map; }; smem_mem: memory@80900000 { reg = <0x0 0x80900000 0x0 0x200000>; no-map; }; tz_mem: memory@80b00000 { reg = <0x0 0x80b00000 0x0 0x3900000>; no-map; }; rmtfs_mem: memory@84400000 { compatible = "qcom,rmtfs-mem"; reg = <0x0 0x84400000 0x0 0x200000>; no-map; qcom,client-id = <1>; qcom,vmid = <15>; }; }; cpus { #address-cells = <2>; #size-cells = <0>; CPU0: cpu@0 { device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; next-level-cache = <&L2_0>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; }; }; }; CPU1: cpu@100 { device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x100>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_100>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; }; }; CPU2: cpu@200 { device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x200>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_200>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; }; }; CPU3: cpu@300 { device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x300>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_300>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; }; }; CPU4: cpu@400 { device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x400>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_400>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; }; }; CPU5: cpu@500 { device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x500>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_500>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; }; }; CPU6: cpu@600 { device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x600>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1740>; dynamic-power-coefficient = <405>; next-level-cache = <&L2_600>; operating-points-v2 = <&cpu6_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; }; }; CPU7: cpu@700 { device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x700>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1740>; dynamic-power-coefficient = <405>; next-level-cache = <&L2_700>; operating-points-v2 = <&cpu6_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 1>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; }; }; cpu-map { cluster0 { core0 { cpu = <&CPU0>; }; core1 { cpu = <&CPU1>; }; core2 { cpu = <&CPU2>; }; core3 { cpu = <&CPU3>; }; core4 { cpu = <&CPU4>; }; core5 { cpu = <&CPU5>; }; core6 { cpu = <&CPU6>; }; core7 { cpu = <&CPU7>; }; }; }; idle-states { entry-method = "psci"; LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { compatible = "arm,idle-state"; idle-state-name = "little-power-down"; arm,psci-suspend-param = <0x40000003>; entry-latency-us = <549>; exit-latency-us = <901>; min-residency-us = <1774>; local-timer-stop; }; LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { compatible = "arm,idle-state"; idle-state-name = "little-rail-power-down"; arm,psci-suspend-param = <0x40000004>; entry-latency-us = <702>; exit-latency-us = <915>; min-residency-us = <4001>; local-timer-stop; }; BIG_CPU_SLEEP_0: cpu-sleep-1-0 { compatible = "arm,idle-state"; idle-state-name = "big-power-down"; arm,psci-suspend-param = <0x40000003>; entry-latency-us = <523>; exit-latency-us = <1244>; min-residency-us = <2207>; local-timer-stop; }; BIG_CPU_SLEEP_1: cpu-sleep-1-1 { compatible = "arm,idle-state"; idle-state-name = "big-rail-power-down"; arm,psci-suspend-param = <0x40000004>; entry-latency-us = <526>; exit-latency-us = <1854>; min-residency-us = <5555>; local-timer-stop; }; CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "arm,idle-state"; idle-state-name = "cluster-power-down"; arm,psci-suspend-param = <0x40003444>; entry-latency-us = <3263>; exit-latency-us = <6562>; min-residency-us = <9926>; local-timer-stop; }; }; }; cpu0_opp_table: cpu0_opp_table { compatible = "operating-points-v2"; opp-shared; cpu0_opp1: opp-300000000 { opp-hz = /bits/ 64 <300000000>; opp-peak-kBps = <1200000 4800000>; }; cpu0_opp2: opp-576000000 { opp-hz = /bits/ 64 <576000000>; opp-peak-kBps = <1200000 4800000>; }; cpu0_opp3: opp-768000000 { opp-hz = /bits/ 64 <768000000>; opp-peak-kBps = <1200000 4800000>; }; cpu0_opp4: opp-1017600000 { opp-hz = /bits/ 64 <1017600000>; opp-peak-kBps = <1804000 8908800>; }; cpu0_opp5: opp-1248000000 { opp-hz = /bits/ 64 <1248000000>; opp-peak-kBps = <2188000 12902400>; }; cpu0_opp6: opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; opp-peak-kBps = <2188000 12902400>; }; cpu0_opp7: opp-1516800000 { opp-hz = /bits/ 64 <1516800000>; opp-peak-kBps = <3072000 15052800>; }; cpu0_opp8: opp-1612800000 { opp-hz = /bits/ 64 <1612800000>; opp-peak-kBps = <3072000 15052800>; }; cpu0_opp9: opp-1708800000 { opp-hz = /bits/ 64 <1708800000>; opp-peak-kBps = <3072000 15052800>; }; cpu0_opp10: opp-1804800000 { opp-hz = /bits/ 64 <1804800000>; opp-peak-kBps = <4068000 22425600>; }; }; cpu6_opp_table: cpu6_opp_table { compatible = "operating-points-v2"; opp-shared; cpu6_opp1: opp-300000000 { opp-hz = /bits/ 64 <300000000>; opp-peak-kBps = <2188000 8908800>; }; cpu6_opp2: opp-652800000 { opp-hz = /bits/ 64 <652800000>; opp-peak-kBps = <2188000 8908800>; }; cpu6_opp3: opp-825600000 { opp-hz = /bits/ 64 <825600000>; opp-peak-kBps = <2188000 8908800>; }; cpu6_opp4: opp-979200000 { opp-hz = /bits/ 64 <979200000>; opp-peak-kBps = <2188000 8908800>; }; cpu6_opp5: opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; opp-peak-kBps = <2188000 8908800>; }; cpu6_opp6: opp-1267200000 { opp-hz = /bits/ 64 <1267200000>; opp-peak-kBps = <4068000 12902400>; }; cpu6_opp7: opp-1555200000 { opp-hz = /bits/ 64 <1555200000>; opp-peak-kBps = <4068000 15052800>; }; cpu6_opp8: opp-1708800000 { opp-hz = /bits/ 64 <1708800000>; opp-peak-kBps = <6220000 19353600>; }; cpu6_opp9: opp-1843200000 { opp-hz = /bits/ 64 <1843200000>; opp-peak-kBps = <6220000 19353600>; }; cpu6_opp10: opp-1900800000 { opp-hz = /bits/ 64 <1900800000>; opp-peak-kBps = <6220000 22425600>; }; cpu6_opp11: opp-1996800000 { opp-hz = /bits/ 64 <1996800000>; opp-peak-kBps = <6220000 22425600>; }; cpu6_opp12: opp-2112000000 { opp-hz = /bits/ 64 <2112000000>; opp-peak-kBps = <6220000 22425600>; }; cpu6_opp13: opp-2208000000 { opp-hz = /bits/ 64 <2208000000>; opp-peak-kBps = <7216000 22425600>; }; cpu6_opp14: opp-2323200000 { opp-hz = /bits/ 64 <2323200000>; opp-peak-kBps = <7216000 22425600>; }; cpu6_opp15: opp-2400000000 { opp-hz = /bits/ 64 <2400000000>; opp-peak-kBps = <8532000 23347200>; }; cpu6_opp16: opp-2553600000 { opp-hz = /bits/ 64 <2553600000>; opp-peak-kBps = <8532000 23347200>; }; }; memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ reg = <0 0x80000000 0 0>; }; pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; }; firmware { scm { compatible = "qcom,scm-sc7180", "qcom,scm"; }; }; tcsr_mutex: hwlock { compatible = "qcom,tcsr-mutex"; syscon = <&tcsr_mutex_regs 0 0x1000>; #hwlock-cells = <1>; }; smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; hwlocks = <&tcsr_mutex 3>; }; smp2p-cdsp { compatible = "qcom,smp2p"; qcom,smem = <94>, <432>; interrupts = ; mboxes = <&apss_shared 6>; qcom,local-pid = <0>; qcom,remote-pid = <5>; cdsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; cdsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; smp2p-lpass { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; interrupts = ; mboxes = <&apss_shared 10>; qcom,local-pid = <0>; qcom,remote-pid = <2>; adsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; adsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; smp2p-mpss { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; interrupts = ; mboxes = <&apss_shared 14>; qcom,local-pid = <0>; qcom,remote-pid = <1>; modem_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; modem_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; ipa_smp2p_out: ipa-ap-to-modem { qcom,entry-name = "ipa"; #qcom,smem-state-cells = <1>; }; ipa_smp2p_in: ipa-modem-to-ap { qcom,entry-name = "ipa"; interrupt-controller; #interrupt-cells = <2>; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; soc: soc@0 { #address-cells = <2>; #size-cells = <2>; ranges = <0 0 0 0 0x10 0>; dma-ranges = <0 0 0 0 0x10 0>; compatible = "simple-bus"; gcc: clock-controller@100000 { compatible = "qcom,gcc-sc7180"; reg = <0 0x00100000 0 0x1f0000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; qfprom: efuse@784000 { compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; reg = <0 0x00784000 0 0x8ff>, <0 0x00780000 0 0x7a0>, <0 0x00782000 0 0x100>, <0 0x00786000 0 0x1fff>; clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; clock-names = "core"; #address-cells = <1>; #size-cells = <1>; qusb2p_hstx_trim: hstx-trim-primary@25b { reg = <0x25b 0x1>; bits = <1 3>; }; }; sdhc_1: sdhci@7c4000 { compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x7c4000 0 0x1000>, <0 0x07c5000 0 0x1000>; reg-names = "hc", "cqhci"; iommus = <&apps_smmu 0x60 0x0>; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; clock-names = "core", "iface"; interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&sdhc1_opp_table>; bus-width = <8>; non-removable; supports-cqe; mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; status = "disabled"; sdhc1_opp_table: sdhc1-opp-table { compatible = "operating-points-v2"; opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <100000 100000>; opp-avg-kBps = <100000 50000>; }; opp-384000000 { opp-hz = /bits/ 64 <384000000>; required-opps = <&rpmhpd_opp_svs_l1>; opp-peak-kBps = <600000 900000>; opp-avg-kBps = <261438 300000>; }; }; }; qup_opp_table: qup-opp-table { compatible = "operating-points-v2"; opp-75000000 { opp-hz = /bits/ 64 <75000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-128000000 { opp-hz = /bits/ 64 <128000000>; required-opps = <&rpmhpd_opp_nom>; }; }; qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x008c0000 0 0x6000>; clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; #address-cells = <2>; #size-cells = <2>; ranges; iommus = <&apps_smmu 0x43 0x0>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>; interconnect-names = "qup-core"; status = "disabled"; i2c0: i2c@880000 { compatible = "qcom,geni-i2c"; reg = <0 0x00880000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c0_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi0: spi@880000 { compatible = "qcom,geni-spi"; reg = <0 0x00880000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi0_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; uart0: serial@880000 { compatible = "qcom,geni-uart"; reg = <0 0x00880000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart0_default>; interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c1: i2c@884000 { compatible = "qcom,geni-i2c"; reg = <0 0x00884000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c1_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi1: spi@884000 { compatible = "qcom,geni-spi"; reg = <0 0x00884000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi1_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; uart1: serial@884000 { compatible = "qcom,geni-uart"; reg = <0 0x00884000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart1_default>; interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c2: i2c@888000 { compatible = "qcom,geni-i2c"; reg = <0 0x00888000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c2_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; uart2: serial@888000 { compatible = "qcom,geni-uart"; reg = <0 0x00888000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart2_default>; interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c3: i2c@88c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0088c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c3_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi3: spi@88c000 { compatible = "qcom,geni-spi"; reg = <0 0x0088c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi3_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; uart3: serial@88c000 { compatible = "qcom,geni-uart"; reg = <0 0x0088c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart3_default>; interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c4: i2c@890000 { compatible = "qcom,geni-i2c"; reg = <0 0x00890000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c4_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; uart4: serial@890000 { compatible = "qcom,geni-uart"; reg = <0 0x00890000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart4_default>; interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c5: i2c@894000 { compatible = "qcom,geni-i2c"; reg = <0 0x00894000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c5_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi5: spi@894000 { compatible = "qcom,geni-spi"; reg = <0 0x00894000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi5_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; uart5: serial@894000 { compatible = "qcom,geni-uart"; reg = <0 0x00894000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart5_default>; interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; }; qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x00ac0000 0 0x6000>; clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; #address-cells = <2>; #size-cells = <2>; ranges; iommus = <&apps_smmu 0x4c3 0x0>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>; interconnect-names = "qup-core"; status = "disabled"; i2c6: i2c@a80000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c6_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi6: spi@a80000 { compatible = "qcom,geni-spi"; reg = <0 0x00a80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi6_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; uart6: serial@a80000 { compatible = "qcom,geni-uart"; reg = <0 0x00a80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart6_default>; interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c7: i2c@a84000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c7_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; uart7: serial@a84000 { compatible = "qcom,geni-uart"; reg = <0 0x00a84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart7_default>; interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c8: i2c@a88000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c8_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi8: spi@a88000 { compatible = "qcom,geni-spi"; reg = <0 0x00a88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi8_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; uart8: serial@a88000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x00a88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart8_default>; interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c9: i2c@a8c000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a8c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c9_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; uart9: serial@a8c000 { compatible = "qcom,geni-uart"; reg = <0 0x00a8c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart9_default>; interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c10: i2c@a90000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c10_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi10: spi@a90000 { compatible = "qcom,geni-spi"; reg = <0 0x00a90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi10_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; uart10: serial@a90000 { compatible = "qcom,geni-uart"; reg = <0 0x00a90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart10_default>; interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c11: i2c@a94000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c11_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi11: spi@a94000 { compatible = "qcom,geni-spi"; reg = <0 0x00a94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi11_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; uart11: serial@a94000 { compatible = "qcom,geni-uart"; reg = <0 0x00a94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart11_default>; interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; }; config_noc: interconnect@1500000 { compatible = "qcom,sc7180-config-noc"; reg = <0 0x01500000 0 0x28000>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; system_noc: interconnect@1620000 { compatible = "qcom,sc7180-system-noc"; reg = <0 0x01620000 0 0x17080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mc_virt: interconnect@1638000 { compatible = "qcom,sc7180-mc-virt"; reg = <0 0x01638000 0 0x1000>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; qup_virt: interconnect@1650000 { compatible = "qcom,sc7180-qup-virt"; reg = <0 0x01650000 0 0x1000>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre1_noc: interconnect@16e0000 { compatible = "qcom,sc7180-aggre1-noc"; reg = <0 0x016e0000 0 0x15080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre2_noc: interconnect@1705000 { compatible = "qcom,sc7180-aggre2-noc"; reg = <0 0x01705000 0 0x9000>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; compute_noc: interconnect@170e000 { compatible = "qcom,sc7180-compute-noc"; reg = <0 0x0170e000 0 0x6000>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mmss_noc: interconnect@1740000 { compatible = "qcom,sc7180-mmss-noc"; reg = <0 0x01740000 0 0x1c100>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; ipa_virt: interconnect@1e00000 { compatible = "qcom,sc7180-ipa-virt"; reg = <0 0x01e00000 0 0x1000>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; ipa: ipa@1e40000 { compatible = "qcom,sc7180-ipa"; iommus = <&apps_smmu 0x440 0x0>, <&apps_smmu 0x442 0x0>; reg = <0 0x1e40000 0 0x7000>, <0 0x1e47000 0 0x2000>, <0 0x1e04000 0 0x2c000>; reg-names = "ipa-reg", "ipa-shared", "gsi"; interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; interrupt-names = "ipa", "gsi", "ipa-clock-query", "ipa-setup-ready"; clocks = <&rpmhcc RPMH_IPA_CLK>; clock-names = "core"; interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; interconnect-names = "memory", "imem", "config"; qcom,smem-states = <&ipa_smp2p_out 0>, <&ipa_smp2p_out 1>; qcom,smem-state-names = "ipa-clock-enabled-valid", "ipa-clock-enabled"; modem-remoteproc = <&remoteproc_mpss>; status = "disabled"; }; tcsr_mutex_regs: syscon@1f40000 { compatible = "syscon"; reg = <0 0x01f40000 0 0x40000>; }; tcsr_regs: syscon@1fc0000 { compatible = "syscon"; reg = <0 0x01fc0000 0 0x40000>; }; tlmm: pinctrl@3500000 { compatible = "qcom,sc7180-pinctrl"; reg = <0 0x03500000 0 0x300000>, <0 0x03900000 0 0x300000>, <0 0x03d00000 0 0x300000>; reg-names = "west", "north", "south"; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 120>; wakeup-parent = <&pdc>; dp_hot_plug_det: dp-hot-plug-det { pinmux { pins = "gpio117"; function = "dp_hot"; }; }; qspi_clk: qspi-clk { pinmux { pins = "gpio63"; function = "qspi_clk"; }; }; qspi_cs0: qspi-cs0 { pinmux { pins = "gpio68"; function = "qspi_cs"; }; }; qspi_cs1: qspi-cs1 { pinmux { pins = "gpio72"; function = "qspi_cs"; }; }; qspi_data01: qspi-data01 { pinmux-data { pins = "gpio64", "gpio65"; function = "qspi_data"; }; }; qspi_data12: qspi-data12 { pinmux-data { pins = "gpio66", "gpio67"; function = "qspi_data"; }; }; qup_i2c0_default: qup-i2c0-default { pinmux { pins = "gpio34", "gpio35"; function = "qup00"; }; }; qup_i2c1_default: qup-i2c1-default { pinmux { pins = "gpio0", "gpio1"; function = "qup01"; }; }; qup_i2c2_default: qup-i2c2-default { pinmux { pins = "gpio15", "gpio16"; function = "qup02_i2c"; }; }; qup_i2c3_default: qup-i2c3-default { pinmux { pins = "gpio38", "gpio39"; function = "qup03"; }; }; qup_i2c4_default: qup-i2c4-default { pinmux { pins = "gpio115", "gpio116"; function = "qup04_i2c"; }; }; qup_i2c5_default: qup-i2c5-default { pinmux { pins = "gpio25", "gpio26"; function = "qup05"; }; }; qup_i2c6_default: qup-i2c6-default { pinmux { pins = "gpio59", "gpio60"; function = "qup10"; }; }; qup_i2c7_default: qup-i2c7-default { pinmux { pins = "gpio6", "gpio7"; function = "qup11_i2c"; }; }; qup_i2c8_default: qup-i2c8-default { pinmux { pins = "gpio42", "gpio43"; function = "qup12"; }; }; qup_i2c9_default: qup-i2c9-default { pinmux { pins = "gpio46", "gpio47"; function = "qup13_i2c"; }; }; qup_i2c10_default: qup-i2c10-default { pinmux { pins = "gpio86", "gpio87"; function = "qup14"; }; }; qup_i2c11_default: qup-i2c11-default { pinmux { pins = "gpio53", "gpio54"; function = "qup15"; }; }; qup_spi0_default: qup-spi0-default { pinmux { pins = "gpio34", "gpio35", "gpio36", "gpio37"; function = "qup00"; }; }; qup_spi0_cs_gpio: qup-spi0-cs-gpio { pinmux { pins = "gpio34", "gpio35", "gpio36"; function = "qup00"; }; pinmux-cs { pins = "gpio37"; function = "gpio"; }; }; qup_spi1_default: qup-spi1-default { pinmux { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "qup01"; }; }; qup_spi1_cs_gpio: qup-spi1-cs-gpio { pinmux { pins = "gpio0", "gpio1", "gpio2"; function = "qup01"; }; pinmux-cs { pins = "gpio3"; function = "gpio"; }; }; qup_spi3_default: qup-spi3-default { pinmux { pins = "gpio38", "gpio39", "gpio40", "gpio41"; function = "qup03"; }; }; qup_spi3_cs_gpio: qup-spi3-cs-gpio { pinmux { pins = "gpio38", "gpio39", "gpio40"; function = "qup03"; }; pinmux-cs { pins = "gpio41"; function = "gpio"; }; }; qup_spi5_default: qup-spi5-default { pinmux { pins = "gpio25", "gpio26", "gpio27", "gpio28"; function = "qup05"; }; }; qup_spi5_cs_gpio: qup-spi5-cs-gpio { pinmux { pins = "gpio25", "gpio26", "gpio27"; function = "qup05"; }; pinmux-cs { pins = "gpio28"; function = "gpio"; }; }; qup_spi6_default: qup-spi6-default { pinmux { pins = "gpio59", "gpio60", "gpio61", "gpio62"; function = "qup10"; }; }; qup_spi6_cs_gpio: qup-spi6-cs-gpio { pinmux { pins = "gpio59", "gpio60", "gpio61"; function = "qup10"; }; pinmux-cs { pins = "gpio62"; function = "gpio"; }; }; qup_spi8_default: qup-spi8-default { pinmux { pins = "gpio42", "gpio43", "gpio44", "gpio45"; function = "qup12"; }; }; qup_spi8_cs_gpio: qup-spi8-cs-gpio { pinmux { pins = "gpio42", "gpio43", "gpio44"; function = "qup12"; }; pinmux-cs { pins = "gpio45"; function = "gpio"; }; }; qup_spi10_default: qup-spi10-default { pinmux { pins = "gpio86", "gpio87", "gpio88", "gpio89"; function = "qup14"; }; }; qup_spi10_cs_gpio: qup-spi10-cs-gpio { pinmux { pins = "gpio86", "gpio87", "gpio88"; function = "qup14"; }; pinmux-cs { pins = "gpio89"; function = "gpio"; }; }; qup_spi11_default: qup-spi11-default { pinmux { pins = "gpio53", "gpio54", "gpio55", "gpio56"; function = "qup15"; }; }; qup_spi11_cs_gpio: qup-spi11-cs-gpio { pinmux { pins = "gpio53", "gpio54", "gpio55"; function = "qup15"; }; pinmux-cs { pins = "gpio56"; function = "gpio"; }; }; qup_uart0_default: qup-uart0-default { pinmux { pins = "gpio34", "gpio35", "gpio36", "gpio37"; function = "qup00"; }; }; qup_uart1_default: qup-uart1-default { pinmux { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "qup01"; }; }; qup_uart2_default: qup-uart2-default { pinmux { pins = "gpio15", "gpio16"; function = "qup02_uart"; }; }; qup_uart3_default: qup-uart3-default { pinmux { pins = "gpio38", "gpio39", "gpio40", "gpio41"; function = "qup03"; }; }; qup_uart4_default: qup-uart4-default { pinmux { pins = "gpio115", "gpio116"; function = "qup04_uart"; }; }; qup_uart5_default: qup-uart5-default { pinmux { pins = "gpio25", "gpio26", "gpio27", "gpio28"; function = "qup05"; }; }; qup_uart6_default: qup-uart6-default { pinmux { pins = "gpio59", "gpio60", "gpio61", "gpio62"; function = "qup10"; }; }; qup_uart7_default: qup-uart7-default { pinmux { pins = "gpio6", "gpio7"; function = "qup11_uart"; }; }; qup_uart8_default: qup-uart8-default { pinmux { pins = "gpio44", "gpio45"; function = "qup12"; }; }; qup_uart9_default: qup-uart9-default { pinmux { pins = "gpio46", "gpio47"; function = "qup13_uart"; }; }; qup_uart10_default: qup-uart10-default { pinmux { pins = "gpio86", "gpio87", "gpio88", "gpio89"; function = "qup14"; }; }; qup_uart11_default: qup-uart11-default { pinmux { pins = "gpio53", "gpio54", "gpio55", "gpio56"; function = "qup15"; }; }; sec_mi2s_active: sec-mi2s-active { pinmux { pins = "gpio49", "gpio50", "gpio51"; function = "mi2s_1"; }; pinconf { pins = "gpio49", "gpio50", "gpio51"; drive-strength = <8>; bias-pull-up; }; }; pri_mi2s_active: pri-mi2s-active { pinmux { pins = "gpio53", "gpio54", "gpio55", "gpio56"; function = "mi2s_0"; }; pinconf { pins = "gpio53", "gpio54", "gpio55", "gpio56"; drive-strength = <8>; bias-pull-up; }; }; pri_mi2s_mclk_active: pri-mi2s-mclk-active { pinmux { pins = "gpio57"; function = "lpass_ext"; }; pinconf { pins = "gpio57"; drive-strength = <8>; bias-pull-up; }; }; sdc1_on: sdc1-on { pinconf-clk { pins = "sdc1_clk"; bias-disable; drive-strength = <16>; }; pinconf-cmd { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <10>; }; pinconf-data { pins = "sdc1_data"; bias-pull-up; drive-strength = <10>; }; pinconf-rclk { pins = "sdc1_rclk"; bias-pull-down; }; }; sdc1_off: sdc1-off { pinconf-clk { pins = "sdc1_clk"; bias-disable; drive-strength = <2>; }; pinconf-cmd { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <2>; }; pinconf-data { pins = "sdc1_data"; bias-pull-up; drive-strength = <2>; }; pinconf-rclk { pins = "sdc1_rclk"; bias-pull-down; }; }; sdc2_on: sdc2-on { pinconf-clk { pins = "sdc2_clk"; bias-disable; drive-strength = <16>; }; pinconf-cmd { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; pinconf-data { pins = "sdc2_data"; bias-pull-up; drive-strength = <10>; }; pinconf-sd-cd { pins = "gpio69"; bias-pull-up; drive-strength = <2>; }; }; sdc2_off: sdc2-off { pinconf-clk { pins = "sdc2_clk"; bias-disable; drive-strength = <2>; }; pinconf-cmd { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <2>; }; pinconf-data { pins = "sdc2_data"; bias-pull-up; drive-strength = <2>; }; pinconf-sd-cd { pins = "gpio69"; bias-disable; drive-strength = <2>; }; }; }; remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sc7180-mpss-pas"; reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; reg-names = "qdsp6", "rmb"; interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", "shutdown-ack"; clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, <&gcc GCC_MSS_NAV_AXI_CLK>, <&gcc GCC_MSS_SNOC_AXI_CLK>, <&gcc GCC_MSS_MFAB_AXIS_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "bus", "nav", "snoc_axi", "mnoc_axi", "xo"; power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, <&rpmhpd SC7180_CX>, <&rpmhpd SC7180_MX>, <&rpmhpd SC7180_MSS>; power-domain-names = "load_state", "cx", "mx", "mss"; memory-region = <&mpss_mem>; qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; resets = <&aoss_reset AOSS_CC_MSS_RESTART>, <&pdc_reset PDC_MODEM_SYNC_RESET>; reset-names = "mss_restart", "pdc_reset"; qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; qcom,spare-regs = <&tcsr_regs 0xb3e4>; status = "disabled"; glink-edge { interrupts = ; label = "modem"; qcom,remote-pid = <1>; mboxes = <&apss_shared 12>; }; }; gpu: gpu@5000000 { compatible = "qcom,adreno-618.0", "qcom,adreno"; #stream-id-cells = <16>; reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, <0 0x05061000 0 0x800>; reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; interrupts = ; iommus = <&adreno_smmu 0>; operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; #cooling-cells = <2>; interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "gfx-mem"; gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-800000000 { opp-hz = /bits/ 64 <800000000>; opp-level = ; opp-peak-kBps = <8532000>; }; opp-650000000 { opp-hz = /bits/ 64 <650000000>; opp-level = ; opp-peak-kBps = <7216000>; }; opp-565000000 { opp-hz = /bits/ 64 <565000000>; opp-level = ; opp-peak-kBps = <5412000>; }; opp-430000000 { opp-hz = /bits/ 64 <430000000>; opp-level = ; opp-peak-kBps = <5412000>; }; opp-355000000 { opp-hz = /bits/ 64 <355000000>; opp-level = ; opp-peak-kBps = <3072000>; }; opp-267000000 { opp-hz = /bits/ 64 <267000000>; opp-level = ; opp-peak-kBps = <3072000>; }; opp-180000000 { opp-hz = /bits/ 64 <180000000>; opp-level = ; opp-peak-kBps = <1804000>; }; }; }; adreno_smmu: iommu@5040000 { compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; reg = <0 0x05040000 0 0x10000>; #iommu-cells = <1>; #global-interrupts = <2>; interrupts = , , , , , , , , , ; clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gcc GCC_GPU_CFG_AHB_CLK>; clock-names = "bus", "iface"; power-domains = <&gpucc CX_GDSC>; }; gmu: gmu@506a000 { compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, <0 0x0b490000 0 0x10000>; reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; interrupts = , ; interrupt-names = "hfi", "gmu"; clocks = <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_CXO_CLK>, <&gcc GCC_DDRSS_GPU_AXI_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>; clock-names = "gmu", "cxo", "axi", "memnoc"; power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; power-domain-names = "cx", "gx"; iommus = <&adreno_smmu 5>; operating-points-v2 = <&gmu_opp_table>; gmu_opp_table: opp-table { compatible = "operating-points-v2"; opp-200000000 { opp-hz = /bits/ 64 <200000000>; opp-level = ; }; }; }; gpucc: clock-controller@5090000 { compatible = "qcom,sc7180-gpucc"; reg = <0 0x05090000 0 0x9000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src", "gcc_gpu_gpll0_div_clk_src"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>; reg-names = "stm-base", "stm-stimulus-base"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { stm_out: endpoint { remote-endpoint = <&funnel0_in7>; }; }; }; }; funnel@6041000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06041000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { funnel0_out: endpoint { remote-endpoint = <&merge_funnel_in0>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@7 { reg = <7>; funnel0_in7: endpoint { remote-endpoint = <&stm_out>; }; }; }; }; funnel@6042000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06042000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { funnel1_out: endpoint { remote-endpoint = <&merge_funnel_in1>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@4 { reg = <4>; funnel1_in4: endpoint { remote-endpoint = <&apss_merge_funnel_out>; }; }; }; }; funnel@6045000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06045000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { merge_funnel_out: endpoint { remote-endpoint = <&swao_funnel_in>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; merge_funnel_in0: endpoint { remote-endpoint = <&funnel0_out>; }; }; port@1 { reg = <1>; merge_funnel_in1: endpoint { remote-endpoint = <&funnel1_out>; }; }; }; }; replicator@6046000 { compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; reg = <0 0x06046000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { replicator_out: endpoint { remote-endpoint = <&etr_in>; }; }; }; in-ports { port { replicator_in: endpoint { remote-endpoint = <&swao_replicator_out>; }; }; }; }; etr@6048000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x06048000 0 0x1000>; iommus = <&apps_smmu 0x04a0 0x20>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,scatter-gather; in-ports { port { etr_in: endpoint { remote-endpoint = <&replicator_out>; }; }; }; }; funnel@6b04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06b04000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { swao_funnel_out: endpoint { remote-endpoint = <&etf_in>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@7 { reg = <7>; swao_funnel_in: endpoint { remote-endpoint = <&merge_funnel_out>; }; }; }; }; etf@6b05000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x06b05000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { etf_out: endpoint { remote-endpoint = <&swao_replicator_in>; }; }; }; in-ports { port { etf_in: endpoint { remote-endpoint = <&swao_funnel_out>; }; }; }; }; replicator@6b06000 { compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; reg = <0 0x06b06000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,replicator-loses-context; out-ports { port { swao_replicator_out: endpoint { remote-endpoint = <&replicator_in>; }; }; }; in-ports { port { swao_replicator_in: endpoint { remote-endpoint = <&etf_out>; }; }; }; }; etm@7040000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07040000 0 0x1000>; cpu = <&CPU0>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm0_out: endpoint { remote-endpoint = <&apss_funnel_in0>; }; }; }; }; etm@7140000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07140000 0 0x1000>; cpu = <&CPU1>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm1_out: endpoint { remote-endpoint = <&apss_funnel_in1>; }; }; }; }; etm@7240000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07240000 0 0x1000>; cpu = <&CPU2>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm2_out: endpoint { remote-endpoint = <&apss_funnel_in2>; }; }; }; }; etm@7340000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07340000 0 0x1000>; cpu = <&CPU3>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm3_out: endpoint { remote-endpoint = <&apss_funnel_in3>; }; }; }; }; etm@7440000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07440000 0 0x1000>; cpu = <&CPU4>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm4_out: endpoint { remote-endpoint = <&apss_funnel_in4>; }; }; }; }; etm@7540000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07540000 0 0x1000>; cpu = <&CPU5>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm5_out: endpoint { remote-endpoint = <&apss_funnel_in5>; }; }; }; }; etm@7640000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07640000 0 0x1000>; cpu = <&CPU6>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm6_out: endpoint { remote-endpoint = <&apss_funnel_in6>; }; }; }; }; etm@7740000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07740000 0 0x1000>; cpu = <&CPU7>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm7_out: endpoint { remote-endpoint = <&apss_funnel_in7>; }; }; }; }; funnel@7800000 { /* APSS Funnel */ compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x07800000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { apss_funnel_out: endpoint { remote-endpoint = <&apss_merge_funnel_in>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; apss_funnel_in0: endpoint { remote-endpoint = <&etm0_out>; }; }; port@1 { reg = <1>; apss_funnel_in1: endpoint { remote-endpoint = <&etm1_out>; }; }; port@2 { reg = <2>; apss_funnel_in2: endpoint { remote-endpoint = <&etm2_out>; }; }; port@3 { reg = <3>; apss_funnel_in3: endpoint { remote-endpoint = <&etm3_out>; }; }; port@4 { reg = <4>; apss_funnel_in4: endpoint { remote-endpoint = <&etm4_out>; }; }; port@5 { reg = <5>; apss_funnel_in5: endpoint { remote-endpoint = <&etm5_out>; }; }; port@6 { reg = <6>; apss_funnel_in6: endpoint { remote-endpoint = <&etm6_out>; }; }; port@7 { reg = <7>; apss_funnel_in7: endpoint { remote-endpoint = <&etm7_out>; }; }; }; }; funnel@7810000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x07810000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { apss_merge_funnel_out: endpoint { remote-endpoint = <&funnel1_in4>; }; }; }; in-ports { port { apss_merge_funnel_in: endpoint { remote-endpoint = <&apss_funnel_out>; }; }; }; }; sdhc_2: sdhci@8804000 { compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; iommus = <&apps_smmu 0x80 0>; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; clock-names = "core", "iface"; interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&sdhc2_opp_table>; bus-width = <4>; status = "disabled"; sdhc2_opp_table: sdhc2-opp-table { compatible = "operating-points-v2"; opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <160000 100000>; opp-avg-kBps = <80000 50000>; }; opp-202000000 { opp-hz = /bits/ 64 <202000000>; required-opps = <&rpmhpd_opp_svs_l1>; opp-peak-kBps = <200000 120000>; opp-avg-kBps = <100000 60000>; }; }; }; qspi_opp_table: qspi-opp-table { compatible = "operating-points-v2"; opp-75000000 { opp-hz = /bits/ 64 <75000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-150000000 { opp-hz = /bits/ 64 <150000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>; required-opps = <&rpmhpd_opp_nom>; }; }; qspi: spi@88dc000 { compatible = "qcom,qspi-v1"; reg = <0 0x088dc000 0 0x600>; #address-cells = <1>; #size-cells = <0>; interrupts = ; clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <&gcc GCC_QSPI_CORE_CLK>; clock-names = "iface", "core"; interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QSPI_0 0>; interconnect-names = "qspi-config"; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qspi_opp_table>; status = "disabled"; }; usb_1_hsphy: phy@88e3000 { compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; reg = <0 0x088e3000 0 0x400>; status = "disabled"; #phy-cells = <0>; clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "cfg_ahb", "ref"; resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; nvmem-cells = <&qusb2p_hstx_trim>; }; usb_1_qmpphy: phy-wrapper@88e9000 { compatible = "qcom,sc7180-qmp-usb3-phy"; reg = <0 0x088e9000 0 0x18c>, <0 0x088e8000 0 0x38>; reg-names = "reg-base", "dp_com"; status = "disabled"; #clock-cells = <1>; #address-cells = <2>; #size-cells = <2>; ranges; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, <&gcc GCC_USB3_PRIM_CLKREF_CLK>, <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; clock-names = "aux", "cfg_ahb", "ref", "com_aux"; resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; reset-names = "phy", "common"; usb_1_ssphy: phy@88e9200 { reg = <0 0x088e9200 0 0x128>, <0 0x088e9400 0 0x200>, <0 0x088e9c00 0 0x218>, <0 0x088e9600 0 0x128>, <0 0x088e9800 0 0x200>, <0 0x088e9a00 0 0x18>; #clock-cells = <0>; #phy-cells = <0>; clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; clock-names = "pipe0"; clock-output-names = "usb3_phy_pipe_clk_src"; }; }; dc_noc: interconnect@9160000 { compatible = "qcom,sc7180-dc-noc"; reg = <0 0x09160000 0 0x03200>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; system-cache-controller@9200000 { compatible = "qcom,sc7180-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; reg-names = "llcc_base", "llcc_broadcast_base"; interrupts = ; }; gem_noc: interconnect@9680000 { compatible = "qcom,sc7180-gem-noc"; reg = <0 0x09680000 0 0x3e200>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; npu_noc: interconnect@9990000 { compatible = "qcom,sc7180-npu-noc"; reg = <0 0x09990000 0 0x1600>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; usb_1: usb@a6f8800 { compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; status = "disabled"; #address-cells = <2>; #size-cells = <2>; ranges; dma-ranges; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB30_PRIM_SLEEP_CLK>; clock-names = "cfg_noc", "core", "iface", "mock_utmi", "sleep"; assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <150000000>; interrupts = , , , ; interrupt-names = "hs_phy_irq", "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; resets = <&gcc GCC_USB30_PRIM_BCR>; interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; interconnect-names = "usb-ddr", "apps-usb"; usb_1_dwc3: dwc3@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xe000>; interrupts = ; iommus = <&apps_smmu 0x540 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; phys = <&usb_1_hsphy>, <&usb_1_ssphy>; phy-names = "usb2-phy", "usb3-phy"; maximum-speed = "super-speed"; }; }; venus: video-codec@aa00000 { compatible = "qcom,sc7180-venus"; reg = <0 0x0aa00000 0 0xff000>; interrupts = ; power-domains = <&videocc VENUS_GDSC>, <&videocc VCODEC0_GDSC>, <&rpmhpd SC7180_CX>; power-domain-names = "venus", "vcodec0", "cx"; operating-points-v2 = <&venus_opp_table>; clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, <&videocc VIDEO_CC_VENUS_AHB_CLK>, <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; clock-names = "core", "iface", "bus", "vcodec0_core", "vcodec0_bus"; iommus = <&apps_smmu 0x0c00 0x60>; memory-region = <&venus_mem>; interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; interconnect-names = "video-mem", "cpu-cfg"; video-decoder { compatible = "venus-decoder"; }; video-encoder { compatible = "venus-encoder"; }; venus_opp_table: venus-opp-table { compatible = "operating-points-v2"; opp-150000000 { opp-hz = /bits/ 64 <150000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-270000000 { opp-hz = /bits/ 64 <270000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-340000000 { opp-hz = /bits/ 64 <340000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-434000000 { opp-hz = /bits/ 64 <434000000>; required-opps = <&rpmhpd_opp_nom>; }; opp-500000097 { opp-hz = /bits/ 64 <500000097>; required-opps = <&rpmhpd_opp_turbo>; }; }; }; videocc: clock-controller@ab00000 { compatible = "qcom,sc7180-videocc"; reg = <0 0x0ab00000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "bi_tcxo"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; camnoc_virt: interconnect@ac00000 { compatible = "qcom,sc7180-camnoc-virt"; reg = <0 0x0ac00000 0 0x1000>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; camcc: clock-controller@ad00000 { compatible = "qcom,sc7180-camcc"; reg = <0 0x0ad00000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_CAMERA_AHB_CLK>, <&gcc GCC_CAMERA_XO_CLK>; clock-names = "bi_tcxo", "iface", "xo"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; mdss: mdss@ae00000 { compatible = "qcom,sc7180-mdss"; reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; power-domains = <&dispcc MDSS_GDSC>; clocks = <&gcc GCC_DISP_AHB_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "ahb", "core"; assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; assigned-clock-rates = <300000000>; interrupts = ; interrupt-controller; #interrupt-cells = <1>; interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "mdp0-mem"; iommus = <&apps_smmu 0x800 0x2>; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; mdp: mdp@ae01000 { compatible = "qcom,sc7180-dpu"; reg = <0 0x0ae01000 0 0x8f000>, <0 0x0aeb0000 0 0x2008>; reg-names = "mdp", "vbif"; clocks = <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_ROT_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "bus", "iface", "rot", "lut", "core", "vsync"; assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_ROT_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>; assigned-clock-rates = <300000000>, <19200000>, <19200000>, <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SC7180_CX>; interrupt-parent = <&mdss>; interrupts = <0>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dpu_intf1_out: endpoint { remote-endpoint = <&dsi0_in>; }; }; }; mdp_opp_table: mdp-opp-table { compatible = "operating-points-v2"; opp-200000000 { opp-hz = /bits/ 64 <200000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-345000000 { opp-hz = /bits/ 64 <345000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-460000000 { opp-hz = /bits/ 64 <460000000>; required-opps = <&rpmhpd_opp_nom>; }; }; }; dsi0: dsi@ae94000 { compatible = "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; interrupts = <4>; clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK>, <&dispcc DISP_CC_MDSS_ESC0_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>; clock-names = "byte", "byte_intf", "pixel", "core", "iface", "bus"; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SC7180_CX>; phys = <&dsi_phy>; phy-names = "dsi"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dsi0_in: endpoint { remote-endpoint = <&dpu_intf1_out>; }; }; port@1 { reg = <1>; dsi0_out: endpoint { }; }; }; dsi_opp_table: dsi-opp-table { compatible = "operating-points-v2"; opp-187500000 { opp-hz = /bits/ 64 <187500000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-358000000 { opp-hz = /bits/ 64 <358000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; }; }; dsi_phy: dsi-phy@ae94400 { compatible = "qcom,dsi-phy-10nm"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, <0 0x0ae94a00 0 0x1e0>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; #clock-cells = <1>; #phy-cells = <0>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "ref"; status = "disabled"; }; }; dispcc: clock-controller@af00000 { compatible = "qcom,sc7180-dispcc"; reg = <0 0x0af00000 0 0x200000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&dsi_phy 0>, <&dsi_phy 1>, <0>, <0>; clock-names = "bi_tcxo", "gcc_disp_gpll0_clk_src", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk", "dp_phy_pll_link_clk", "dp_phy_pll_vco_div_clk"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; pdc: interrupt-controller@b220000 { compatible = "qcom,sc7180-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>; qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupt-controller; }; pdc_reset: reset-controller@b2e0000 { compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; reg = <0 0x0b2e0000 0 0x20000>; #reset-cells = <1>; }; tsens0: thermal-sensor@c263000 { compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; reg = <0 0x0c263000 0 0x1ff>, /* TM */ <0 0x0c222000 0 0x1ff>; /* SROT */ #qcom,sensors = <15>; interrupts = , ; interrupt-names = "uplow","critical"; #thermal-sensor-cells = <1>; }; tsens1: thermal-sensor@c265000 { compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; reg = <0 0x0c265000 0 0x1ff>, /* TM */ <0 0x0c223000 0 0x1ff>; /* SROT */ #qcom,sensors = <10>; interrupts = , ; interrupt-names = "uplow","critical"; #thermal-sensor-cells = <1>; }; aoss_reset: reset-controller@c2a0000 { compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; reg = <0 0x0c2a0000 0 0x31000>; #reset-cells = <1>; }; aoss_qmp: qmp@c300000 { compatible = "qcom,sc7180-aoss-qmp"; reg = <0 0x0c300000 0 0x100000>; interrupts = ; mboxes = <&apss_shared 0>; #clock-cells = <0>; #power-domain-cells = <1>; }; spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>, <0 0x0c600000 0 0x2000000>, <0 0x0e600000 0 0x100000>, <0 0x0e700000 0 0xa0000>, <0 0x0c40a000 0 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <1>; #size-cells = <1>; interrupt-controller; #interrupt-cells = <4>; cell-index = <0>; }; apps_smmu: iommu@15000000 { compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; #iommu-cells = <2>; #global-interrupts = <1>; interrupts = , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ; }; intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; #address-cells = <2>; #size-cells = <2>; ranges; #interrupt-cells = <3>; interrupt-controller; reg = <0 0x17a00000 0 0x10000>, /* GICD */ <0 0x17a60000 0 0x100000>; /* GICR * 8 */ interrupts = ; msi-controller@17a40000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0 0x17a40000 0 0x20000>; status = "disabled"; }; }; apss_shared: mailbox@17c00000 { compatible = "qcom,sc7180-apss-shared"; reg = <0 0x17c00000 0 0x10000>; #mbox-cells = <1>; }; watchdog@17c10000 { compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; reg = <0 0x17c10000 0 0x1000>; clocks = <&sleep_clk>; interrupts = ; }; timer@17c20000{ #address-cells = <2>; #size-cells = <2>; ranges; compatible = "arm,armv7-timer-mem"; reg = <0 0x17c20000 0 0x1000>; frame@17c21000 { frame-number = <0>; interrupts = , ; reg = <0 0x17c21000 0 0x1000>, <0 0x17c22000 0 0x1000>; }; frame@17c23000 { frame-number = <1>; interrupts = ; reg = <0 0x17c23000 0 0x1000>; status = "disabled"; }; frame@17c25000 { frame-number = <2>; interrupts = ; reg = <0 0x17c25000 0 0x1000>; status = "disabled"; }; frame@17c27000 { frame-number = <3>; interrupts = ; reg = <0 0x17c27000 0 0x1000>; status = "disabled"; }; frame@17c29000 { frame-number = <4>; interrupts = ; reg = <0 0x17c29000 0 0x1000>; status = "disabled"; }; frame@17c2b000 { frame-number = <5>; interrupts = ; reg = <0 0x17c2b000 0 0x1000>; status = "disabled"; }; frame@17c2d000 { frame-number = <6>; interrupts = ; reg = <0 0x17c2d000 0 0x1000>; status = "disabled"; }; }; apps_rsc: rsc@18200000 { compatible = "qcom,rpmh-rsc"; reg = <0 0x18200000 0 0x10000>, <0 0x18210000 0 0x10000>, <0 0x18220000 0 0x10000>; reg-names = "drv-0", "drv-1", "drv-2"; interrupts = , , ; qcom,tcs-offset = <0xd00>; qcom,drv-id = <2>; qcom,tcs-config = , , , ; rpmhcc: clock-controller { compatible = "qcom,sc7180-rpmh-clk"; clocks = <&xo_board>; clock-names = "xo"; #clock-cells = <1>; }; rpmhpd: power-controller { compatible = "qcom,sc7180-rpmhpd"; #power-domain-cells = <1>; operating-points-v2 = <&rpmhpd_opp_table>; rpmhpd_opp_table: opp-table { compatible = "operating-points-v2"; rpmhpd_opp_ret: opp1 { opp-level = ; }; rpmhpd_opp_min_svs: opp2 { opp-level = ; }; rpmhpd_opp_low_svs: opp3 { opp-level = ; }; rpmhpd_opp_svs: opp4 { opp-level = ; }; rpmhpd_opp_svs_l1: opp5 { opp-level = ; }; rpmhpd_opp_svs_l2: opp6 { opp-level = <224>; }; rpmhpd_opp_nom: opp7 { opp-level = ; }; rpmhpd_opp_nom_l1: opp8 { opp-level = ; }; rpmhpd_opp_nom_l2: opp9 { opp-level = ; }; rpmhpd_opp_turbo: opp10 { opp-level = ; }; rpmhpd_opp_turbo_l1: opp11 { opp-level = ; }; }; }; apps_bcm_voter: bcm_voter { compatible = "qcom,bcm-voter"; }; }; osm_l3: interconnect@18321000 { compatible = "qcom,sc7180-osm-l3"; reg = <0 0x18321000 0 0x1400>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; #interconnect-cells = <1>; }; cpufreq_hw: cpufreq@18323000 { compatible = "qcom,cpufreq-hw"; reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; reg-names = "freq-domain0", "freq-domain1"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; #freq-domain-cells = <1>; }; wifi: wifi@18800000 { compatible = "qcom,wcn3990-wifi"; reg = <0 0x18800000 0 0x800000>; reg-names = "membase"; iommus = <&apps_smmu 0xc0 0x1>; interrupts = , , , , , , , , , , , ; memory-region = <&wlan_mem>; qcom,msa-fixed-perm; status = "disabled"; }; lpasscc: clock-controller@62d00000 { compatible = "qcom,sc7180-lpasscorecc"; reg = <0 0x62d00000 0 0x50000>, <0 0x62780000 0 0x30000>; reg-names = "lpass_core_cc", "lpass_audio_cc"; clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "bi_tcxo"; power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; #clock-cells = <1>; #power-domain-cells = <1>; }; lpass_cpu: lpass@62f00000 { compatible = "qcom,sc7180-lpass-cpu"; reg = <0 0x62f00000 0 0x29000>; reg-names = "lpass-lpaif"; iommus = <&apps_smmu 0x1020 0>; power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; clock-names = "pcnoc-sway-clk", "audio-core", "mclk0", "pcnoc-mport-clk", "mi2s-bit-clk0", "mi2s-bit-clk1"; #sound-dai-cells = <1>; #address-cells = <1>; #size-cells = <0>; interrupts = ; interrupt-names = "lpass-irq-lpaif"; }; lpass_hm: clock-controller@63000000 { compatible = "qcom,sc7180-lpasshm"; reg = <0 0x63000000 0 0x28>; clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "bi_tcxo"; #clock-cells = <1>; #power-domain-cells = <1>; }; }; thermal-zones { cpu0_thermal: cpu0-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 1>; sustainable-power = <768>; trips { cpu0_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu0_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu0_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu0_alert0>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu0_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu1_thermal: cpu1-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 2>; sustainable-power = <768>; trips { cpu1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu1_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu1_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu1_alert0>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu1_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu2_thermal: cpu2-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 3>; sustainable-power = <768>; trips { cpu2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu2_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu2_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu2_alert0>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu2_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu3_thermal: cpu3-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 4>; sustainable-power = <768>; trips { cpu3_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu3_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu3_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu3_alert0>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu3_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu4_thermal: cpu4-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 5>; sustainable-power = <768>; trips { cpu4_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu4_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu4_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu4_alert0>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu4_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu5_thermal: cpu5-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 6>; sustainable-power = <768>; trips { cpu5_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu5_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu5_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu5_alert0>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu5_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu6_thermal: cpu6-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 9>; sustainable-power = <1202>; trips { cpu6_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu6_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu6_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu6_alert0>; cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu6_alert1>; cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu7_thermal: cpu7-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 10>; sustainable-power = <1202>; trips { cpu7_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu7_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu7_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu7_alert0>; cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu7_alert1>; cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu8_thermal: cpu8-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 11>; sustainable-power = <1202>; trips { cpu8_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu8_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu8_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu8_alert0>; cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu8_alert1>; cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu9_thermal: cpu9-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 12>; sustainable-power = <1202>; trips { cpu9_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu9_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu9_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu9_alert0>; cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu9_alert1>; cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; aoss0-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 0>; trips { aoss0_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; aoss0_crit: aoss0_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; }; cpuss0-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 7>; trips { cpuss0_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; cpuss0_crit: cluster0_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; }; cpuss1-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 8>; trips { cpuss1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; cpuss1_crit: cluster0_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; }; gpuss0-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 13>; trips { gpuss0_alert0: trip-point0 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; gpuss0_crit: gpuss0_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&gpuss0_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; gpuss1-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 14>; trips { gpuss1_alert0: trip-point0 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; gpuss1_crit: gpuss1_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&gpuss1_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; aoss1-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 0>; trips { aoss1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; aoss1_crit: aoss1_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; }; cwlan-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 1>; trips { cwlan_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; cwlan_crit: cwlan_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; }; audio-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 2>; trips { audio_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; audio_crit: audio_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; }; ddr-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 3>; trips { ddr_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; ddr_crit: ddr_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; }; q6-hvx-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 4>; trips { q6_hvx_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; q6_hvx_crit: q6_hvx_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; }; camera-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 5>; trips { camera_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; camera_crit: camera_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; }; mdm-core-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 6>; trips { mdm_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; mdm_crit: mdm_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; }; mdm-dsp-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 7>; trips { mdm_dsp_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; mdm_dsp_crit: mdm_dsp_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; }; npu-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 8>; trips { npu_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; npu_crit: npu_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; }; video-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 9>; trips { video_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; video_crit: video_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; }; }; timer { compatible = "arm,armv8-timer"; interrupts = , , , ; }; };