From 932e98224d5602be17ed61d0e057e9326f12b59d Mon Sep 17 00:00:00 2001 From: Abhilash Kesavan Date: Tue, 28 Oct 2014 16:48:55 +0530 Subject: clk: samsung: exynos7: add gate clock for ADC block Add clock support for the ADC interface in Exynos7. Signed-off-by: Abhilash Kesavan Signed-off-by: Sylwester Nawrocki --- include/dt-bindings/clock/exynos7-clk.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/dt-bindings/clock/exynos7-clk.h') diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index f255bb7c64b3..8e4681b07ae7 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -55,7 +55,8 @@ #define PCLK_HSI2C11 9 #define PCLK_PWM 10 #define SCLK_PWM 11 -#define PERIC0_NR_CLK 12 +#define PCLK_ADCIF 12 +#define PERIC0_NR_CLK 13 /* PERIC1 */ #define PCLK_UART1 1 -- cgit v1.2.3