From 2ab2dfe5d4eef6bad8cdd90dc6bba5a7660273d4 Mon Sep 17 00:00:00 2001 From: Naveen Krishna Ch Date: Tue, 28 Oct 2014 16:48:54 +0530 Subject: clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks Add clock support for the watchdog timer, pwm timer and thermal management unit IPs in Exynos7. Signed-off-by: Naveen Krishna Ch Signed-off-by: Abhilash Kesavan Signed-off-by: Sylwester Nawrocki --- include/dt-bindings/clock/exynos7-clk.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'include/dt-bindings/clock/exynos7-clk.h') diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index dd89aa0f84e1..f255bb7c64b3 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -53,7 +53,9 @@ #define PCLK_HSI2C9 7 #define PCLK_HSI2C10 8 #define PCLK_HSI2C11 9 -#define PERIC0_NR_CLK 10 +#define PCLK_PWM 10 +#define SCLK_PWM 11 +#define PERIC0_NR_CLK 12 /* PERIC1 */ #define PCLK_UART1 1 @@ -72,7 +74,10 @@ /* PERIS */ #define PCLK_CHIPID 1 #define SCLK_CHIPID 2 -#define PERIS_NR_CLK 3 +#define PCLK_WDT 3 +#define PCLK_TMU 4 +#define SCLK_TMU 5 +#define PERIS_NR_CLK 6 /* FSYS0 */ #define ACLK_MMC2 1 -- cgit v1.2.3