From ba1eb1d825fdef40f69871caf8e5842d00efbbc5 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 14 Oct 2008 19:55:10 -0700 Subject: i915: Map status page cached for chips with GTT-based HWS location. This should improve performance by avoiding uncached reads by the CPU (the point of having a status page), and may improve stability. This patch only affects G33, GM45 and G45 chips as those are the only ones using GTT-based HWS mappings. Signed-off-by: Keith Packard Signed-off-by: Eric Anholt Signed-off-by: Dave Airlie --- include/drm/drmP.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/drm') diff --git a/include/drm/drmP.h b/include/drm/drmP.h index 90a9e0247d58..59c796b46ee7 100644 --- a/include/drm/drmP.h +++ b/include/drm/drmP.h @@ -1016,7 +1016,8 @@ extern int drm_bind_agp(DRM_AGP_MEM * handle, unsigned int start); extern DRM_AGP_MEM *drm_agp_bind_pages(struct drm_device *dev, struct page **pages, unsigned long num_pages, - uint32_t gtt_offset); + uint32_t gtt_offset, + uint32_t type); extern int drm_unbind_agp(DRM_AGP_MEM * handle); /* Misc. IOCTL support (drm_ioctl.h) */ -- cgit v1.2.3