From 77f36b27127630f326d6967318159e938a4137dd Mon Sep 17 00:00:00 2001 From: Zeyu Fan Date: Mon, 13 Feb 2017 11:49:07 -0500 Subject: drm/amd/display: Fix logic that causes segfault on DP display. Signed-off-by: Zeyu Fan Acked-by: Jordan Lazare Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 87eba4be3249..26742e038274 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -852,17 +852,19 @@ static bool dce110_program_pix_clk( * during PLL Reset, but they do not have effect * until SS_EN is asserted.*/ if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL - && pix_clk_params->flags.ENABLE_SS && !dc_is_dp_signal( - pix_clk_params->signal_type)) { - if (!enable_spread_spectrum(clk_src, - pix_clk_params->signal_type, - pll_settings)) - return false; + && !dc_is_dp_signal(pix_clk_params->signal_type)) { + + if (pix_clk_params->flags.ENABLE_SS) + if (!enable_spread_spectrum(clk_src, + pix_clk_params->signal_type, + pll_settings)) + return false; + + /* Resync deep color DTO */ + dce110_program_pixel_clk_resync(clk_src, + pix_clk_params->signal_type, + pix_clk_params->color_depth); } - /* Resync deep color DTO */ - dce110_program_pixel_clk_resync(clk_src, - pix_clk_params->signal_type, - pix_clk_params->color_depth); break; case DCE_VERSION_11_2: -- cgit v1.2.3