From ba96de3ae5a7e2121cac80053b277eb2ab51a0ae Mon Sep 17 00:00:00 2001 From: Zou Wei Date: Tue, 11 May 2021 11:55:50 +0800 Subject: soc: mediatek: add missing MODULE_DEVICE_TABLE This patch adds missing MODULE_DEVICE_TABLE definition which generates correct modalias for automatic loading of this driver when it is built as an external module. Reported-by: Hulk Robot Signed-off-by: Zou Wei Link: https://lore.kernel.org/r/1620705350-104687-1-git-send-email-zou_wei@huawei.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-devapc.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c index f1cea041dc5a..7c65ad3d1f8a 100644 --- a/drivers/soc/mediatek/mtk-devapc.c +++ b/drivers/soc/mediatek/mtk-devapc.c @@ -234,6 +234,7 @@ static const struct of_device_id mtk_devapc_dt_match[] = { }, { }, }; +MODULE_DEVICE_TABLE(of, mtk_devapc_dt_match); static int mtk_devapc_probe(struct platform_device *pdev) { -- cgit v1.2.3 From eed6ff1bb2da65067d928f4ab322c7d75f944fa4 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Tue, 1 Jun 2021 11:59:04 +0800 Subject: soc: mtk-pm-domains: do not register smi node as syscon Mediatek requires mmsys clocks to be unprepared during suspend, otherwise system has chances to hang. syscon_regmap_lookup_by_phandle_optional() will attach and prepare the first clock in smi node, leading to additional prepare to the clock which is not balanced with the prepare/unprepare pair in resume/suspend callbacks. If a power domain node requests an smi node and the smi node's first clock is an mmsys clock, it will results in an unstable suspend resume. Fixes: f414854c8843 ("soc: mediatek: pm-domains: Add SMI block as bus protection block") Signed-off-by: Hsin-Yi Wang Reviewed-by: chun-jie.chen Reviewed-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20210601035905.2970384-2-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-pm-domains.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 0af00efa0ef8..22fa52f0e86e 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -297,6 +297,7 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no const struct scpsys_domain_data *domain_data; struct scpsys_domain *pd; struct device_node *root_node = scpsys->dev->of_node; + struct device_node *smi_node; struct property *prop; const char *clk_name; int i, ret, num_clks; @@ -352,9 +353,13 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no if (IS_ERR(pd->infracfg)) return ERR_CAST(pd->infracfg); - pd->smi = syscon_regmap_lookup_by_phandle_optional(node, "mediatek,smi"); - if (IS_ERR(pd->smi)) - return ERR_CAST(pd->smi); + smi_node = of_parse_phandle(node, "mediatek,smi", 0); + if (smi_node) { + pd->smi = device_node_to_regmap(smi_node); + of_node_put(smi_node); + if (IS_ERR(pd->smi)) + return ERR_CAST(pd->smi); + } num_clks = of_clk_get_parent_count(node); if (num_clks > 0) { -- cgit v1.2.3 From f0fce06e345dc4f75c1cdd21840780f5fe2df1f3 Mon Sep 17 00:00:00 2001 From: Weiyi Lu Date: Tue, 1 Jun 2021 11:59:03 +0800 Subject: soc: mtk-pm-domains: Fix the clock prepared issue In this new power domain driver, when adding one power domain it will prepare the dependent clocks at the same. So we only do clk_bulk_enable/disable control during power ON/OFF. When system suspend, the pm runtime framework will forcely power off power domains. However, the dependent clocks are disabled but kept prepared. In MediaTek clock drivers, PLL would be turned ON when we do clk_bulk_prepare control. Clock hierarchy: PLL --> DIV_CK --> CLK_MUX (may be dependent clocks) --> SUBSYS_CG (may be dependent clocks) It will lead some unexpected clock states during system suspend. This patch will fix by doing prepare_enable/disable_unprepare on dependent clocks at the same time while we are going to power on/off any power domain. Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains") Signed-off-by: Weiyi Lu Signed-off-by: Hsin-Yi Wang Reviewed-by: chun-jie.chen Reviewed-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20210601035905.2970384-1-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-pm-domains.c | 31 ++++++++----------------------- 1 file changed, 8 insertions(+), 23 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 22fa52f0e86e..b762bc40f56b 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -211,7 +211,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) if (ret) return ret; - ret = clk_bulk_enable(pd->num_clks, pd->clks); + ret = clk_bulk_prepare_enable(pd->num_clks, pd->clks); if (ret) goto err_reg; @@ -229,7 +229,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); - ret = clk_bulk_enable(pd->num_subsys_clks, pd->subsys_clks); + ret = clk_bulk_prepare_enable(pd->num_subsys_clks, pd->subsys_clks); if (ret) goto err_pwr_ack; @@ -246,9 +246,9 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) err_disable_sram: scpsys_sram_disable(pd); err_disable_subsys_clks: - clk_bulk_disable(pd->num_subsys_clks, pd->subsys_clks); + clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); err_pwr_ack: - clk_bulk_disable(pd->num_clks, pd->clks); + clk_bulk_disable_unprepare(pd->num_clks, pd->clks); err_reg: scpsys_regulator_disable(pd->supply); return ret; @@ -269,7 +269,7 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) if (ret < 0) return ret; - clk_bulk_disable(pd->num_subsys_clks, pd->subsys_clks); + clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); /* subsys power off */ regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); @@ -284,7 +284,7 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) if (ret < 0) return ret; - clk_bulk_disable(pd->num_clks, pd->clks); + clk_bulk_disable_unprepare(pd->num_clks, pd->clks); scpsys_regulator_disable(pd->supply); @@ -410,14 +410,6 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no pd->subsys_clks[i].clk = clk; } - ret = clk_bulk_prepare(pd->num_clks, pd->clks); - if (ret) - goto err_put_subsys_clocks; - - ret = clk_bulk_prepare(pd->num_subsys_clks, pd->subsys_clks); - if (ret) - goto err_unprepare_clocks; - /* * Initially turn on all domains to make the domains usable * with !CONFIG_PM and to get the hardware in sync with the @@ -432,7 +424,7 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no ret = scpsys_power_on(&pd->genpd); if (ret < 0) { dev_err(scpsys->dev, "%pOF: failed to power on domain: %d\n", node, ret); - goto err_unprepare_clocks; + goto err_put_subsys_clocks; } } @@ -440,7 +432,7 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no ret = -EINVAL; dev_err(scpsys->dev, "power domain with id %d already exists, check your device-tree\n", id); - goto err_unprepare_subsys_clocks; + goto err_put_subsys_clocks; } if (!pd->data->name) @@ -460,10 +452,6 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no return scpsys->pd_data.domains[id]; -err_unprepare_subsys_clocks: - clk_bulk_unprepare(pd->num_subsys_clks, pd->subsys_clks); -err_unprepare_clocks: - clk_bulk_unprepare(pd->num_clks, pd->clks); err_put_subsys_clocks: clk_bulk_put(pd->num_subsys_clks, pd->subsys_clks); err_put_clocks: @@ -542,10 +530,7 @@ static void scpsys_remove_one_domain(struct scpsys_domain *pd) "failed to remove domain '%s' : %d - state may be inconsistent\n", pd->genpd.name, ret); - clk_bulk_unprepare(pd->num_clks, pd->clks); clk_bulk_put(pd->num_clks, pd->clks); - - clk_bulk_unprepare(pd->num_subsys_clks, pd->subsys_clks); clk_bulk_put(pd->num_subsys_clks, pd->subsys_clks); } -- cgit v1.2.3 From e88edc977b00cc467d598e4ea5091b8bb4a7f78d Mon Sep 17 00:00:00 2001 From: Henry Chen Date: Wed, 2 Jun 2021 19:20:50 +0800 Subject: soc: mediatek: pwrap: add pwrap driver for MT8195 SoC MT8195 are highly integrated SoC and use PMIC_MT6359 for power management. This patch adds pwrap master driver to access PMIC_MT6359. Signed-off-by: Henry Chen Link: https://lore.kernel.org/r/20210602112050.12338-3-james.lo@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-pmic-wrap.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index e4de75f35c33..952bc554f443 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -961,6 +961,23 @@ static int mt8183_regs[] = { [PWRAP_WACS2_VLDCLR] = 0xC28, }; +static int mt8195_regs[] = { + [PWRAP_INIT_DONE2] = 0x0, + [PWRAP_STAUPD_CTRL] = 0x4C, + [PWRAP_TIMER_EN] = 0x3E4, + [PWRAP_INT_EN] = 0x420, + [PWRAP_INT_FLG] = 0x428, + [PWRAP_INT_CLR] = 0x42C, + [PWRAP_INT1_EN] = 0x450, + [PWRAP_INT1_FLG] = 0x458, + [PWRAP_INT1_CLR] = 0x45C, + [PWRAP_WACS2_CMD] = 0x880, + [PWRAP_SWINF_2_WDATA_31_0] = 0x884, + [PWRAP_SWINF_2_RDATA_31_0] = 0x894, + [PWRAP_WACS2_VLDCLR] = 0x8A4, + [PWRAP_WACS2_RDATA] = 0x8A8, +}; + static int mt8516_regs[] = { [PWRAP_MUX_SEL] = 0x0, [PWRAP_WRAP_EN] = 0x4, @@ -1066,6 +1083,7 @@ enum pwrap_type { PWRAP_MT8135, PWRAP_MT8173, PWRAP_MT8183, + PWRAP_MT8195, PWRAP_MT8516, }; @@ -1525,6 +1543,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) break; case PWRAP_MT6873: case PWRAP_MT8183: + case PWRAP_MT8195: break; } @@ -2025,6 +2044,19 @@ static const struct pmic_wrapper_type pwrap_mt8183 = { .init_soc_specific = pwrap_mt8183_init_soc_specific, }; +static struct pmic_wrapper_type pwrap_mt8195 = { + .regs = mt8195_regs, + .type = PWRAP_MT8195, + .arb_en_all = 0x777f, /* NEED CONFIRM */ + .int_en_all = 0x180000, /* NEED CONFIRM */ + .int1_en_all = 0, + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src = PWRAP_WDT_SRC_MASK_ALL, + .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB, + .init_reg_clock = pwrap_common_init_reg_clock, + .init_soc_specific = NULL, +}; + static struct pmic_wrapper_type pwrap_mt8516 = { .regs = mt8516_regs, .type = PWRAP_MT8516, @@ -2065,6 +2097,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = { }, { .compatible = "mediatek,mt8183-pwrap", .data = &pwrap_mt8183, + }, { + .compatible = "mediatek,mt8195-pwrap", + .data = &pwrap_mt8195, }, { .compatible = "mediatek,mt8516-pwrap", .data = &pwrap_mt8516, -- cgit v1.2.3