From e5c3b3e9f012b8862753a04f03c6e27344332718 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Tue, 31 Jan 2017 16:36:32 -0600 Subject: PCI: iproc: Use of_device_get_match_data() to simplify probe The only way to call iproc_pcie_pltfm_probe() is to match an entry in iproc_pcie_of_match_table[], so match cannot be NULL. Use of_device_get_match_data() to retrieve the pcie->type. No functional change intended. Based-on-suggestion-from: Geert Uytterhoeven Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pcie-iproc-platform.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'drivers/pci') diff --git a/drivers/pci/host/pcie-iproc-platform.c b/drivers/pci/host/pcie-iproc-platform.c index 22d814a78a78..f4909bb0b2ad 100644 --- a/drivers/pci/host/pcie-iproc-platform.c +++ b/drivers/pci/host/pcie-iproc-platform.c @@ -47,7 +47,6 @@ MODULE_DEVICE_TABLE(of, iproc_pcie_of_match_table); static int iproc_pcie_pltfm_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - const struct of_device_id *of_id; struct iproc_pcie *pcie; struct device_node *np = dev->of_node; struct resource reg; @@ -55,16 +54,12 @@ static int iproc_pcie_pltfm_probe(struct platform_device *pdev) LIST_HEAD(res); int ret; - of_id = of_match_device(iproc_pcie_of_match_table, dev); - if (!of_id) - return -EINVAL; - pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) return -ENOMEM; pcie->dev = dev; - pcie->type = (enum iproc_pcie_type)of_id->data; + pcie->type = (enum iproc_pcie_type) of_device_get_match_data(dev); ret = of_address_to_resource(np, 0, ®); if (ret < 0) { -- cgit v1.2.3 From 4d4836ab70d3c59bc934d244f0cccdd035c1ead8 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Fri, 27 Jan 2017 16:44:08 -0500 Subject: PCI: iproc: Configure PCIe MPS settings Make sure PCIe MPS settings are valid when we enumerate a new hierarchy. [bhelgaas: changelog] Signed-off-by: Jon Mason Signed-off-by: Bjorn Helgaas Acked-by: Ray Jui --- drivers/pci/host/pcie-iproc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/pci') diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c index 3ebc025499b9..0f39bd2a04cb 100644 --- a/drivers/pci/host/pcie-iproc.c +++ b/drivers/pci/host/pcie-iproc.c @@ -1205,7 +1205,7 @@ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res) struct device *dev; int ret; void *sysdata; - struct pci_bus *bus; + struct pci_bus *bus, *child; dev = pcie->dev; @@ -1278,6 +1278,9 @@ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res) if (pcie->map_irq) pci_fixup_irqs(pci_common_swizzle, pcie->map_irq); + list_for_each_entry(child, &bus->children, node) + pcie_bus_configure_settings(child); + pci_bus_add_devices(bus); return 0; -- cgit v1.2.3 From ce709f86501a013e941e9986cb072eae375ddf3e Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Fri, 27 Jan 2017 16:44:09 -0500 Subject: PCI: Add Broadcom Northstar2 PAXC quirk for device class and MPSS The Broadcom Northstar2 SoC has a number of quirks for the PAXC (internal/fake) PCI bus. Specifically, the PCI config space is shared between the root port and the first PF (ie., PF0), and a number of fields are tied to zero (thus preventing them from being set). These cannot be "fixed" in device firmware, so we must fix them with a quirk. Signed-off-by: Jon Mason Signed-off-by: Bjorn Helgaas --- drivers/pci/quirks.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'drivers/pci') diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 1800befa8b8b..c5ef20a6c937 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2239,6 +2239,27 @@ DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5719, quirk_brcm_5719_limit_mrrs); +#ifdef CONFIG_PCIE_IPROC_PLATFORM +static void quirk_paxc_bridge(struct pci_dev *pdev) +{ + /* The PCI config space is shared with the PAXC root port and the first + * Ethernet device. So, we need to workaround this by telling the PCI + * code that the bridge is not an Ethernet device. + */ + if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) + pdev->class = PCI_CLASS_BRIDGE_PCI << 8; + + /* MPSS is not being set properly (as it is currently 0). This is + * because that area of the PCI config space is hard coded to zero, and + * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS) + * so that the MPS can be set to the real max value. + */ + pdev->pcie_mpss = 2; +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge); +#endif + /* Originally in EDAC sources for i82875P: * Intel tells BIOS developers to hide device 6 which * configures the overflow device access containing -- cgit v1.2.3