From 4352aa5bbf1d0080c2dcf904ce1e4be0a1cb5937 Mon Sep 17 00:00:00 2001 From: Alexander Duyck Date: Thu, 25 Mar 2010 13:03:30 -0700 Subject: PCI aerdrv: use correct bit defines and add 2ms delay to aer_root_reset While testing completion timeouts I found that hardware was not recovering. It looks like the hot reset was never being propagated to the endpoint devices on the bus due to the fact that we were clearing the bit too quickly. The documentation I have states that we should be transmitting hot reset TS1s for 2ms. To achieve this I have added a 2ms delay from the time we set the secondary bus reset bit to the time we clear it. In addition I changed the define used for the secondary bus reset bit to match the register define that was being used. Reviewed-by: Hidetoshi Seto Signed-off-by: Alexander Duyck Signed-off-by: Jesse Barnes --- drivers/pci/pcie/aer/aerdrv.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers/pci') diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c index aa495ad9bbd4..7a711ee314b7 100644 --- a/drivers/pci/pcie/aer/aerdrv.c +++ b/drivers/pci/pcie/aer/aerdrv.c @@ -244,11 +244,17 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev) /* Assert Secondary Bus Reset */ pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &p2p_ctrl); - p2p_ctrl |= PCI_CB_BRIDGE_CTL_CB_RESET; + p2p_ctrl |= PCI_BRIDGE_CTL_BUS_RESET; pci_write_config_word(dev, PCI_BRIDGE_CONTROL, p2p_ctrl); + /* + * we should send hot reset message for 2ms to allow it time to + * propogate to all downstream ports + */ + msleep(2); + /* De-assert Secondary Bus Reset */ - p2p_ctrl &= ~PCI_CB_BRIDGE_CTL_CB_RESET; + p2p_ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; pci_write_config_word(dev, PCI_BRIDGE_CONTROL, p2p_ctrl); /* -- cgit v1.2.3