From 549ce8f134bd95a1d4bf1a62215a62f1e9408a96 Mon Sep 17 00:00:00 2001 From: Zubair Lutfullah Kakakhel Date: Fri, 12 Aug 2016 12:48:52 +0100 Subject: misc: pch_phub: Read prefetch value from device tree if passed The default prefetch value for the eg20t device is hard coded to 0x000affaa. Add support for an alternative to be read from DT if available Signed-off-by: Zubair Lutfullah Kakakhel Signed-off-by: Greg Kroah-Hartman --- drivers/misc/pch_phub.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'drivers/misc/pch_phub.c') diff --git a/drivers/misc/pch_phub.c b/drivers/misc/pch_phub.c index 4810e039bbec..1dd18f500730 100644 --- a/drivers/misc/pch_phub.c +++ b/drivers/misc/pch_phub.c @@ -28,6 +28,7 @@ #include #include #include +#include #define PHUB_STATUS 0x00 /* Status Register offset */ #define PHUB_CONTROL 0x04 /* Control Register offset */ @@ -711,6 +712,12 @@ static int pch_phub_probe(struct pci_dev *pdev, if (id->driver_data == 1) { /* EG20T PCH */ const char *board_name; + unsigned int prefetch = 0x000affaa; + + if (pdev->dev.of_node) + of_property_read_u32(pdev->dev.of_node, + "intel,eg20t-prefetch", + &prefetch); ret = sysfs_create_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr); @@ -736,7 +743,7 @@ static int pch_phub_probe(struct pci_dev *pdev, CLKCFG_UART_MASK); /* set the prefech value */ - iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14); + iowrite32(prefetch, chip->pch_phub_base_address + 0x14); /* set the interrupt delay value */ iowrite32(0x25, chip->pch_phub_base_address + 0x44); chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T; -- cgit v1.2.3 From bed3d7babafda16cf2e095366dec3f64143b370a Mon Sep 17 00:00:00 2001 From: Zubair Lutfullah Kakakhel Date: Fri, 12 Aug 2016 12:48:53 +0100 Subject: misc: pch_phub: Add UART_CLK quirk for Boston platform The EG20T has 4 UART blocks. The clock source for the UART block is configured to receive a clock from an external pin by default. An internal 25MHz clock in the EG20T can also be used as a clock source for the clock. The MIPS based Boston platform ties the external clock pin down and relies on the internal clock source for the UART to function. Boston is based on device tree. Add a quirk to allow Boston to be detected via device tree and set the correct clock source for UART. Signed-off-by: Zubair Lutfullah Kakakhel Signed-off-by: Greg Kroah-Hartman --- drivers/misc/pch_phub.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'drivers/misc/pch_phub.c') diff --git a/drivers/misc/pch_phub.c b/drivers/misc/pch_phub.c index 1dd18f500730..e42bdc90fa27 100644 --- a/drivers/misc/pch_phub.c +++ b/drivers/misc/pch_phub.c @@ -58,6 +58,7 @@ /* CM-iTC */ #define CLKCFG_UART_48MHZ (1 << 16) +#define CLKCFG_UART_25MHZ (2 << 16) #define CLKCFG_BAUDDIV (2 << 20) #define CLKCFG_PLL2VCO (8 << 9) #define CLKCFG_UARTCLKSEL (1 << 18) @@ -748,6 +749,16 @@ static int pch_phub_probe(struct pci_dev *pdev, iowrite32(0x25, chip->pch_phub_base_address + 0x44); chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T; chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T; + + /* quirk for MIPS Boston platform */ + if (pdev->dev.of_node) { + if (of_machine_is_compatible("img,boston")) { + pch_phub_read_modify_write_reg(chip, + (unsigned int)CLKCFG_REG_OFFSET, + CLKCFG_UART_25MHZ, + CLKCFG_UART_MASK); + } + } } else if (id->driver_data == 2) { /* ML7213 IOH */ ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); if (ret) -- cgit v1.2.3