From 8e79561c41ec7746361a1e9a079c7225e010515e Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Thu, 4 Apr 2013 13:33:27 +0900 Subject: clk: exynos4: Add missing mout_sata on Exynos4210 This patch adds missing mout_sata that is a parent of div_sata clock. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Reviewed-by: Thomas Abraham Acked-by: Mike Turquette Signed-off-by: Kukjin Kim --- drivers/clk/samsung/clk-exynos4.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk') diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 7e875a462d89..e572f62ec423 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -360,6 +360,7 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { MUX(none, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4), MUX(none, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4), MUX(none, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4), + MUX(none, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1), MUX(none, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4), MUX(none, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4), MUX(none, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4), -- cgit v1.2.3