From 8230a5ab435c6a0f395ff8fb190e53b563f06179 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Wed, 12 Mar 2014 12:41:41 -0300 Subject: clk: mvebu: Fix ratio register offset on A375 SoC This commit fixes the ratio register offset which is 0x4, as per the Armada 375 SoC specification. Signed-off-by: Ezequiel Garcia Link: https://lkml.kernel.org/r/1394638901-13368-2-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper --- drivers/clk/mvebu/clk-corediv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk/mvebu') diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c index 4da60760be10..4af33ba54a1e 100644 --- a/drivers/clk/mvebu/clk-corediv.c +++ b/drivers/clk/mvebu/clk-corediv.c @@ -213,7 +213,7 @@ static const struct clk_corediv_soc_desc armada375_corediv_soc = { .set_rate = clk_corediv_set_rate, }, .ratio_reload = BIT(8), - .ratio_offset = 0x8, + .ratio_offset = 0x4, }; static void __init -- cgit v1.2.3 From 0737c15ff51857657aa5e2769d033f930334a1f6 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Thu, 13 Mar 2014 17:24:28 -0300 Subject: clk: mvebu: Support Armada 380 SoC on the core divider clock This commit adds support for the Core Divider clocks of the Armada 380 SoCs. Similarly to Armada 370 and XP, the Core Divider clocks of the 380 have gate capabilities. The only difference is the register layout. Signed-off-by: Ezequiel Garcia Link: https://lkml.kernel.org/r/1394742273-5113-2-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper --- drivers/clk/mvebu/clk-corediv.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'drivers/clk/mvebu') diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c index 4af33ba54a1e..d1e5863d3375 100644 --- a/drivers/clk/mvebu/clk-corediv.c +++ b/drivers/clk/mvebu/clk-corediv.c @@ -204,6 +204,22 @@ static const struct clk_corediv_soc_desc armada370_corediv_soc = { .ratio_offset = 0x8, }; +static const struct clk_corediv_soc_desc armada380_corediv_soc = { + .descs = mvebu_corediv_desc, + .ndescs = ARRAY_SIZE(mvebu_corediv_desc), + .ops = { + .enable = clk_corediv_enable, + .disable = clk_corediv_disable, + .is_enabled = clk_corediv_is_enabled, + .recalc_rate = clk_corediv_recalc_rate, + .round_rate = clk_corediv_round_rate, + .set_rate = clk_corediv_set_rate, + }, + .ratio_reload = BIT(8), + .enable_bit_offset = 16, + .ratio_offset = 0x4, +}; + static const struct clk_corediv_soc_desc armada375_corediv_soc = { .descs = mvebu_corediv_desc, .ndescs = ARRAY_SIZE(mvebu_corediv_desc), @@ -290,3 +306,10 @@ static void __init armada375_corediv_clk_init(struct device_node *node) } CLK_OF_DECLARE(armada375_corediv_clk, "marvell,armada-375-corediv-clock", armada375_corediv_clk_init); + +static void __init armada380_corediv_clk_init(struct device_node *node) +{ + return mvebu_corediv_clk_init(node, &armada380_corediv_soc); +} +CLK_OF_DECLARE(armada380_corediv_clk, "marvell,armada-380-corediv-clock", + armada380_corediv_clk_init); -- cgit v1.2.3