From f627217064dbef1eef53ceb01edb9c94203991e0 Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Mon, 13 May 2013 12:42:44 +0000 Subject: ACPI / LPSS: add support for Intel BayTrail Intel BayTrail has almost the same Low Power Subsystem than Lynxpoint with few differences. Peripherals are clocked with different speeds (typically lower) and the clock is not always gated. To support this we add possibility to share a common fixed rate clock and make clock gating optional. Signed-off-by: Mika Westerberg Acked-by: Mike Turquette Signed-off-by: Rafael J. Wysocki --- drivers/acpi/acpi_lpss.c | 88 ++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 81 insertions(+), 7 deletions(-) (limited to 'drivers/acpi') diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c index 652fd5ce303c..f6d760581faa 100644 --- a/drivers/acpi/acpi_lpss.c +++ b/drivers/acpi/acpi_lpss.c @@ -33,11 +33,19 @@ ACPI_MODULE_NAME("acpi_lpss"); #define LPSS_SW_LTR 0x10 #define LPSS_AUTO_LTR 0x14 +struct lpss_shared_clock { + const char *name; + unsigned long rate; + struct clk *clk; +}; + struct lpss_device_desc { bool clk_required; const char *clkdev_name; bool ltr_required; unsigned int prv_offset; + bool clk_gate; + struct lpss_shared_clock *shared_clock; }; static struct lpss_device_desc lpss_dma_desc = { @@ -56,6 +64,7 @@ static struct lpss_device_desc lpt_dev_desc = { .clk_required = true, .prv_offset = 0x800, .ltr_required = true, + .clk_gate = true, }; static struct lpss_device_desc lpt_sdio_dev_desc = { @@ -63,6 +72,45 @@ static struct lpss_device_desc lpt_sdio_dev_desc = { .ltr_required = true, }; +static struct lpss_shared_clock uart_clock = { + .name = "uart_clk", + .rate = 44236800, +}; + +static struct lpss_device_desc byt_uart_dev_desc = { + .clk_required = true, + .prv_offset = 0x800, + .clk_gate = true, + .shared_clock = &uart_clock, +}; + +static struct lpss_shared_clock spi_clock = { + .name = "spi_clk", + .rate = 50000000, +}; + +static struct lpss_device_desc byt_spi_dev_desc = { + .clk_required = true, + .prv_offset = 0x400, + .clk_gate = true, + .shared_clock = &spi_clock, +}; + +static struct lpss_device_desc byt_sdio_dev_desc = { + .clk_required = true, +}; + +static struct lpss_shared_clock i2c_clock = { + .name = "i2c_clk", + .rate = 100000000, +}; + +static struct lpss_device_desc byt_i2c_dev_desc = { + .clk_required = true, + .prv_offset = 0x800, + .shared_clock = &i2c_clock, +}; + static const struct acpi_device_id acpi_lpss_device_ids[] = { /* Generic LPSS devices */ { "INTL9C60", (unsigned long)&lpss_dma_desc }, @@ -77,6 +125,13 @@ static const struct acpi_device_id acpi_lpss_device_ids[] = { { "INT33C6", (unsigned long)&lpt_sdio_dev_desc }, { "INT33C7", }, + /* BayTrail LPSS devices */ + { "80860F0A", (unsigned long)&byt_uart_dev_desc }, + { "80860F0E", (unsigned long)&byt_spi_dev_desc }, + { "80860F14", (unsigned long)&byt_sdio_dev_desc }, + { "80860F41", (unsigned long)&byt_i2c_dev_desc }, + { "INT33B2", }, + { } }; @@ -98,7 +153,10 @@ static int register_device_clock(struct acpi_device *adev, struct lpss_private_data *pdata) { const struct lpss_device_desc *dev_desc = pdata->dev_desc; + struct lpss_shared_clock *shared_clock = dev_desc->shared_clock; + struct clk *clk = ERR_PTR(-ENODEV); struct lpss_clk_data *clk_data; + const char *parent; if (!lpss_clk_dev) lpt_register_clock_device(); @@ -117,14 +175,30 @@ static int register_device_clock(struct acpi_device *adev, || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) return -ENODATA; - pdata->clk = clk_register_gate(NULL, dev_name(&adev->dev), - clk_data->name, 0, - pdata->mmio_base + dev_desc->prv_offset, - 0, 0, NULL); - if (IS_ERR(pdata->clk)) - return PTR_ERR(pdata->clk); + parent = clk_data->name; + + if (shared_clock) { + clk = shared_clock->clk; + if (!clk) { + clk = clk_register_fixed_rate(NULL, shared_clock->name, + "lpss_clk", 0, + shared_clock->rate); + shared_clock->clk = clk; + } + parent = shared_clock->name; + } + + if (dev_desc->clk_gate) { + clk = clk_register_gate(NULL, dev_name(&adev->dev), parent, 0, + pdata->mmio_base + dev_desc->prv_offset, + 0, 0, NULL); + pdata->clk = clk; + } + + if (IS_ERR(clk)) + return PTR_ERR(clk); - clk_register_clkdev(pdata->clk, NULL, dev_name(&adev->dev)); + clk_register_clkdev(clk, NULL, dev_name(&adev->dev)); return 0; } -- cgit v1.2.3 From 06d8641504726322fca54400bbac982bd44f9a27 Mon Sep 17 00:00:00 2001 From: Heikki Krogerus Date: Mon, 17 Jun 2013 13:25:46 +0300 Subject: ACPI / LPSS: mask the UART TX completion interrupt Intel LPSS provides an extra TX byte counter and an extra TX completion interrupt for some of its bus controllers. However, there is no use for the extra UART interrupt and it has to be masked out during initialization. Otherwise, if the firmware does not mask the interrupt and the driver does not clear it, it may cause an interrupt flood freezing the board to happen. Add code masking that problematic interrupt to the ACPI LPSS driver. [rjw: Changelog] Signed-off-by: Heikki Krogerus Signed-off-by: Rafael J. Wysocki --- drivers/acpi/acpi_lpss.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) (limited to 'drivers/acpi') diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c index f6d760581faa..bd9867f592b7 100644 --- a/drivers/acpi/acpi_lpss.c +++ b/drivers/acpi/acpi_lpss.c @@ -32,6 +32,8 @@ ACPI_MODULE_NAME("acpi_lpss"); #define LPSS_GENERAL_LTR_MODE_SW BIT(2) #define LPSS_SW_LTR 0x10 #define LPSS_AUTO_LTR 0x14 +#define LPSS_TX_INT 0x20 +#define LPSS_TX_INT_MASK BIT(1) struct lpss_shared_clock { const char *name; @@ -39,6 +41,8 @@ struct lpss_shared_clock { struct clk *clk; }; +struct lpss_private_data; + struct lpss_device_desc { bool clk_required; const char *clkdev_name; @@ -46,6 +50,7 @@ struct lpss_device_desc { unsigned int prv_offset; bool clk_gate; struct lpss_shared_clock *shared_clock; + void (*setup)(struct lpss_private_data *pdata); }; static struct lpss_device_desc lpss_dma_desc = { @@ -60,6 +65,15 @@ struct lpss_private_data { const struct lpss_device_desc *dev_desc; }; +static void lpss_uart_setup(struct lpss_private_data *pdata) +{ + unsigned int tx_int_offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; + u32 reg; + + reg = readl(pdata->mmio_base + tx_int_offset); + writel(reg | LPSS_TX_INT_MASK, pdata->mmio_base + tx_int_offset); +} + static struct lpss_device_desc lpt_dev_desc = { .clk_required = true, .prv_offset = 0x800, @@ -67,6 +81,14 @@ static struct lpss_device_desc lpt_dev_desc = { .clk_gate = true, }; +static struct lpss_device_desc lpt_uart_dev_desc = { + .clk_required = true, + .prv_offset = 0x800, + .ltr_required = true, + .clk_gate = true, + .setup = lpss_uart_setup, +}; + static struct lpss_device_desc lpt_sdio_dev_desc = { .prv_offset = 0x1000, .ltr_required = true, @@ -82,6 +104,7 @@ static struct lpss_device_desc byt_uart_dev_desc = { .prv_offset = 0x800, .clk_gate = true, .shared_clock = &uart_clock, + .setup = lpss_uart_setup, }; static struct lpss_shared_clock spi_clock = { @@ -120,8 +143,8 @@ static const struct acpi_device_id acpi_lpss_device_ids[] = { { "INT33C1", (unsigned long)&lpt_dev_desc }, { "INT33C2", (unsigned long)&lpt_dev_desc }, { "INT33C3", (unsigned long)&lpt_dev_desc }, - { "INT33C4", (unsigned long)&lpt_dev_desc }, - { "INT33C5", (unsigned long)&lpt_dev_desc }, + { "INT33C4", (unsigned long)&lpt_uart_dev_desc }, + { "INT33C5", (unsigned long)&lpt_uart_dev_desc }, { "INT33C6", (unsigned long)&lpt_sdio_dev_desc }, { "INT33C7", }, @@ -247,6 +270,9 @@ static int acpi_lpss_create_device(struct acpi_device *adev, } } + if (dev_desc->setup) + dev_desc->setup(pdata); + adev->driver_data = pdata; ret = acpi_create_platform_device(adev, id); if (ret > 0) -- cgit v1.2.3 From 958c4eb2aa325099ea1f54c7354e381e3d79f3ae Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Tue, 18 Jun 2013 16:51:35 +0300 Subject: ACPI / LPSS: override SDIO private register space size from ACPI tables The SDIO device in Lynxpoint has its LTR registers reserved for a WiFi device (a child of the SDIO device) in the ACPI namespace even though those registers physically belong to the SDIO device itself. In order to be able to access the SDIO LTR registers from the ACPI LPSS driver for diagnostic purposes we need to use a size override for the SDIO private register space. Add a possibility to override the size of the private register space of an LPSS device provided by the ACPI tables in the ACPI LPSS driver and set the correct size for the SDIO device in there. [rjw: Changelog] Signed-off-by: Mika Westerberg Signed-off-by: Rafael J. Wysocki --- drivers/acpi/acpi_lpss.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers/acpi') diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c index bd9867f592b7..a4e8c0337a59 100644 --- a/drivers/acpi/acpi_lpss.c +++ b/drivers/acpi/acpi_lpss.c @@ -48,6 +48,7 @@ struct lpss_device_desc { const char *clkdev_name; bool ltr_required; unsigned int prv_offset; + size_t prv_size_override; bool clk_gate; struct lpss_shared_clock *shared_clock; void (*setup)(struct lpss_private_data *pdata); @@ -91,6 +92,7 @@ static struct lpss_device_desc lpt_uart_dev_desc = { static struct lpss_device_desc lpt_sdio_dev_desc = { .prv_offset = 0x1000, + .prv_size_override = 0x1018, .ltr_required = true, }; @@ -249,7 +251,10 @@ static int acpi_lpss_create_device(struct acpi_device *adev, list_for_each_entry(rentry, &resource_list, node) if (resource_type(&rentry->res) == IORESOURCE_MEM) { - pdata->mmio_size = resource_size(&rentry->res); + if (dev_desc->prv_size_override) + pdata->mmio_size = dev_desc->prv_size_override; + else + pdata->mmio_size = resource_size(&rentry->res); pdata->mmio_base = ioremap(rentry->res.start, pdata->mmio_size); pdata->dev_desc = dev_desc; -- cgit v1.2.3