From 298447928bb1c6bda9ad6f2ce3958d15c329816b Mon Sep 17 00:00:00 2001 From: Greentime Hu Date: Wed, 24 Jun 2020 17:03:15 +0800 Subject: riscv: Support irq_work via self IPIs Support for arch_irq_work_raise() and arch_irq_work_has_interrupt() was missing from riscv (a prerequisite for FULL_NOHZ). Signed-off-by: Greentime Hu Signed-off-by: Palmer Dabbelt --- arch/riscv/include/asm/irq_work.h | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 arch/riscv/include/asm/irq_work.h (limited to 'arch/riscv/include/asm') diff --git a/arch/riscv/include/asm/irq_work.h b/arch/riscv/include/asm/irq_work.h new file mode 100644 index 000000000000..d6c277992f76 --- /dev/null +++ b/arch/riscv/include/asm/irq_work.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RISCV_IRQ_WORK_H +#define _ASM_RISCV_IRQ_WORK_H + +static inline bool arch_irq_work_has_interrupt(void) +{ + return true; +} +extern void arch_irq_work_raise(void); +#endif /* _ASM_RISCV_IRQ_WORK_H */ -- cgit v1.2.3 From f2c9699f65557a31fed4ddb9e5b4d9489b1bf32f Mon Sep 17 00:00:00 2001 From: Guo Ren Date: Fri, 10 Jul 2020 16:19:57 +0000 Subject: riscv: Add STACKPROTECTOR supported The -fstack-protector & -fstack-protector-strong features are from gcc. The patch only add basic kernel support to stack-protector feature and some arch could have its own solution such as ARM64_PTR_AUTH. After enabling STACKPROTECTOR and STACKPROTECTOR_STRONG, the .text size is expanded from 0x7de066 to 0x81fb32 (only 5%) to add canary checking code. Signed-off-by: Guo Ren Reviewed-by: Kees Cook Signed-off-by: Palmer Dabbelt --- arch/riscv/include/asm/stackprotector.h | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 arch/riscv/include/asm/stackprotector.h (limited to 'arch/riscv/include/asm') diff --git a/arch/riscv/include/asm/stackprotector.h b/arch/riscv/include/asm/stackprotector.h new file mode 100644 index 000000000000..d95f7b2a7f37 --- /dev/null +++ b/arch/riscv/include/asm/stackprotector.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _ASM_RISCV_STACKPROTECTOR_H +#define _ASM_RISCV_STACKPROTECTOR_H + +#include +#include +#include + +extern unsigned long __stack_chk_guard; + +/* + * Initialize the stackprotector canary value. + * + * NOTE: this must only be called from functions that never return, + * and it must always be inlined. + */ +static __always_inline void boot_init_stack_canary(void) +{ + unsigned long canary; + unsigned long tsc; + + /* Try to get a semi random initial value. */ + get_random_bytes(&canary, sizeof(canary)); + tsc = get_cycles(); + canary += tsc + (tsc << BITS_PER_LONG/2); + canary ^= LINUX_VERSION_CODE; + canary &= CANARY_MASK; + + current->stack_canary = canary; + __stack_chk_guard = current->stack_canary; +} +#endif /* _ASM_RISCV_STACKPROTECTOR_H */ -- cgit v1.2.3 From ebc00dde8a975a543f5e1a7cdac93fef89fefe58 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Tue, 14 Jul 2020 09:40:44 +0200 Subject: riscv: Add jump-label implementation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add jump-label implementation based on the ARM64 version and add CONFIG_JUMP_LABEL=y to the defconfigs. Signed-off-by: Emil Renner Berthing Reviewed-by: Björn Töpel Tested-by: Björn Töpel Signed-off-by: Palmer Dabbelt --- arch/riscv/include/asm/jump_label.h | 60 +++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 arch/riscv/include/asm/jump_label.h (limited to 'arch/riscv/include/asm') diff --git a/arch/riscv/include/asm/jump_label.h b/arch/riscv/include/asm/jump_label.h new file mode 100644 index 000000000000..38af2ec7b9bf --- /dev/null +++ b/arch/riscv/include/asm/jump_label.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2020 Emil Renner Berthing + * + * Based on arch/arm64/include/asm/jump_label.h + */ +#ifndef __ASM_JUMP_LABEL_H +#define __ASM_JUMP_LABEL_H + +#ifndef __ASSEMBLY__ + +#include +#include + +#define JUMP_LABEL_NOP_SIZE 4 + +static __always_inline bool arch_static_branch(struct static_key *key, + bool branch) +{ + asm_volatile_goto( + " .option push \n\t" + " .option norelax \n\t" + " .option norvc \n\t" + "1: nop \n\t" + " .option pop \n\t" + " .pushsection __jump_table, \"aw\" \n\t" + " .align " RISCV_LGPTR " \n\t" + " .long 1b - ., %l[label] - . \n\t" + " " RISCV_PTR " %0 - . \n\t" + " .popsection \n\t" + : : "i"(&((char *)key)[branch]) : : label); + + return false; +label: + return true; +} + +static __always_inline bool arch_static_branch_jump(struct static_key *key, + bool branch) +{ + asm_volatile_goto( + " .option push \n\t" + " .option norelax \n\t" + " .option norvc \n\t" + "1: jal zero, %l[label] \n\t" + " .option pop \n\t" + " .pushsection __jump_table, \"aw\" \n\t" + " .align " RISCV_LGPTR " \n\t" + " .long 1b - ., %l[label] - . \n\t" + " " RISCV_PTR " %0 - . \n\t" + " .popsection \n\t" + : : "i"(&((char *)key)[branch]) : : label); + + return false; +label: + return true; +} + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_JUMP_LABEL_H */ -- cgit v1.2.3 From 89b03cc1dff0654fc01958f3bdd5005c9a510e2e Mon Sep 17 00:00:00 2001 From: Pekka Enberg Date: Wed, 15 Jul 2020 08:33:40 +0300 Subject: riscv: Use generic pgprot_* macros from The header now defines generic pgprot_ macros also for the no-MMU configuration, so let's use them. Signed-off-by: Pekka Enberg Signed-off-by: Palmer Dabbelt --- arch/riscv/include/asm/mmio.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch/riscv/include/asm') diff --git a/arch/riscv/include/asm/mmio.h b/arch/riscv/include/asm/mmio.h index 56053c9838b2..aff6c33ab0c0 100644 --- a/arch/riscv/include/asm/mmio.h +++ b/arch/riscv/include/asm/mmio.h @@ -14,12 +14,6 @@ #include #include -#ifndef CONFIG_MMU -#define pgprot_noncached(x) (x) -#define pgprot_writecombine(x) (x) -#define pgprot_device(x) (x) -#endif /* CONFIG_MMU */ - /* Generic IO read/write. These perform native-endian accesses. */ #define __raw_writeb __raw_writeb static inline void __raw_writeb(u8 val, volatile void __iomem *addr) -- cgit v1.2.3 From 635093e306a3e4543937b079dc797c2ee0bafa09 Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Wed, 29 Jul 2020 17:25:35 -0700 Subject: RISC-V: Fix build warning for smpboot.c The following warnings are reported by kbuild with W=1. >> arch/riscv/kernel/smpboot.c:109:5: warning: no previous prototype for 'start_secondary_cpu' [-Wmissing-prototypes] 109 | int start_secondary_cpu(int cpu, struct task_struct *tidle) | ^~~~~~~~~~~~~~~~~~~ arch/riscv/kernel/smpboot.c:146:34: warning: no previous prototype for 'smp_callin' [-Wmissing-prototypes] 146 | asmlinkage __visible void __init smp_callin(void) | ^~~~~~~~~~ Fix the warnings by marking the local functions static and adding the prototype for the global function. Signed-off-by: Atish Patra Signed-off-by: Palmer Dabbelt --- arch/riscv/include/asm/smp.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/riscv/include/asm') diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 40bb1c15a731..6dfd2a1446d5 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -40,6 +40,9 @@ void arch_send_call_function_single_ipi(int cpu); int riscv_hartid_to_cpuid(int hartid); void riscv_cpuid_to_hartid_mask(const struct cpumask *in, struct cpumask *out); +/* Secondary hart entry */ +asmlinkage void smp_callin(void); + /* * Obtains the hart ID of the currently executing task. This relies on * THREAD_INFO_IN_TASK, but we define that unconditionally. -- cgit v1.2.3