From 26ab96dfa9f98d74ef38efbe830d356547a292c1 Mon Sep 17 00:00:00 2001 From: Leonid Yegoshin Date: Wed, 27 Nov 2013 10:07:53 +0000 Subject: MIPS: Add support for interAptiv cores The interAptiv is a power-efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The interAptiv combines a multi-threading pipeline with a coherence manager to deliver improved computational throughput and power efficiency. The interAptiv can contain one to four MIPS32R3 interAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit. Signed-off-by: Leonid Yegoshin Signed-off-by: Markos Chandras Signed-off-by: John Crispin Patchwork: http://patchwork.linux-mips.org/patch/6163/ --- arch/mips/oprofile/op_model_mipsxx.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/mips/oprofile/op_model_mipsxx.c') diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 3e28aaa39bc9..4d94d75ec6f9 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -376,6 +376,10 @@ static int __init mipsxx_init(void) op_model_mipsxx_ops.cpu_type = "mips/74K"; break; + case CPU_INTERAPTIV: + op_model_mipsxx_ops.cpu_type = "mips/interAptiv"; + break; + case CPU_PROAPTIV: op_model_mipsxx_ops.cpu_type = "mips/proAptiv"; break; -- cgit v1.2.3