From 67613f02788d73541c7c9b1c851061b8c223057b Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Thu, 13 Aug 2015 09:56:29 +0200 Subject: MIPS: math-emu: Add support for the MIPS R6 SELEQZ FPU instruction MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MIPS R6 introduced the following instruction: SELEQZ.fmt: FPR[fd]  FPR[ft].bit0 ? 0 : FPR[fs] Add support for emulating the single and double precision formats of the said instruction. Signed-off-by: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10954/ Signed-off-by: Ralf Baechle --- arch/mips/math-emu/cp1emu.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch/mips/math-emu') diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index ef41fc895e75..02ba536f1594 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -1743,6 +1743,17 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, SPFROMREG(rv.s, MIPSInst_FS(ir)); break; + case fseleqz_op: + if (!cpu_has_mips_r6) + return SIGILL; + + SPFROMREG(rv.s, MIPSInst_FT(ir)); + if (rv.w & 0x1) + rv.w = 0; + else + SPFROMREG(rv.s, MIPSInst_FS(ir)); + break; + case fabs_op: handler.u = ieee754sp_abs; goto scopuop; @@ -1940,6 +1951,18 @@ copcsr: return 0; DPFROMREG(rv.d, MIPSInst_FS(ir)); break; + + case fseleqz_op: + if (!cpu_has_mips_r6) + return SIGILL; + + DPFROMREG(rv.d, MIPSInst_FT(ir)); + if (rv.l & 0x1) + rv.l = 0; + else + DPFROMREG(rv.d, MIPSInst_FS(ir)); + break; + case fabs_op: handler.u = ieee754dp_abs; goto dcopuop; -- cgit v1.2.3