From 5e5b6527128cea50f12a7064bf61b130b3a2739a Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Mon, 24 Aug 2020 18:32:44 +0200 Subject: MIPS: Convert R4600_V1_HIT_CACHEOP into a config option Use a new config option to enable R4600 V1 cacheop hit workaround and remove define from the different war.h files. Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/mach-rm/war.h | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/mips/include/asm/mach-rm') diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h index fe3c17f38650..192ec3358ad0 100644 --- a/arch/mips/include/asm/mach-rm/war.h +++ b/arch/mips/include/asm/mach-rm/war.h @@ -12,7 +12,6 @@ * The RM200C seems to have been shipped only with V2.0 R4600s */ -#define R4600_V1_HIT_CACHEOP_WAR 0 #define R4600_V2_HIT_CACHEOP_WAR 1 #define BCM1250_M3_WAR 0 #define SIBYTE_1956_WAR 0 -- cgit v1.2.3