From 7034228792cc561e79ff8600f02884bd4c80e287 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 22 Jan 2013 12:59:30 +0100 Subject: MIPS: Whitespace cleanup. Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle --- arch/mips/alchemy/common/dbdma.c | 14 +-- arch/mips/alchemy/common/gpiolib.c | 14 +-- arch/mips/alchemy/common/irq.c | 178 ++++++++++++++++++------------------ arch/mips/alchemy/common/platform.c | 4 +- arch/mips/alchemy/common/setup.c | 2 +- arch/mips/alchemy/common/sleeper.S | 20 ++-- arch/mips/alchemy/common/time.c | 2 +- arch/mips/alchemy/common/usb.c | 2 +- 8 files changed, 118 insertions(+), 118 deletions(-) (limited to 'arch/mips/alchemy/common') diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index cf02d7dc2df0..19d5642c16d9 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -252,7 +252,7 @@ EXPORT_SYMBOL(au1xxx_ddma_del_device); u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, void (*callback)(int, void *), void *callparam) { - unsigned long flags; + unsigned long flags; u32 used, chan; u32 dcp; int i; @@ -512,7 +512,7 @@ u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries) break; } - /* If source input is FIFO, set static address. */ + /* If source input is FIFO, set static address. */ if (stp->dev_flags & DEV_FLAGS_IN) { if (stp->dev_flags & DEV_FLAGS_BURSTABLE) src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST); @@ -635,7 +635,7 @@ u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags) dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); ctp->chan_ptr->ddma_dbell = 0; - /* Get next descriptor pointer. */ + /* Get next descriptor pointer. */ ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); /* Return something non-zero. */ @@ -697,7 +697,7 @@ u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags) dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); ctp->chan_ptr->ddma_dbell = 0; - /* Get next descriptor pointer. */ + /* Get next descriptor pointer. */ ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); /* Return something non-zero. */ @@ -742,7 +742,7 @@ u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes) *nbytes = dp->dscr_cmd1; rv = dp->dscr_stat; - /* Get next descriptor pointer. */ + /* Get next descriptor pointer. */ ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); /* Return something non-zero. */ @@ -891,7 +891,7 @@ void au1xxx_dbdma_dump(u32 chanid) chan_tab_t *ctp; au1x_ddma_desc_t *dp; dbdev_tab_t *stp, *dtp; - au1x_dma_chan_t *cp; + au1x_dma_chan_t *cp; u32 i = 0; ctp = *((chan_tab_t **)chanid); @@ -969,7 +969,7 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr) dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V; ctp->chan_ptr->ddma_dbell = 0; - /* Get next descriptor pointer. */ + /* Get next descriptor pointer. */ ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); /* Return something non-zero. */ diff --git a/arch/mips/alchemy/common/gpiolib.c b/arch/mips/alchemy/common/gpiolib.c index f1b50f0c01db..f9bc4f520440 100644 --- a/arch/mips/alchemy/common/gpiolib.c +++ b/arch/mips/alchemy/common/gpiolib.c @@ -106,14 +106,14 @@ struct gpio_chip alchemy_gpio_chip[] = { .ngpio = ALCHEMY_GPIO1_NUM, }, [1] = { - .label = "alchemy-gpio2", - .direction_input = gpio2_direction_input, - .direction_output = gpio2_direction_output, - .get = gpio2_get, - .set = gpio2_set, + .label = "alchemy-gpio2", + .direction_input = gpio2_direction_input, + .direction_output = gpio2_direction_output, + .get = gpio2_get, + .set = gpio2_set, .to_irq = gpio2_to_irq, - .base = ALCHEMY_GPIO2_BASE, - .ngpio = ALCHEMY_GPIO2_NUM, + .base = ALCHEMY_GPIO2_BASE, + .ngpio = ALCHEMY_GPIO2_NUM, }, }; diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index 94fbcd19eb9c..63a71817a00c 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c @@ -84,20 +84,20 @@ static int au1300_gpic_settype(struct irq_data *d, unsigned int type); * needs the highest priority. */ struct alchemy_irqmap au1000_irqmap[] __initdata = { - { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, @@ -106,33 +106,33 @@ struct alchemy_irqmap au1000_irqmap[] __initdata = { { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 }, - { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 }, + { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 }, { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, - { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 }, { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, - { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { -1, }, }; struct alchemy_irqmap au1500_irqmap[] __initdata = { - { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1500_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 1, 0 }, - { AU1500_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 1, 0 }, - { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1500_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 1, 0 }, - { AU1500_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 1, 0 }, - { AU1500_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1500_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1500_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1500_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1500_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1500_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1500_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1500_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1500_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1500_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1500_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, { AU1500_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { AU1500_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { AU1500_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, @@ -141,31 +141,31 @@ struct alchemy_irqmap au1500_irqmap[] __initdata = { { AU1500_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { AU1500_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { AU1500_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 }, - { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 }, + { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 }, { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, - { AU1500_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1500_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 }, { AU1500_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, - { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, { AU1500_AC97C_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { -1, }, }; struct alchemy_irqmap au1100_irqmap[] __initdata = { - { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1100_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1100_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1100_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1100_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1100_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1100_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1100_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1100_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1100_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1100_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, { AU1100_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { AU1100_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { AU1100_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, @@ -174,33 +174,33 @@ struct alchemy_irqmap au1100_irqmap[] __initdata = { { AU1100_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { AU1100_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { AU1100_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 }, - { AU1100_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1100_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 }, + { AU1100_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 }, { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, - { AU1100_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1100_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 }, { AU1100_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, - { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, { AU1100_AC97C_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { -1, }, }; struct alchemy_irqmap au1550_irqmap[] __initdata = { - { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 1, 0 }, - { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 1, 0 }, - { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 1, 0 }, - { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 1, 0 }, - { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 }, - { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, { AU1550_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { AU1550_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { AU1550_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, @@ -210,26 +210,26 @@ struct alchemy_irqmap au1550_irqmap[] __initdata = { { AU1550_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { AU1550_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 }, { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, - { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 }, + { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 }, { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, - { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 }, - { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, { -1, }, }; struct alchemy_irqmap au1200_irqmap[] __initdata = { - { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, - { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, { AU1200_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { AU1200_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { AU1200_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, @@ -239,9 +239,9 @@ struct alchemy_irqmap au1200_irqmap[] __initdata = { { AU1200_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { AU1200_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 }, { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, - { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, - { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, { -1, }, }; diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 7af941d8e717..9837a134a6d6 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -53,7 +53,7 @@ static void alchemy_8250_pm(struct uart_port *port, unsigned int state, .irq = _irq, \ .regshift = 2, \ .iotype = UPIO_AU, \ - .flags = UPF_SKIP_TEST | UPF_IOREMAP | \ + .flags = UPF_SKIP_TEST | UPF_IOREMAP | \ UPF_FIXED_TYPE, \ .type = PORT_16550A, \ .pm = alchemy_8250_pm, \ @@ -137,7 +137,7 @@ static void alchemy_ehci_power_off(struct platform_device *pdev) } static struct usb_ehci_pdata alchemy_ehci_pdata = { - .no_io_watchdog = 1, + .no_io_watchdog = 1, .power_on = alchemy_ehci_power_on, .power_off = alchemy_ehci_power_off, .power_suspend = alchemy_ehci_power_off, diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c index 37ffd997c616..62b4e7bbeab9 100644 --- a/arch/mips/alchemy/common/setup.c +++ b/arch/mips/alchemy/common/setup.c @@ -59,7 +59,7 @@ void __init plat_mem_setup(void) /* Clear to obtain best system bus performance */ clear_c0_config(1 << 19); /* Clear Config[OD] */ - board_setup(); /* board specific setup */ + board_setup(); /* board specific setup */ /* IO/MEM resources. */ set_io_port_base(0); diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S index c7bcc7e5c822..706d933e0085 100644 --- a/arch/mips/alchemy/common/sleeper.S +++ b/arch/mips/alchemy/common/sleeper.S @@ -102,12 +102,12 @@ LEAF(alchemy_sleep_au1000) cache 0x14, 96(t0) .set mips0 -1: lui a0, 0xb400 /* mem_xxx */ - sw zero, 0x001c(a0) /* Precharge */ +1: lui a0, 0xb400 /* mem_xxx */ + sw zero, 0x001c(a0) /* Precharge */ sync sw zero, 0x0020(a0) /* Auto Refresh */ sync - sw zero, 0x0030(a0) /* Sleep */ + sw zero, 0x0030(a0) /* Sleep */ sync DO_SLEEP @@ -128,15 +128,15 @@ LEAF(alchemy_sleep_au1550) cache 0x14, 96(t0) .set mips0 -1: lui a0, 0xb400 /* mem_xxx */ - sw zero, 0x08c0(a0) /* Precharge */ +1: lui a0, 0xb400 /* mem_xxx */ + sw zero, 0x08c0(a0) /* Precharge */ sync sw zero, 0x08d0(a0) /* Self Refresh */ sync /* wait for sdram to enter self-refresh mode */ - lui t0, 0x0100 -2: lw t1, 0x0850(a0) /* mem_sdstat */ + lui t0, 0x0100 +2: lw t1, 0x0850(a0) /* mem_sdstat */ and t2, t1, t0 beq t2, zero, 2b nop @@ -144,9 +144,9 @@ LEAF(alchemy_sleep_au1550) /* disable SDRAM clocks */ lui t0, 0xcfff ori t0, t0, 0xffff - lw t1, 0x0840(a0) /* mem_sdconfiga */ - and t1, t0, t1 /* clear CE[1:0] */ - sw t1, 0x0840(a0) /* mem_sdconfiga */ + lw t1, 0x0840(a0) /* mem_sdconfiga */ + and t1, t0, t1 /* clear CE[1:0] */ + sw t1, 0x0840(a0) /* mem_sdconfiga */ sync DO_SLEEP diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index b67930d19325..38afb11ba2c4 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -85,7 +85,7 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = { .name = "rtcmatch2", .features = CLOCK_EVT_FEAT_ONESHOT, .rating = 1500, - .set_next_event = au1x_rtcmatch2_set_next_event, + .set_next_event = au1x_rtcmatch2_set_next_event, .set_mode = au1x_rtcmatch2_set_mode, .cpumask = cpu_all_mask, }; diff --git a/arch/mips/alchemy/common/usb.c b/arch/mips/alchemy/common/usb.c index 936af8359fb2..fcc695626117 100644 --- a/arch/mips/alchemy/common/usb.c +++ b/arch/mips/alchemy/common/usb.c @@ -122,7 +122,7 @@ static inline void __au1300_ohci_control(void __iomem *base, int enable, int id) unsigned long r; if (enable) { - __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ + __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ wmb(); r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */ -- cgit v1.2.3