From 62cedc4fde2d15b08e4502aa3fb2d9d798f3ccd8 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 31 Jan 2012 18:18:45 +0100 Subject: MIPS: introduce CPU_R4K_CACHE_TLB R4K-style CPUs having common code to support their caches and tlb have this boolean defined by default. Allows us to remove some lines in arch/mips/mm/Makefile. Signed-off-by: Florian Fainelli Patchwork: http://patchwork.linux-mips.org/patch/3328/ Signed-off-by: John Crispin --- arch/mips/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/mips/Kconfig') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 0920936fc67f..1dcbbd11b1db 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1888,6 +1888,10 @@ config CPU_R4K_FPU bool default y if !(CPU_R3000 || CPU_R6000 || CPU_TX39XX || CPU_CAVIUM_OCTEON) +config CPU_R4K_CACHE_TLB + bool + default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON) + choice prompt "MIPS MT options" -- cgit v1.2.3