From 95b840afe420bb4152fde11473e7ce370b058c1b Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Wed, 5 Apr 2017 16:06:11 +0200 Subject: ARM: dts: rockchip: Setup usb vbus-supply on rk3288-rock2 Now that the rockchip usb phy has a vbus-supply property use that to control the vbus regulator on rock2. Signed-off-by: Sjoerd Simons Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-rock2-square.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts index a23a94811be8..8ed25e9f60bc 100644 --- a/arch/arm/boot/dts/rk3288-rock2-square.dts +++ b/arch/arm/boot/dts/rk3288-rock2-square.dts @@ -125,10 +125,6 @@ gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&host_vbus_drv>; - /* Always on as the rockchip usb phy doesn't have a vbus-supply - * property - */ - regulator-always-on; regulator-name = "vcc_host"; }; @@ -279,6 +275,10 @@ status = "okay"; }; +&usbphy1 { + vbus-supply = <&vcc_usb_host>; +}; + &usb_host0_ehci { status = "okay"; }; -- cgit v1.2.3 From a3b882f9867f884a995c5df12d447822426027e5 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Mon, 14 Nov 2016 20:12:35 +0800 Subject: ARM: debug: add low level debug uart for rv1108 RK1108 UARTs are Synopsis DesignWare 8250 compatible. Only with different register addresses. Signed-off-by: Andy Yan Tested-by: Jacob Chen [rk1108->rv1108 rename] Signed-off-by: Heiko Stuebner --- arch/arm/Kconfig.debug | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 426d2716f55d..b3677d1d07fc 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -776,6 +776,30 @@ choice their output to the standard serial port on the RealView PB1176 platform. + config DEBUG_RV1108_UART0 + bool "Kernel low-level debugging messages via Rockchip RV1108 UART0" + depends on ARCH_ROCKCHIP + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on Rockchip RV1108 based platforms. + + config DEBUG_RV1108_UART1 + bool "Kernel low-level debugging messages via Rockchip RV1108 UART1" + depends on ARCH_ROCKCHIP + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on Rockchip RV1108 based platforms. + + config DEBUG_RV1108_UART2 + bool "Kernel low-level debugging messages via Rockchip RV1108 UART2" + depends on ARCH_ROCKCHIP + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on Rockchip RV1108 based platforms. + config DEBUG_RK29_UART0 bool "Kernel low-level debugging messages via Rockchip RK29 UART0" depends on ARCH_ROCKCHIP @@ -1465,6 +1489,9 @@ config DEBUG_UART_PHYS default 0x10126000 if DEBUG_RK3X_UART1 default 0x101f1000 if DEBUG_VERSATILE default 0x101fb000 if DEBUG_NOMADIK_UART + default 0x10210000 if DEBUG_RV1108_UART2 + default 0x10220000 if DEBUG_RV1108_UART1 + default 0x10230000 if DEBUG_RV1108_UART0 default 0x11002000 if DEBUG_MT8127_UART0 default 0x11006000 if DEBUG_MT6589_UART0 default 0x11009000 if DEBUG_MT8135_UART3 @@ -1563,6 +1590,9 @@ config DEBUG_UART_PHYS config DEBUG_UART_VIRT hex "Virtual base address of debug UART" + default 0xc881f000 if DEBUG_RV1108_UART2 + default 0xc8821000 if DEBUG_RV1108_UART1 + default 0xc8912000 if DEBUG_RV1108_UART0 default 0xe0000a00 if DEBUG_NETX_UART default 0xe0010fe0 if ARCH_RPC default 0xf0000be0 if ARCH_EBSA110 -- cgit v1.2.3 From 51f6bfc78beaaa4c42bd2ab394e2550285caab0c Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Mon, 14 Nov 2016 20:15:47 +0800 Subject: ARM: rockchip: enable support for RV1108 SoC Add a rockchip,rv1108 compatible. Signed-off-by: Andy Yan [rk1108->rv1108 rename] Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/rockchip.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c index ef0500a4c8ad..927cf563ea47 100644 --- a/arch/arm/mach-rockchip/rockchip.c +++ b/arch/arm/mach-rockchip/rockchip.c @@ -70,6 +70,7 @@ static const char * const rockchip_board_dt_compat[] = { "rockchip,rk3188", "rockchip,rk3228", "rockchip,rk3288", + "rockchip,rv1108", NULL, }; -- cgit v1.2.3 From 802139d00970f32396ea4e25ab7a371967691da8 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 18 Apr 2017 12:22:03 +0800 Subject: ARM: sun8i: a83t: Drop skeleton.dtsi skeleton.dtsi is deprecated. Remove it from sun8i-a83t.dtsi and add the needed device nodes directly. Also drop an extra, non-style-conforming line in the copyright license header. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 0ec143773ee9..913aacafe8d5 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -40,15 +40,20 @@ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. - */ -#include "skeleton.dtsi" - #include / { interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + }; + + chosen { + }; cpus { #address-cells = <1>; @@ -146,6 +151,11 @@ }; }; + memory { + reg = <0x40000000 0x80000000>; + device_type = "memory"; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; -- cgit v1.2.3 From e53bfb022fd21637270c43e83a853b823fc6b1d1 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 18 Apr 2017 12:22:05 +0800 Subject: ARM: sun8i: a83t: Rename pinmux setting names The pinmux setting nodes all have an address element in their node names, however the pinctrl node does not have #address-cells. Rename the existing pinmux setting nodes and labels in sun8i-a83t.dtsi, dropping identifiers for functions that only have one possible setting, and using the pingroup name if the function is identically available on different pingroups. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 2 +- arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 2 +- arch/arm/boot/dts/sun8i-a83t.dtsi | 10 +++++----- 3 files changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts index 342e1d33fa1c..aecdeeb368ed 100644 --- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts @@ -59,6 +59,6 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_b>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts index 88b1e0970b8d..d2614f101ecc 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -60,6 +60,6 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_b>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 913aacafe8d5..5f5c10c04dd3 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -174,7 +174,7 @@ #interrupt-cells = <3>; #gpio-cells = <3>; - mmc0_pins_a: mmc0@0 { + mmc0_pins: mmc0_pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; @@ -182,13 +182,13 @@ bias-pull-up; }; - uart0_pins_a: uart0@0 { - pins = "PF2", "PF4"; + uart0_pb_pins: uart0_pb_pins { + pins = "PB9", "PB10"; function = "uart0"; }; - uart0_pins_b: uart0@1 { - pins = "PB9", "PB10"; + uart0_pf_pins: uart0_pf_pins { + pins = "PF2", "PF4"; function = "uart0"; }; }; -- cgit v1.2.3 From 8a92770b648121570eafc7fdec5bb50b8e4a7347 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 19 Apr 2017 13:09:16 +0800 Subject: ARM: sunxi: common-regulators: Drop pinmux settings for GPIO pins As part of our effort to move pinctrl/GPIO interlocking into the driver where it belongs, this patch drops the definition and usage of the pinmux settings for the common regulators defined in sunxi-common-regulators.dtsi. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts | 4 --- arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts | 8 ------ arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts | 4 --- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 4 --- arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts | 4 --- .../boot/dts/sun5i-a13-empire-electronix-d709.dts | 4 --- arch/arm/boot/dts/sun5i-a13-hsg-h702.dts | 5 ---- arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 4 --- arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 5 ---- arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 8 ------ arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 4 --- arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 4 --- arch/arm/boot/dts/sunxi-common-regulators.dtsi | 30 ---------------------- 13 files changed, 88 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts index 85dcf81ab64e..bc4351bb851f 100644 --- a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts +++ b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts @@ -120,10 +120,6 @@ status = "okay"; }; -&usb2_vbus_pin_a { - pins = "PH6"; -}; - &usb_otg { dr_mode = "otg"; status = "okay"; diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts index c6f742a7e69f..d2dee8d434bf 100644 --- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts +++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts @@ -136,14 +136,6 @@ status = "okay"; }; -&usb0_vbus_pin_a { - pins = "PG13"; -}; - -&usb1_vbus_pin_a { - pins = "PB10"; -}; - &usb_otg { dr_mode = "host"; status = "okay"; diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts index a27c3fa58736..16f839df4227 100644 --- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts +++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts @@ -168,10 +168,6 @@ status = "okay"; }; -&usb1_vbus_pin_a { - pins = "PG13"; -}; - &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index 894f874a5beb..eff36fe1aaa3 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -271,10 +271,6 @@ status = "okay"; }; -&usb0_vbus_pin_a { - pins = "PG11"; -}; - &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; diff --git a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts index ea3e5655a61b..5482be174e12 100644 --- a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts +++ b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts @@ -216,10 +216,6 @@ status = "okay"; }; -&usb1_vbus_pin_a { - pins = "PG12"; -}; - &usbphy { usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts index 34411d27aadf..3dbb0d7c2f8c 100644 --- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts +++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts @@ -207,10 +207,6 @@ status = "okay"; }; -&usb0_vbus_pin_a { - pins = "PG12"; -}; - &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts index 2489c16f7efa..584fa579ded2 100644 --- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts +++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts @@ -186,7 +186,6 @@ }; ®_usb0_vbus { - pinctrl-0 = <&usb0_vbus_pin_a>; gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ status = "okay"; }; @@ -202,10 +201,6 @@ status = "okay"; }; -&usb0_vbus_pin_a { - pins = "PG12"; -}; - &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 95f591bb8ced..38072c7e10e2 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -269,10 +269,6 @@ status = "okay"; }; -&usb0_vbus_pin_a { - pins = "PG12"; -}; - &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index d4f74f476f25..b4c87a23e3f8 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -344,11 +344,6 @@ status = "okay"; }; -&usb1_vbus_pin_a { - /* different pin from sunxi-common-regulators */ - pins = "PH24"; -}; - &usbphy { usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ usb0_vbus_det-gpio = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */ diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts index 96bb0bc198ba..004b6ddac813 100644 --- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts +++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts @@ -85,10 +85,6 @@ }; }; -&ahci_pwr_pin_a { - pins = "PB3"; -}; - &ahci { target-supply = <®_ahci_5v>; status = "okay"; @@ -319,10 +315,6 @@ status = "okay"; }; -&usb2_vbus_pin_a { - pins = "PH12"; -}; - &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts index 7c96b53b76bf..98177b5891cb 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts @@ -106,10 +106,6 @@ status = "okay"; }; -&ahci_pwr_pin_a { - pins = "PH2"; -}; - &codec { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index 5b6d14555b7c..d7d5330c566f 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -195,10 +195,6 @@ status = "disabled"; }; -&usb1_vbus_pin_a { - pins = "PG13"; -}; - &usbphy { usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi index ce5c53e4452f..d8e5826fb3de 100644 --- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi +++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi @@ -44,33 +44,9 @@ #include -&pio { - ahci_pwr_pin_a: ahci_pwr_pin@0 { - pins = "PB8"; - function = "gpio_out"; - }; - - usb0_vbus_pin_a: usb0_vbus_pin@0 { - pins = "PB9"; - function = "gpio_out"; - }; - - usb1_vbus_pin_a: usb1_vbus_pin@0 { - pins = "PH6"; - function = "gpio_out"; - }; - - usb2_vbus_pin_a: usb2_vbus_pin@0 { - pins = "PH3"; - function = "gpio_out"; - }; -}; - / { reg_ahci_5v: ahci-5v { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&ahci_pwr_pin_a>; regulator-name = "ahci-5v"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -82,8 +58,6 @@ reg_usb0_vbus: usb0-vbus { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_vbus_pin_a>; regulator-name = "usb0-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -94,8 +68,6 @@ reg_usb1_vbus: usb1-vbus { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_vbus_pin_a>; regulator-name = "usb1-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -107,8 +79,6 @@ reg_usb2_vbus: usb2-vbus { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_vbus_pin_a>; regulator-name = "usb2-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; -- cgit v1.2.3 From cf439662affda9475d4b71b910aad856fc3966d3 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 19 Apr 2017 13:09:17 +0800 Subject: ARM: sunxi: Drop mmc0_cd_pin_reference_design pinmux setting As part of our effort to move pinctrl/GPIO interlocking into the driver where it belongs, this patch drops the definition and usage of the mmc0_cd_pin_reference_design pinmux setting for the default mmc0 card detect GPIO pin. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-a1000.dts | 2 +- arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts | 2 +- arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts | 2 +- arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 2 +- arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts | 2 +- arch/arm/boot/dts/sun4i-a10-gemei-g9.dts | 2 +- arch/arm/boot/dts/sun4i-a10-hackberry.dts | 2 +- arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts | 2 +- arch/arm/boot/dts/sun4i-a10-inet1.dts | 2 +- arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | 2 +- arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts | 2 +- arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts | 2 +- arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts | 2 +- arch/arm/boot/dts/sun4i-a10-marsboard.dts | 2 +- arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 2 +- arch/arm/boot/dts/sun4i-a10-mk802.dts | 2 +- arch/arm/boot/dts/sun4i-a10-mk802ii.dts | 2 +- arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 2 +- arch/arm/boot/dts/sun4i-a10-pcduino.dts | 2 +- arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts | 2 +- arch/arm/boot/dts/sun4i-a10.dtsi | 6 ------ arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 2 +- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 2 +- arch/arm/boot/dts/sun7i-a20-hummingbird.dts | 2 +- arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 2 +- arch/arm/boot/dts/sun7i-a20-icnova-swac.dts | 2 +- arch/arm/boot/dts/sun7i-a20-itead-ibox.dts | 2 +- arch/arm/boot/dts/sun7i-a20-m3.dts | 2 +- arch/arm/boot/dts/sun7i-a20-mk808c.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 2 +- arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 2 +- arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 2 +- arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 2 +- arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts | 2 +- arch/arm/boot/dts/sun7i-a20.dtsi | 6 ------ 38 files changed, 36 insertions(+), 48 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index f2a01fe2bebc..f80d37ddc4c6 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -171,7 +171,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts index 942d739a4384..6b02de592a02 100644 --- a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts +++ b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts @@ -109,7 +109,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts index 17f8c5ec011c..a7d61994b8fd 100644 --- a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts +++ b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts @@ -128,7 +128,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index d844938e2aa7..a698a994e5ff 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -142,7 +142,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts index aad3bec1cb39..e0777ae808c7 100644 --- a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts +++ b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts @@ -163,7 +163,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts index 9616cdecce93..d8bfd7b74916 100644 --- a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts +++ b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts @@ -146,7 +146,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH01 */ diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index a1a7282199d5..856cfc9128e6 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts @@ -107,7 +107,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts index bc4351bb851f..6506595268b2 100644 --- a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts +++ b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts @@ -79,7 +79,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-inet1.dts b/arch/arm/boot/dts/sun4i-a10-inet1.dts index b8923b92cb36..d51d8c302daf 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet1.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet1.dts @@ -161,7 +161,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts index a1a2bbb3f9d3..a8e479fe43ca 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts @@ -147,7 +147,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts index 4a27eb9102cd..2acb89a87d41 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts @@ -305,7 +305,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts b/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts index 4e798f014c99..92e3e030ced3 100644 --- a/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts +++ b/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts @@ -100,7 +100,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts index 308dc1513041..92b2d4af3d21 100644 --- a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts +++ b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts @@ -140,7 +140,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-marsboard.dts b/arch/arm/boot/dts/sun4i-a10-marsboard.dts index 98a5f7258dca..0f927da28ee1 100644 --- a/arch/arm/boot/dts/sun4i-a10-marsboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-marsboard.dts @@ -141,7 +141,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index 484c57493bd2..a5ed9e4e22c6 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts @@ -97,7 +97,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-mk802.dts b/arch/arm/boot/dts/sun4i-a10-mk802.dts index 2b75745cd246..81db6824a2c7 100644 --- a/arch/arm/boot/dts/sun4i-a10-mk802.dts +++ b/arch/arm/boot/dts/sun4i-a10-mk802.dts @@ -72,7 +72,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-mk802ii.dts b/arch/arm/boot/dts/sun4i-a10-mk802ii.dts index c861fa7e356c..e74a881fd9a7 100644 --- a/arch/arm/boot/dts/sun4i-a10-mk802ii.dts +++ b/arch/arm/boot/dts/sun4i-a10-mk802ii.dts @@ -83,7 +83,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts index 3a2522a9419d..462412ee903c 100644 --- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts @@ -145,7 +145,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts index 83596fd2ccfc..84f55e76df0c 100644 --- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts @@ -147,7 +147,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts index a68c7cc53b94..c0f8c88b5a7d 100644 --- a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts +++ b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts @@ -149,7 +149,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index b63668ece151..41c2579143fd 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -1030,12 +1030,6 @@ bias-pull-up; }; - mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { - pins = "PH1"; - function = "gpio_in"; - bias-pull-up; - }; - ps20_pins_a: ps20@0 { pins = "PI20", "PI21"; function = "ps2"; diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index a2eab7aa80e0..7ac5bcc9f972 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -137,7 +137,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 102903e83bd2..4ebeecf9c3d7 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -178,7 +178,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts index 99c00b9a1546..6e6264cd69f8 100644 --- a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts +++ b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts @@ -160,7 +160,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts index 4da49717da21..e5cbcad3a556 100644 --- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts +++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts @@ -157,7 +157,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts index 28d3abbdc2d4..794e7617f545 100644 --- a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts +++ b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts @@ -104,7 +104,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 8 5 GPIO_ACTIVE_HIGH>; /* PI5 */ diff --git a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts index d52222c82cb8..8a8a6dbcd414 100644 --- a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts +++ b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts @@ -121,7 +121,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-m3.dts b/arch/arm/boot/dts/sun7i-a20-m3.dts index 86f69813683e..43c94787ef07 100644 --- a/arch/arm/boot/dts/sun7i-a20-m3.dts +++ b/arch/arm/boot/dts/sun7i-a20-m3.dts @@ -117,7 +117,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-mk808c.dts b/arch/arm/boot/dts/sun7i-a20-mk808c.dts index c4ee30709f3a..f7413094183c 100644 --- a/arch/arm/boot/dts/sun7i-a20-mk808c.dts +++ b/arch/arm/boot/dts/sun7i-a20-mk808c.dts @@ -109,7 +109,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts index 1af5b46862cb..64c8ef9a2756 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts @@ -187,7 +187,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts index dcd0f7a0dffa..2ce1a9f13a17 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts @@ -130,7 +130,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts index e7d45425758c..097bd755764c 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts @@ -131,7 +131,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index def0ad8395bb..0b7403e4d687 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -198,7 +198,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts index f47a5c46bc20..39bc73db72e5 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts @@ -130,7 +130,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts index 98177b5891cb..777152a3df0f 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts @@ -156,7 +156,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts index e19f17177755..f8d0aafb9f88 100644 --- a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts +++ b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts @@ -151,7 +151,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts index c3078d4f1093..84462d7961f5 100644 --- a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts +++ b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts @@ -120,7 +120,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 93aa55970bd7..c03b59aaec82 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -1190,12 +1190,6 @@ bias-pull-up; }; - mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { - pins = "PH1"; - function = "gpio_in"; - bias-pull-up; - }; - mmc2_pins_a: mmc2@0 { pins = "PC6", "PC7", "PC8", "PC9", "PC10", "PC11"; -- cgit v1.2.3 From 52826587a44f55e958e89c6f21bfdaadf0273ac8 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 19 Apr 2017 13:09:18 +0800 Subject: ARM: sun8i: h3: orangepi-pc: Enable USB OTG The Orange Pi PC, PC Plus, and Plus 2E all have a USB OTG port that can be used in both powered host mode and peripheral mode. When in peripheral mode, the port does not power the board. There is no VBUS sensing on the port. All three boards have all related pins routed the same way. The device tree file for the Orange Pi Plus 2E is based on the Orange Pi PC Plus, which itself is based on the Orange Pi PC. Changes to the base Orange Pi PC device tree file affects all 3 boards. This patch adds the regulator controlling VBUS on the OTG port, the GPIO for the ID detect pin, and enables the USB OTG and host controllers. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts index f148111c326d..1a044b17d6c6 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts @@ -97,6 +97,10 @@ status = "okay"; }; +&ehci0 { + status = "okay"; +}; + &ehci1 { status = "okay"; }; @@ -125,6 +129,10 @@ status = "okay"; }; +&ohci0 { + status = "okay"; +}; + &ohci1 { status = "okay"; }; @@ -156,6 +164,11 @@ }; }; +®_usb0_vbus { + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; @@ -180,7 +193,14 @@ status = "disabled"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { - /* USB VBUS is always on */ + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply = <®_usb0_vbus>; + /* VBUS on USB host ports are always on */ status = "okay"; }; -- cgit v1.2.3 From ef00b70d386499aa110a03fa283e35f5839f13fa Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 19 Apr 2017 13:09:19 +0800 Subject: ARM: sun8i: h3: bananapi-m2-plus: Enable USB OTG The Bananapi M2 Plus has a USB OTG port that can be used in both powered host mode and peripheral mode. When in peripheral mode, the port does not power the board. There is no VBUS sensing on the port. This patch adds the regulator controlling VBUS on the OTG port, the GPIO for the ID detect pin, and enables the USB OTG and host controllers. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts index 52acbe111cad..17c7c088cdea 100644 --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts @@ -92,6 +92,10 @@ }; }; +&ehci0 { + status = "okay"; +}; + &ehci1 { status = "okay"; }; @@ -145,6 +149,10 @@ status = "okay"; }; +&ohci0 { + status = "okay"; +}; + &ohci1 { status = "okay"; }; @@ -170,6 +178,11 @@ }; }; +®_usb0_vbus { + gpio = <&pio 3 11 GPIO_ACTIVE_HIGH>; /* PD11 */ + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; @@ -182,7 +195,14 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { - /* USB VBUS is on as long as VCC-IO is on */ + usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + usb0_vbus-supply = <®_usb0_vbus>; + /* USB host VBUS is on as long as VCC-IO is on */ status = "okay"; }; -- cgit v1.2.3 From 84f1738a9c6b9171e226e5324863e3257b89a503 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Thu, 20 Apr 2017 16:25:09 +0530 Subject: ARM: sun8i: Use - instead of @ for DT OPP entries Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by: Krzysztof Kozlowski Reported-by: Masahiro Yamada Suggested-by: Mark Rutland Signed-off-by: Viresh Kumar Acked-by: Maxime Ripard Acked-by: Rob Herring Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 4 ++-- arch/arm/boot/dts/sun8i-a33.dtsi | 30 +++++++++++++------------- 2 files changed, 17 insertions(+), 17 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts index 9b620cc1d5f1..8a0b42a2c2da 100644 --- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts @@ -88,13 +88,13 @@ }; &cpu0_opp_table { - opp@1104000000 { + opp-1104000000 { opp-hz = /bits/ 64 <1104000000>; opp-microvolt = <1320000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@1200000000 { + opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1320000>; clock-latency-ns = <244144>; /* 8 32k periods */ diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 013978259372..22660919bd08 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -50,73 +50,73 @@ compatible = "operating-points-v2"; opp-shared; - opp@120000000 { + opp-120000000 { opp-hz = /bits/ 64 <120000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@240000000 { + opp-240000000 { opp-hz = /bits/ 64 <240000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@312000000 { + opp-312000000 { opp-hz = /bits/ 64 <312000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@408000000 { + opp-408000000 { opp-hz = /bits/ 64 <408000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@480000000 { + opp-480000000 { opp-hz = /bits/ 64 <480000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@504000000 { + opp-504000000 { opp-hz = /bits/ 64 <504000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@600000000 { + opp-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@648000000 { + opp-648000000 { opp-hz = /bits/ 64 <648000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@720000000 { + opp-720000000 { opp-hz = /bits/ 64 <720000000>; opp-microvolt = <1100000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@816000000 { + opp-816000000 { opp-hz = /bits/ 64 <816000000>; opp-microvolt = <1100000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@912000000 { + opp-912000000 { opp-hz = /bits/ 64 <912000000>; opp-microvolt = <1200000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@1008000000 { + opp-1008000000 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <1200000>; clock-latency-ns = <244144>; /* 8 32k periods */ @@ -164,15 +164,15 @@ mali_opp_table: gpu-opp-table { compatible = "operating-points-v2"; - opp@144000000 { + opp-144000000 { opp-hz = /bits/ 64 <144000000>; }; - opp@240000000 { + opp-240000000 { opp-hz = /bits/ 64 <240000000>; }; - opp@384000000 { + opp-384000000 { opp-hz = /bits/ 64 <384000000>; }; }; -- cgit v1.2.3 From 4ee75fa55b7afd4cb65e378f0381f307bd63fa6c Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Tue, 18 Apr 2017 09:34:18 +0200 Subject: ARM: dtsi: axp209: add battery power supply subnode The X-Powers AXP209 PMIC exposes battery supply various data such as the battery status (charging, discharging, full, dead), current max limit, current current, battery capacity (in percentage), voltage max and min limits, current voltage, and battery capacity (in Ah). This adds the battery power supply subnode for AXP20X PMIC. Signed-off-by: Quentin Schulz Acked-by: Maxime Ripard Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/axp209.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi index 9677dd5cf6b6..3c8fa26e87b7 100644 --- a/arch/arm/boot/dts/axp209.dtsi +++ b/arch/arm/boot/dts/axp209.dtsi @@ -64,6 +64,11 @@ #gpio-cells = <2>; }; + battery_power_supply: battery-power-supply { + compatible = "x-powers,axp209-battery-power-supply"; + status = "disabled"; + }; + regulators { /* Default work frequency for buck regulators */ x-powers,dcdc-freq = <1500>; -- cgit v1.2.3 From 4ec5c401269607903d59e11332fd55f43a4531e7 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Tue, 18 Apr 2017 09:34:19 +0200 Subject: ARM: dtsi: axp22x: add battery power supply subnode The X-Powers AXP22X PMIC exposes battery supply various data such as the battery status (charging, discharging, full, dead), current max limit, current current, battery capacity (in percentage), voltage max limit, current voltage, and battery capacity (in Ah). This adds the battery power supply subnode for AXP22X PMIC. Signed-off-by: Quentin Schulz Acked-by: Maxime Ripard Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/axp22x.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/axp22x.dtsi b/arch/arm/boot/dts/axp22x.dtsi index 67331c5f1714..87fb08e812ec 100644 --- a/arch/arm/boot/dts/axp22x.dtsi +++ b/arch/arm/boot/dts/axp22x.dtsi @@ -57,6 +57,11 @@ status = "disabled"; }; + battery_power_supply: battery-power-supply { + compatible = "x-powers,axp221-battery-power-supply"; + status = "disabled"; + }; + regulators { /* Default work frequency for buck regulators */ x-powers,dcdc-freq = <3000>; -- cgit v1.2.3 From e7c42f327bc8444205f4d258718648b32fcca04e Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Tue, 18 Apr 2017 09:34:20 +0200 Subject: ARM: dts: sun8i: sina33: enable battery power supply subnode The Sinlinx SinA33 has an AXP223 PMIC and a battery connector, thus, we enable the battery power supply subnode in its Device Tree. Signed-off-by: Quentin Schulz Acked-by: Maxime Ripard Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts index 8a0b42a2c2da..433cf2a2a9a2 100644 --- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts @@ -196,6 +196,10 @@ status = "okay"; }; +&battery_power_supply { + status = "okay"; +}; + ®_aldo1 { regulator-always-on; regulator-min-microvolt = <3000000>; -- cgit v1.2.3 From b9107d3798b8fdf6098be6672a5e181a35b918d0 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Tue, 18 Apr 2017 09:34:21 +0200 Subject: ARM: sun5i: chip: enable battery power supply subnode The NextThing Co. CHIP has an AXP209 PMIC with battery connector. This enables the battery power supply subnode. Signed-off-by: Quentin Schulz Acked-by: Maxime Ripard Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-r8-chip.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts index d0785602663b..879a4b0f3bd5 100644 --- a/arch/arm/boot/dts/sun5i-r8-chip.dts +++ b/arch/arm/boot/dts/sun5i-r8-chip.dts @@ -132,6 +132,10 @@ status = "okay"; }; +&battery_power_supply { + status = "okay"; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins_a>; -- cgit v1.2.3 From 9a26882a7378ade6a74f845d439c8ef39b1a4712 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 21 Apr 2017 16:38:56 +0800 Subject: ARM: dts: sun6i: Add second display pipeline device nodes The Allwinner A31/A31s SoCs have 2 display pipelines, as in 2 display frontends, backends, and tcons each. The relationship between the backends and tcons are 1:1, but the frontends can feed either backend. Add device nodes and of graph nodes describing this relationship. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 168 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 167 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 9c999d3788f6..dfcf64515d7f 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -232,7 +232,7 @@ de: display-engine { compatible = "allwinner,sun6i-a31-display-engine"; - allwinner,pipelines = <&fe0>; + allwinner,pipelines = <&fe0>, <&fe1>; status = "disabled"; }; @@ -289,6 +289,43 @@ }; }; + tcon1: lcd-controller@01c0d000 { + compatible = "allwinner,sun6i-a31-tcon"; + reg = <0x01c0d000 0x1000>; + interrupts = ; + resets = <&ccu RST_AHB1_LCD1>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB1_LCD1>, + <&ccu CLK_LCD1_CH0>, + <&ccu CLK_LCD1_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon1-pixel-clock"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon1_in_drc1: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc1_out_tcon1>; + }; + }; + + tcon1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + mmc0: mmc@01c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; @@ -896,6 +933,130 @@ reg = <0>; remote-endpoint = <&be0_in_fe0>; }; + + fe0_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe0>; + }; + }; + }; + }; + + fe1: display-frontend@01e20000 { + compatible = "allwinner,sun6i-a31-display-frontend"; + reg = <0x01e20000 0x20000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>, + <&ccu CLK_DRAM_FE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_FE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe1_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe1>; + }; + + fe1_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe1>; + }; + }; + }; + }; + + be1: display-backend@01e40000 { + compatible = "allwinner,sun6i-a31-display-backend"; + reg = <0x01e40000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>, + <&ccu CLK_DRAM_BE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_BE1>; + + assigned-clocks = <&ccu CLK_BE1>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be1_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be1>; + }; + + be1_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be1>; + }; + }; + + be1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be1_out_drc1: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc1_in_be1>; + }; + }; + }; + }; + + drc1: drc@01e50000 { + compatible = "allwinner,sun6i-a31-drc"; + reg = <0x01e50000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>, + <&ccu CLK_DRAM_DRC1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_DRC1>; + + assigned-clocks = <&ccu CLK_IEP_DRC1>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + drc1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + drc1_in_be1: endpoint@0 { + reg = <0>; + remote-endpoint = <&be1_out_drc1>; + }; + }; + + drc1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + drc1_out_tcon1: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon1_in_drc1>; + }; }; }; }; @@ -926,6 +1087,11 @@ reg = <0>; remote-endpoint = <&fe0_out_be0>; }; + + be0_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be0>; + }; }; be0_out: port@1 { -- cgit v1.2.3 From f89f2a37cc52d13e94c91e134055a9d70c4b6690 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 21 Apr 2017 16:38:57 +0800 Subject: ARM: dts: sun6i: Enable tcon0 by default tcon0 contains a muxing register used to mux tcon output to downstream hdmi or mipi dsi encoders. tcon0 must be available for the mux to be configured. Whether the display subsystem is enabled or not is now solely controlled by the display-engine node. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 1 - arch/arm/boot/dts/sun6i-a31.dtsi | 1 - 2 files changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index b4c87a23e3f8..55607208468b 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -319,7 +319,6 @@ &tcon0 { pinctrl-names = "default"; pinctrl-0 = <&lcd0_rgb888_pins>; - status = "okay"; }; &tcon0_out { diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index dfcf64515d7f..d0cede5aaeb5 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -264,7 +264,6 @@ "tcon-ch0", "tcon-ch1"; clock-output-names = "tcon0-pixel-clock"; - status = "disabled"; ports { #address-cells = <1>; -- cgit v1.2.3 From e407e25d4f925d7be6d51fc8bc262efe7876bcf8 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 1 May 2017 11:14:07 +0800 Subject: ARM: sun8i: a83t: Drop leading zeroes from device node addresses Kbuild now complains about leading zeroes in the address portion of device node names. Get rid of them all, except for the uart device node. U-boot currently hard codes the device node path. We can remove the leading zero for the uart once we teach U-boot to use the aliases or stdout-path property. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 5f5c10c04dd3..aecde8be53bc 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -162,7 +162,7 @@ #size-cells = <1>; ranges; - pio: pinctrl@01c20800 { + pio: pinctrl@1c20800 { compatible = "allwinner,sun8i-a83t-pinctrl"; interrupts = , , @@ -193,7 +193,7 @@ }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; interrupts = , @@ -201,7 +201,7 @@ clocks = <&osc24M>; }; - watchdog@01c20ca0 { + watchdog@1c20ca0 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; interrupts = ; @@ -218,7 +218,7 @@ status = "disabled"; }; - gic: interrupt-controller@01c81000 { + gic: interrupt-controller@1c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, <0x01c82000 0x2000>, -- cgit v1.2.3 From 62628be26caae02b9320494c2fc5feb7daf7c1ee Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 1 May 2017 11:14:08 +0800 Subject: ARM: sun8i: a83t: Replace underscores with hyphens in pinmux node names We should use hyphens and not underscores in device node names. Replace the ones that were just added. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index aecde8be53bc..c0a1e4f74b89 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -174,7 +174,7 @@ #interrupt-cells = <3>; #gpio-cells = <3>; - mmc0_pins: mmc0_pins { + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; @@ -182,12 +182,12 @@ bias-pull-up; }; - uart0_pb_pins: uart0_pb_pins { + uart0_pb_pins: uart0-pb-pins { pins = "PB9", "PB10"; function = "uart0"; }; - uart0_pf_pins: uart0_pf_pins { + uart0_pf_pins: uart0-pf-pins { pins = "PF2", "PF4"; function = "uart0"; }; -- cgit v1.2.3 From e20f04935176ec16f62c3c9c8b219490661aa10c Mon Sep 17 00:00:00 2001 From: Marcus Cooper Date: Wed, 10 May 2017 11:51:38 +0000 Subject: ARM: dts: sun8i-h3: orange-pi-2: Enable audio codec The Orange Pi 2 routes the LINEOUT pins through a SGM8900 PA which needs to be enabled. The onboard microphone is routed to MIC1, with MBIAS providing power. Signed-off-by: Marcus Cooper Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index d7d5330c566f..8ff71b1bb45b 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -104,6 +104,15 @@ }; }; +&codec { + allwinner,pa-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */ + allwinner,audio-routing = + "Speaker", "LINEOUT", + "MIC1", "Mic", + "Mic", "MBIAS"; + status = "okay"; +}; + &ehci1 { status = "okay"; }; -- cgit v1.2.3 From 392aba5558843891cb938cbb8f3da1e1557c87c4 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Sat, 6 May 2017 07:30:38 +0200 Subject: arm: dts: sun7i-a20-bananapi: name the GPIO lines This names the GPIO lines on the Banana Pi board in accordance with the A20_Banana_Pi v1.4 Specification. This will make these line names reflect through to user space so that they can easily be identified and used with the new character device ABI. Signed-off-by: Oleksij Rempel Reviewed-by: Linus Walleij Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-bananapi.dts | 51 ++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts index ed2f35adf542..88a1c2363c6c 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts @@ -177,6 +177,57 @@ }; &pio { + gpio-line-names = + /* PA */ + "ERXD3", "ERXD2", "ERXD1", "ERXD0", "ETXD3", + "ETXD2", "ETXD1", "ETXD0", + "ERXCK", "ERXERR", "ERXDV", "EMDC", "EMDIO", + "ETXEN", "ETXCK", "ECRS", + "ECOL", "ETXERR", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PB */ + "PMU-SCK", "PMU-SDA", "", "", "", "", "", "", + "", "USB0-DRV", "", "", "", "", "", "", + "", "", "", "", "SCL", "SDA", "", "", + "", "", "", "", "", "", "", "", + /* PC */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PD */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PE */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PF */ + "SD0-D1", "SD0-D0", "SD0-CLK", "SD0-CMD", "SD0-D3", + "SD0-D2", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PG */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PH */ + "TXD0", "RXD0", "IO-1", "PH3", "USB0-IDDET", "PH5", "", "", + "", "", "SD0-DET", "", "", "", "", "", + "", "", "", "", "IO-4", "IO-5", "", "EMAC-PWR-EN", + "LED1", "", "", "", "", "", "", "", + /* PI */ + "", "", "", "IO-GCLK", "", "", "", "", + "", "", "SPI-CE0", "SPI-CLK", "SPI-MOSI", + "SPI-MISO", "SPI-CE1", "", + "IO-6", "IO-3", "IO-2", "IO-0", "", "", "", "", + "", "", "", "", "", "", "", ""; + usb0_id_detect_pin: usb0_id_detect_pin@0 { pins = "PH4"; function = "gpio_in"; -- cgit v1.2.3 From 96800f036813c648cdd64918399bdd6768e68273 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Fri, 17 Mar 2017 18:18:39 +0100 Subject: ARM: dts: rockchip: rename core dtsi from RK1108 to RV1108 Rockchip finally named the SOC as RV1108, so change it for compatible. Signed-off-by: Andy Yan [adapt include in rk1108-evb.dts to not introduce errors] Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk1108-evb.dts | 2 +- arch/arm/boot/dts/rk1108.dtsi | 452 --------------------------------------- arch/arm/boot/dts/rv1108.dtsi | 452 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 453 insertions(+), 453 deletions(-) delete mode 100644 arch/arm/boot/dts/rk1108.dtsi create mode 100644 arch/arm/boot/dts/rv1108.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk1108-evb.dts b/arch/arm/boot/dts/rk1108-evb.dts index 3956cff4ca79..88fe0a8c4faa 100644 --- a/arch/arm/boot/dts/rk1108-evb.dts +++ b/arch/arm/boot/dts/rk1108-evb.dts @@ -40,7 +40,7 @@ /dts-v1/; -#include "rk1108.dtsi" +#include "rv1108.dtsi" / { model = "Rockchip RK1108 Evaluation board"; diff --git a/arch/arm/boot/dts/rk1108.dtsi b/arch/arm/boot/dts/rk1108.dtsi deleted file mode 100644 index 1297924db6ad..000000000000 --- a/arch/arm/boot/dts/rk1108.dtsi +++ /dev/null @@ -1,452 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -/ { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "rockchip,rk1108"; - - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = ; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - ; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@102a0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x102a0000 0x4000>; - interrupts = ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - }; - - bus_intmem@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x2000>; - }; - - uart2: serial@10210000 { - compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart"; - reg = <0x10210000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "disabled"; - }; - - uart1: serial@10220000 { - compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart"; - reg = <0x10220000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - status = "disabled"; - }; - - uart0: serial@10230000 { - compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart"; - reg = <0x10230000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "disabled"; - }; - - grf: syscon@10300000 { - compatible = "rockchip,rk1108-grf", "syscon"; - reg = <0x10300000 0x1000>; - }; - - pmugrf: syscon@20060000 { - compatible = "rockchip,rk1108-pmugrf", "syscon"; - reg = <0x20060000 0x1000>; - }; - - cru: clock-controller@20200000 { - compatible = "rockchip,rk1108-cru"; - reg = <0x20200000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - emmc: dwmmc@30110000 { - compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x30110000 0x4000>; - status = "disabled"; - }; - - sdio: dwmmc@30120000 { - compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x30120000 0x4000>; - status = "disabled"; - }; - - sdmmc: dwmmc@30130000 { - compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 100000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x30130000 0x4000>; - status = "disabled"; - }; - - gic: interrupt-controller@32010000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x32011000 0x1000>, - <0x32012000 0x2000>, - <0x32014000 0x2000>, - <0x32016000 0x2000>; - interrupts = ; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rv1108-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@20030000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20030000 0x100>; - interrupts = ; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@10310000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10310000 0x100>; - interrupts = ; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@10320000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10320000 0x100>; - interrupts = ; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@10330000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10330000 0x100>; - interrupts = ; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { - drive-strength = <12>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { - drive-strength = <4>; - }; - - pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { - bias-pull-up; - drive-strength = <4>; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_input_high: pcfg-input-high { - bias-pull-up; - input-enable; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; - }; - }; - - i2c2m1 { - i2c2m1_xfer: i2c2m1-xfer { - rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>; - }; - - i2c2m1_gpio: i2c2m1-gpio { - rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - i2c2m05v { - i2c2m05v_xfer: i2c2m05v-xfer { - rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>; - }; - - i2c2m05v_gpio: i2c2m05v-gpio { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, - <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_cd: sdmmc-cd { - rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>, - <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts_gpio: uart0-rts-gpio { - rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, - <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2m0 { - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2m1 { - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>, - <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - uart2_5v { - uart2_5v_cts: uart2_5v-cts { - rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart2_5v_rts: uart2_5v-rts { - rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi new file mode 100644 index 000000000000..437098b556eb --- /dev/null +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -0,0 +1,452 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "rockchip,rv1108"; + + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + ; + clock-frequency = <24000000>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@102a0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x102a0000 0x4000>; + interrupts = ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + }; + }; + + bus_intmem@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x2000>; + }; + + uart2: serial@10210000 { + compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; + reg = <0x10210000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "disabled"; + }; + + uart1: serial@10220000 { + compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; + reg = <0x10220000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + status = "disabled"; + }; + + uart0: serial@10230000 { + compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; + reg = <0x10230000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "disabled"; + }; + + grf: syscon@10300000 { + compatible = "rockchip,rv1108-grf", "syscon"; + reg = <0x10300000 0x1000>; + }; + + pmugrf: syscon@20060000 { + compatible = "rockchip,rv1108-pmugrf", "syscon"; + reg = <0x20060000 0x1000>; + }; + + cru: clock-controller@20200000 { + compatible = "rockchip,rv1108-cru"; + reg = <0x20200000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + emmc: dwmmc@30110000 { + compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + reg = <0x30110000 0x4000>; + status = "disabled"; + }; + + sdio: dwmmc@30120000 { + compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + reg = <0x30120000 0x4000>; + status = "disabled"; + }; + + sdmmc: dwmmc@30130000 { + compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 100000000>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + reg = <0x30130000 0x4000>; + status = "disabled"; + }; + + gic: interrupt-controller@32010000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x32011000 0x1000>, + <0x32012000 0x2000>, + <0x32014000 0x2000>, + <0x32016000 0x2000>; + interrupts = ; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rv1108-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@20030000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20030000 0x100>; + interrupts = ; + clocks = <&xin24m>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@10310000 { + compatible = "rockchip,gpio-bank"; + reg = <0x10310000 0x100>; + interrupts = ; + clocks = <&xin24m>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@10320000 { + compatible = "rockchip,gpio-bank"; + reg = <0x10320000 0x100>; + interrupts = ; + clocks = <&xin24m>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@10330000 { + compatible = "rockchip,gpio-bank"; + reg = <0x10330000 0x100>; + interrupts = ; + clocks = <&xin24m>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + drive-strength = <8>; + }; + + pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { + drive-strength = <12>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { + drive-strength = <4>; + }; + + pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { + bias-pull-up; + drive-strength = <4>; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_input_high: pcfg-input-high { + bias-pull-up; + input-enable; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, + <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + i2c2m1 { + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, + <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>; + }; + + i2c2m1_gpio: i2c2m1-gpio { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + i2c2m05v { + i2c2m05v_xfer: i2c2m05v-xfer { + rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>; + }; + + i2c2m05v_gpio: i2c2m05v-gpio { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + }; + + sdmmc_cd: sdmmc-cd { + rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + }; + + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, + <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, + <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, + <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>, + <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts_gpio: uart0-rts-gpio { + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, + <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart2m0 { + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>, + <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart2m1 { + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>, + <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart2_5v { + uart2_5v_cts: uart2_5v-cts { + rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart2_5v_rts: uart2_5v-rts { + rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + }; +}; -- cgit v1.2.3 From 5be21d0a0f487f779d6e1e72790852769e9d976f Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Fri, 17 Mar 2017 18:18:40 +0100 Subject: ARM: dts: rockchip: rename RK1108-evb to RV1108-evb Rockchip finally named the SOC as RV1108, so change it for compatible. The rk1108/rv1108 is completely new to the market, so there no real devices exist in the wild, only the Rockchip internal evaluation board. Therefore we're not breaking any existing devices when changing compatible values. Signed-off-by: Andy Yan Acked-by: Rob Herring [added paragraph about no real devices existing] Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/Makefile | 2 +- arch/arm/boot/dts/rk1108-evb.dts | 69 ---------------------------------------- arch/arm/boot/dts/rv1108-evb.dts | 69 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 70 insertions(+), 70 deletions(-) delete mode 100644 arch/arm/boot/dts/rk1108-evb.dts create mode 100644 arch/arm/boot/dts/rv1108-evb.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9c5e1d944d1c..32537f8c9e41 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -718,7 +718,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r8a7794-silk.dtb \ sh73a0-kzm9g.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ - rk1108-evb.dtb \ + rv1108-evb.dtb \ rk3036-evb.dtb \ rk3036-kylin.dtb \ rk3066a-bqcurie2.dtb \ diff --git a/arch/arm/boot/dts/rk1108-evb.dts b/arch/arm/boot/dts/rk1108-evb.dts deleted file mode 100644 index 88fe0a8c4faa..000000000000 --- a/arch/arm/boot/dts/rk1108-evb.dts +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "rv1108.dtsi" - -/ { - model = "Rockchip RK1108 Evaluation board"; - compatible = "rockchip,rk1108-evb", "rockchip,rk1108"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x08000000>; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts new file mode 100644 index 000000000000..58cf4ac079c3 --- /dev/null +++ b/arch/arm/boot/dts/rv1108-evb.dts @@ -0,0 +1,69 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "rv1108.dtsi" + +/ { + model = "Rockchip RV1108 Evaluation board"; + compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x08000000>; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; -- cgit v1.2.3 From 1999c614fbfcf7a1f228c62a3b92466e7d914c6d Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Tue, 2 May 2017 17:46:00 +0300 Subject: ARM: imx_v6_v7_defconfig: Enable cpufreq governors Enable more common cpufreq governors in imx defconfig because this is very useful for testing. In particular you can't use cpufreq-set -f $FREQ without explicitly defining CONFIG_CPU_FREQ_GOV_USERSPACE=y. Signed-off-by: Leonard Crestez Acked-by: Dong Aisheng Signed-off-by: Shawn Guo --- arch/arm/configs/imx_v6_v7_defconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index bb6fa568b620..bf1e7e316918 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -55,6 +55,9 @@ CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" CONFIG_KEXEC=y CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y CONFIG_ARM_IMX6Q_CPUFREQ=y CONFIG_CPU_IDLE=y CONFIG_VFP=y -- cgit v1.2.3 From 1b1ec50366a87ed84ac07db9a09c56ac7cafb367 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 10 Apr 2017 13:58:10 -0700 Subject: ARM: dts: imx: ventana: fix DTC warnings Remove the sky2 ethernet device node from the pcie controller which was invalid to begin with. The original intent was to allow the bootloader to populate the MAC via dt but this requires the PCI bus topology to be complete in dt as well and as these boards have an expansion connector that topology is dynamic and can't be represented here. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-gw5400-a.dts | 5 ----- arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 5 ----- arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 5 ----- 3 files changed, 15 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index 8e84713f42c0..687ab911c13f 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -19,7 +19,6 @@ /* these are used by bootloader for disabling nodes */ aliases { - ethernet1 = ð1; i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; @@ -347,10 +346,6 @@ &pcie { reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; status = "okay"; - - eth1: sky2@8 { /* MAC/PHY on bus 8 */ - compatible = "marvell,sky2"; - }; }; &ssi1 { diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index a208e7e0dc6e..5bc6ed1a5b35 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -14,7 +14,6 @@ / { /* these are used by bootloader for disabling nodes */ aliases { - ethernet1 = ð1; led0 = &led0; led1 = &led1; led2 = &led2; @@ -342,10 +341,6 @@ pinctrl-0 = <&pinctrl_pcie>; reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; status = "okay"; - - eth1: sky2@8 { /* MAC/PHY on bus 8 */ - compatible = "marvell,sky2"; - }; }; &pwm2 { diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 968fda94d14b..66fcf838e964 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -14,7 +14,6 @@ / { /* these are used by bootloader for disabling nodes */ aliases { - ethernet1 = ð1; led0 = &led0; led1 = &led1; led2 = &led2; @@ -379,10 +378,6 @@ pinctrl-0 = <&pinctrl_pcie>; reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; status = "okay"; - - eth1: sky2@8 { /* MAC/PHY on bus 8 */ - compatible = "marvell,sky2"; - }; }; &pwm1 { -- cgit v1.2.3 From e761b82ef22269b4e4fdf1a4d397c09522bc5d54 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 12 Apr 2017 18:45:59 +0200 Subject: ARM: dts: imx6: adopt DT to new GPC binding Adopt the i.MX6Q/DL DT to the new and more flexible GPC binding. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q.dtsi | 2 +- arch/arm/boot/dts/imx6qdl.dtsi | 37 ++++++++++++++++++++++++++----------- 2 files changed, 27 insertions(+), 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index e9a5d0b8c7b0..dd33849335b2 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -125,7 +125,7 @@ clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, <&clks IMX6QDL_CLK_GPU2D_CORE>; clock-names = "bus", "core"; - power-domains = <&gpc 1>; + power-domains = <&pd_pu>; }; ipu2: ipu@02800000 { diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index e426faa9c243..2c2af6737b0e 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -156,7 +156,7 @@ <&clks IMX6QDL_CLK_GPU3D_CORE>, <&clks IMX6QDL_CLK_GPU3D_SHADER>; clock-names = "bus", "core", "shader"; - power-domains = <&gpc 1>; + power-domains = <&pd_pu>; }; gpu_2d: gpu@00134000 { @@ -166,7 +166,7 @@ clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, <&clks IMX6QDL_CLK_GPU2D_CORE>; clock-names = "bus", "core"; - power-domains = <&gpc 1>; + power-domains = <&pd_pu>; }; timer@00a00600 { @@ -434,7 +434,7 @@ clocks = <&clks IMX6QDL_CLK_VPU_AXI>, <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; clock-names = "per", "ahb"; - power-domains = <&gpc 1>; + power-domains = <&pd_pu>; resets = <&src 1>; iram = <&ocram>; }; @@ -797,14 +797,29 @@ interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, <0 90 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; - pu-supply = <®_pu>; - clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, - <&clks IMX6QDL_CLK_GPU3D_SHADER>, - <&clks IMX6QDL_CLK_GPU2D_CORE>, - <&clks IMX6QDL_CLK_GPU2D_AXI>, - <&clks IMX6QDL_CLK_OPENVG_AXI>, - <&clks IMX6QDL_CLK_VPU_AXI>; - #power-domain-cells = <1>; + clocks = <&clks IMX6QDL_CLK_IPG>; + clock-names = "ipg"; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + power-domain@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + pd_pu: power-domain@1 { + reg = <1>; + #power-domain-cells = <0>; + power-supply = <®_pu>; + clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, + <&clks IMX6QDL_CLK_GPU3D_SHADER>, + <&clks IMX6QDL_CLK_GPU2D_CORE>, + <&clks IMX6QDL_CLK_GPU2D_AXI>, + <&clks IMX6QDL_CLK_OPENVG_AXI>, + <&clks IMX6QDL_CLK_VPU_AXI>; + }; + }; }; gpr: iomuxc-gpr@020e0000 { -- cgit v1.2.3 From 6447a053ddf6e3e42af6c8e1c65a8ec2b367abbc Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 12 Apr 2017 18:46:00 +0200 Subject: ARM: dts: imx6qp: add specific compatible for GPC Add the more specific QuadPlus compatible to the GPC node, to trigger the required workarounds in the power domain code. In regard to the interrupt mapping the QuadPlus controller is fully compatible to the Quad one, so keep that compatible in place. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qp.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi index 59453f2ac4ba..299d863690c5 100644 --- a/arch/arm/boot/dts/imx6qp.dtsi +++ b/arch/arm/boot/dts/imx6qp.dtsi @@ -120,6 +120,10 @@ <0 119 IRQ_TYPE_LEVEL_HIGH>; }; +&gpc { + compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc"; +}; + &ipu1 { compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; fsl,prg = <&prg1>; -- cgit v1.2.3 From b8a559feffb2210344bb11cedc1103311ac41de5 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 2 May 2017 10:39:37 -0700 Subject: ARM: dts: imx: add Gateworks Ventana GW5600 support The Gateworks Ventana GW5600 is a media-centric single-board computer based on the NXP IMX6 SoC with the following features: * PoE (emulated 802.3af) * IMX6 DualLite Soc (supports IMX6S,IMX6DL,IMX6Q) * 1GiB DDR3 DRAM (supports up to 4GiB) * 8GB eMMC * 1x microSD connector * Gateworks System Controller: - hardware watchdog - hardware monitor - pushbutton controller - EEPROM storage - power control * 1x bi-color USER LED * 1x front-panel pushbutton * 1x front-panel GbE * 2x front panel USB 2.0 * 1x front panel USB OTG * 1x SIM socket * 1x miniPCIe socket with SATA (mSATA) * 1x miniPCIe socket with USB 2.0 (Modem) * 1x miniPCIe socket with PCIe, USB 2.0, and SIM * RS232/RS485 serial - 2x RS232 UARTs (off-board connector) - 1x RS485 (loading option) * 4x digital I/O signals (PWM/I2C/GPIO/5V/3.3V options) * 1x analog input (0 to 5V) * 1x CAN (loading option) * off-board LVDS: - I2C - 12V - LED driver (4x 330mA strings) - matrix keypad controller (8row x 10col) - I2S - dual-channel LVDS - PWM * off-board video input: - 16bit parallel / MIPI (IPU1_CSI0) * GPS (loading option) * Analog Video Input (CVBS) 3 inputs (1 active at a time) * Analog Audio Input/Output (2ch Line level, optional MIC/HP drivers) * HDMI out * JTAG programmable * Inertial Module Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-gw560x.dts | 55 +++ arch/arm/boot/dts/imx6q-gw560x.dts | 59 +++ arch/arm/boot/dts/imx6qdl-gw560x.dtsi | 749 ++++++++++++++++++++++++++++++++++ 4 files changed, 865 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-gw560x.dts create mode 100644 arch/arm/boot/dts/imx6q-gw560x.dts create mode 100644 arch/arm/boot/dts/imx6qdl-gw560x.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9c5e1d944d1c..7881aaef2d58 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -363,6 +363,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-gw551x.dtb \ imx6dl-gw552x.dtb \ imx6dl-gw553x.dtb \ + imx6dl-gw560x.dtb \ imx6dl-gw5903.dtb \ imx6dl-gw5904.dtb \ imx6dl-hummingboard.dtb \ @@ -408,6 +409,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-gw551x.dtb \ imx6q-gw552x.dtb \ imx6q-gw553x.dtb \ + imx6q-gw560x.dtb \ imx6q-gw5903.dtb \ imx6q-gw5904.dtb \ imx6q-h100.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-gw560x.dts b/arch/arm/boot/dts/imx6dl-gw560x.dts new file mode 100644 index 000000000000..21bdfaf8df53 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-gw560x.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2017 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw560x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW560X"; + compatible = "gw,imx6dl-gw560x", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6q-gw560x.dts b/arch/arm/boot/dts/imx6q-gw560x.dts new file mode 100644 index 000000000000..735f2bbf1439 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-gw560x.dts @@ -0,0 +1,59 @@ +/* + * Copyright 2017 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw560x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW560X"; + compatible = "gw,imx6q-gw560x", "gw,ventana", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi new file mode 100644 index 000000000000..d894dde6e85d --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi @@ -0,0 +1,749 @@ +/* + * Copyright 2017 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + ssi0 = &ssi1; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + stdout-path = &uart2; + }; + + backlight-display { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = < + 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <100>; + }; + + backlight-keypad { + compatible = "gpio-backlight"; + gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; + default-on; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + + led2: user3 { + label = "user3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory@10000000 { + reg = <0x10000000 0x40000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_12p0v: regulator-12p0v { + compatible = "regulator-fixed"; + regulator-name = "12P0V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_1p4v: regulator-vddsoc { + compatible = "regulator-fixed"; + regulator-name = "vdd_soc"; + regulator-min-microvolt = <1400000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx6q-ventana-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + pca9555: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + ds1672: rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_3p3v>; + }; + + tca8418: keypad@34 { + compatible = "ti,tca8418"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_keypad>; + reg = <0x34>; + interrupt-parent = <&gpio5>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + linux,keymap = < MATRIX_KEY(0x00, 0x01, BTN_0) + MATRIX_KEY(0x00, 0x00, BTN_1) + MATRIX_KEY(0x01, 0x01, BTN_2) + MATRIX_KEY(0x01, 0x00, BTN_3) + MATRIX_KEY(0x02, 0x00, BTN_4) + MATRIX_KEY(0x00, 0x03, BTN_5) + MATRIX_KEY(0x00, 0x02, BTN_6) + MATRIX_KEY(0x01, 0x03, BTN_7) + MATRIX_KEY(0x01, 0x02, BTN_8) + MATRIX_KEY(0x02, 0x02, BTN_9) + >; + keypad,num-rows = <4>; + keypad,num-columns = <4>; + }; + + ltc3676: pmic@3c { + compatible = "lltc,ltc3676"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x3c>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + regulators { + /* VDD_DDR (1+R1/R2 = 2.105) */ + reg_vdd_ddr: sw2 { + regulator-name = "vddddr"; + regulator-min-microvolt = <868310>; + regulator-max-microvolt = <1684000>; + lltc,fb-voltage-divider = <221000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_ARM (1+R1/R2 = 1.931) */ + reg_vdd_arm: sw3 { + regulator-name = "vddarm"; + regulator-min-microvolt = <796551>; + regulator-max-microvolt = <1544827>; + lltc,fb-voltage-divider = <243000 261000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + linux,phandle = <®_vdd_arm>; + }; + + /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ + reg_1p8v: sw4 { + regulator-name = "vdd1p8"; + regulator-min-microvolt = <1033310>; + regulator-max-microvolt = <2004000>; + lltc,fb-voltage-divider = <301000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P0 (1+R1/R2 = 1.39): PCIe/ENET-PHY */ + reg_1p0v: ldo2 { + regulator-name = "vdd1p0"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1050000>; + lltc,fb-voltage-divider = <78700 200000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_AUD_1P8: Audio codec */ + reg_aud_1p8v: ldo3 { + regulator-name = "vdd1p8a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + /* VDD_HIGH (1+R1/R2 = 4.17) */ + reg_3p0v: ldo4 { + regulator-name = "vdd3p0"; + regulator-min-microvolt = <3023250>; + regulator-max-microvolt = <3023250>; + lltc,fb-voltage-divider = <634000 200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + egalax_ts: touchscreen@4 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio5>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + }; +}; + +&ldb { + fsl,dual-channel; + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio4 31 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; + vmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + /* AUD4 */ + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ + /* AUD6 */ + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 + MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 + >; + }; + + pinctrl_ecspi3: escpi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ + >; + }; + + pinctrl_flexcan: flexcangrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x4001b0b0 /* DIOI2C_DIS# */ + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0001b0b0 /* LVDS_TOUCH_IRQ# */ + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0001b0b0 /* LVDS_BACKEN */ + >; + }; + + pinctrl_keypad: keypadgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */ + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x0001b0b0 /* KEYPAD_LED_EN */ + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* USBHUB_RST# */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x170f9 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x170f9 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x170f9 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; -- cgit v1.2.3 From 2b7349345ede5a8c221a7ca2d6731588241d8425 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 19 Apr 2017 22:22:02 +0200 Subject: ARM: dts: imx6qdl-nitrogen6_max: fix rv4162 compatible The rv4162 vendor is microcrystal, not ST. Signed-off-by: Alexandre Belloni Acked-by: Gary Bisson Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index bad3c9f9eeac..b63134e3b51a 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -408,7 +408,7 @@ }; rtc: rtc@68 { - compatible = "st,rv4162"; + compatible = "microcrystal,rv4162"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rv4162>; reg = <0x68>; -- cgit v1.2.3 From 16e54a1452eddfb2af28546e9bf2f8bffb8eabdd Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 19 Apr 2017 22:22:03 +0200 Subject: ARM: dts: imx6qdl-nitrogen6_som2: fix rv4162 compatible The rv4162 vendor is microcrystal, not ST. Signed-off-by: Alexandre Belloni Acked-by: Gary Bisson Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi index 559da17297ef..aeaa5a6e4fcf 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi @@ -326,7 +326,7 @@ }; rtc@68 { - compatible = "st,rv4162"; + compatible = "microcrystal,rv4162"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rv4162>; reg = <0x68>; -- cgit v1.2.3 From dcf79dc58b368d29bccc087852846eb1117eac7a Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 19 Apr 2017 22:22:04 +0200 Subject: ARM: dts: imx7d-nitrogen7: fix rv4162 compatible The rv4162 compatbile string is missing the vendor part, add it. Signed-off-by: Alexandre Belloni Acked-by: Gary Bisson Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-nitrogen7.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index 5d98e2b5d54b..a44f992051ac 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -279,7 +279,7 @@ status = "okay"; rtc@68 { - compatible = "rv4162"; + compatible = "microcrystal,rv4162"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2_rv4162>; reg = <0x68>; -- cgit v1.2.3 From e711b857aab01c2cfa563aadc6a4c669169c1c4c Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 10 Apr 2017 14:00:15 -0700 Subject: ARM: dts: imx7: add USDHC NAND and IPG clock to SDHC instances The USDHC instances need the USDHC NAND and IPG clock in order to operate. Reference them properly by replacing the dummy clocks with the actual clocks. Note that both clocks are currently implicitly enabled since they are part of the i.MX 7 clock drivers init_on list. This might change in the future. Signed-off-by: Stefan Agner Acked-by: Dong Aisheng Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index c4f12fd2e044..843eb379e1ea 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -934,8 +934,8 @@ compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; reg = <0x30b40000 0x10000>; interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>, + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, <&clks IMX7D_USDHC1_ROOT_CLK>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; @@ -946,8 +946,8 @@ compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; reg = <0x30b50000 0x10000>; interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>, + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, <&clks IMX7D_USDHC2_ROOT_CLK>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; @@ -958,8 +958,8 @@ compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; reg = <0x30b60000 0x10000>; interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>, + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, <&clks IMX7D_USDHC3_ROOT_CLK>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; -- cgit v1.2.3 From 6559b3915592b32fc43f78ef7ae04f614595a6cf Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 26 Apr 2017 12:05:30 +0200 Subject: ARM: dts: emev2: update PFC node name to pin-controller The device trees for Renesas SoCs use either pfc or pin-controller as the node name for the PFC device. This patch is intended to take a step towards unifying the node name used as pin-controller which appears to be the more generic of the two and thus more in keeping with the DT specs. My analysis is that this is a user-visible change to the extent that kernel logs, and sysfs entries change from e0140200.pfc and pfc@e0140200 to e0140200.pin-controller and pin-controller@e0140200. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/emev2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index 0124faf175c8..42ea246e71cb 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -197,7 +197,7 @@ clock-names = "sclk"; }; - pfc: pfc@e0140200 { + pfc: pin-controller@e0140200 { compatible = "renesas,pfc-emev2"; reg = <0xe0140200 0x100>; }; -- cgit v1.2.3 From 5b9906c9ee3b7117273467e3e74ecbd8f93ea730 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 26 Apr 2017 12:05:31 +0200 Subject: ARM: dts: r8a73a4: update PFC node name to pin-controller The device trees for Renesas SoCs use either pfc or pin-controller as the node name for the PFC device. This patch is intended to take a step towards unifying the node name used as pin-controller which appears to be the more generic of the two and thus more in keeping with the DT specs. My analysis is that this is a user-visible change to the extent that kernel logs, and sysfs entries change from e6050000.pfc and pfc@e6050000 to e6050000.pin-controller and pin-controller@e6050000. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a73a4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 1f5c9f6dddba..310222634570 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -219,7 +219,7 @@ power-domains = <&pd_c4>; }; - pfc: pfc@e6050000 { + pfc: pin-controller@e6050000 { compatible = "renesas,pfc-r8a73a4"; reg = <0 0xe6050000 0 0x9000>; gpio-controller; -- cgit v1.2.3 From 9d65683f6e228df6b3b0e6b74de4729a782b1e65 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 26 Apr 2017 12:05:32 +0200 Subject: ARM: dts: r8a7740: update PFC node name to pin-controller The device trees for Renesas SoCs use either pfc or pin-controller as the node name for the PFC device. This patch is intended to take a step towards unifying the node name used as pin-controller which appears to be the more generic of the two and thus more in keeping with the DT specs. My analysis is that this is a user-visible change to the extent that kernel logs, and sysfs entries change from e6050000.pfc and pfc@e6050000 to e6050000.pin-controller and pin-controller@e6050000. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7740.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 34159a8349de..d37d22682a63 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -299,7 +299,7 @@ status = "disabled"; }; - pfc: pfc@e6050000 { + pfc: pin-controller@e6050000 { compatible = "renesas,pfc-r8a7740"; reg = <0xe6050000 0x8000>, <0xe605800c 0x20>; -- cgit v1.2.3 From b3ed04985ce6d19a0cb12dccf95d41c1b86693cc Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 26 Apr 2017 12:05:33 +0200 Subject: ARM: dts: r8a7778: update PFC node name to pin-controller The device trees for Renesas SoCs use either pfc or pin-controller as the node name for the PFC device. This patch is intended to take a step towards unifying the node name used as pin-controller which appears to be the more generic of the two and thus more in keeping with the DT specs. My analysis is that this is a user-visible change to the extent that kernel logs, and sysfs entries change from fffc0000.pfc and pfc@fffc0000 to fffc0000.pin-controller and pin-controller@fffc0000. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7778.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 1e93c94a9eac..8f3156c0e575 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -142,7 +142,7 @@ interrupt-controller; }; - pfc: pfc@fffc0000 { + pfc: pin-controller@fffc0000 { compatible = "renesas,pfc-r8a7778"; reg = <0xfffc0000 0x118>; }; -- cgit v1.2.3 From b07b763c5255cf400ddfd4b6a7899adf0538dea9 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 26 Apr 2017 12:05:34 +0200 Subject: ARM: dts: r8a7779: update PFC node name to pin-controller The device trees for Renesas SoCs use either pfc or pin-controller as the node name for the PFC device. This patch is intended to take a step towards unifying the node name used as pin-controller which appears to be the more generic of the two and thus more in keeping with the DT specs. My analysis is that this is a user-visible change to the extent that kernel logs, and sysfs entries change from fffc0000.pfc and pfc@fffc0000 to fffc0000.pin-controller and pin-controller@fffc0000. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7779.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index ae2d9a9c65af..8ee0b2ca5d39 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -286,7 +286,7 @@ status = "disabled"; }; - pfc: pfc@fffc0000 { + pfc: pin-controller@fffc0000 { compatible = "renesas,pfc-r8a7779"; reg = <0xfffc0000 0x23c>; }; -- cgit v1.2.3 From a5f4ae3c3165134599ad850f8d34c6a35d6c0f97 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 26 Apr 2017 12:05:35 +0200 Subject: ARM: dts: r8a7790: update PFC node name to pin-controller The device trees for Renesas SoCs use either pfc or pin-controller as the node name for the PFC device. This patch is intended to take a step towards unifying the node name used as pin-controller which appears to be the more generic of the two and thus more in keeping with the DT specs. My analysis is that this is a user-visible change to the extent that kernel logs, and sysfs entries change from e6060000.pfc and pfc@e6060000 to e6060000.pin-controller and pin-controller@e6060000. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7790.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 99269aaca6fc..416956a42c93 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -614,7 +614,7 @@ max-frequency = <97500000>; }; - pfc: pfc@e6060000 { + pfc: pin-controller@e6060000 { compatible = "renesas,pfc-r8a7790"; reg = <0 0xe6060000 0 0x250>; }; -- cgit v1.2.3 From 12cc7145d4dbb7849468fa3c834de4f66e60323a Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 26 Apr 2017 12:05:36 +0200 Subject: ARM: dts: r8a7791: update PFC node name to pin-controller The device trees for Renesas SoCs use either pfc or pin-controller as the node name for the PFC device. This patch is intended to take a step towards unifying the node name used as pin-controller which appears to be the more generic of the two and thus more in keeping with the DT specs. My analysis is that this is a user-visible change to the extent that kernel logs, and sysfs entries change from e6060000.pfc and pfc@e6060000 to e6060000.pin-controller and pin-controller@e6060000. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7791.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 4d0c2ce59900..540c5b27b842 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -562,7 +562,7 @@ status = "disabled"; }; - pfc: pfc@e6060000 { + pfc: pin-controller@e6060000 { compatible = "renesas,pfc-r8a7791"; reg = <0 0xe6060000 0 0x250>; }; -- cgit v1.2.3 From 5506dc4a8ebc2258e01a536b025bad17b6828da8 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 26 Apr 2017 12:05:37 +0200 Subject: ARM: dts: r8a7793: update PFC node name to pin-controller The device trees for Renesas SoCs use either pfc or pin-controller as the node name for the PFC device. This patch is intended to take a step towards unifying the node name used as pin-controller which appears to be the more generic of the two and thus more in keeping with the DT specs. My analysis is that this is a user-visible change to the extent that kernel logs, and sysfs entries change from e6060000.pfc and pfc@e6060000 to e6060000.pin-controller and pin-controller@e6060000. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7793.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 4de6041d61f9..728b5bca5bdb 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -529,7 +529,7 @@ status = "disabled"; }; - pfc: pfc@e6060000 { + pfc: pin-controller@e6060000 { compatible = "renesas,pfc-r8a7793"; reg = <0 0xe6060000 0 0x250>; }; -- cgit v1.2.3 From c6a4b9442dec038e7f6d276ef91713a663921f09 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 26 Apr 2017 12:05:38 +0200 Subject: ARM: dts: sh73a0: update PFC node name to pin-controller The device trees for Renesas SoCs use either pfc or pin-controller as the node name for the PFC device. This patch is intended to take a step towards unifying the node name used as pin-controller which appears to be the more generic of the two and thus more in keeping with the DT specs. My analysis is that this is a user-visible change to the extent that kernel logs, and sysfs entries change from e6050000.pfc and pfc@e6050000 to e6050000.pin-controller and pin-controller@e6050000. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/sh73a0.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 6b01ab354e88..4ea5c5a16c57 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -444,7 +444,7 @@ status = "disabled"; }; - pfc: pfc@e6050000 { + pfc: pin-controller@e6050000 { compatible = "renesas,pfc-sh73a0"; reg = <0xe6050000 0x8000>, <0xe605801c 0x1c>; -- cgit v1.2.3 From 9907a4a00f6df0796d6e838c9dbf3ecce2ec4600 Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Fri, 28 Apr 2017 12:01:34 -0700 Subject: ARM: dts: r7s72100: add usb clocks to device tree This adds the USB0 and USB1 clocks to the device tree. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 0423996e4dcc..5cf53e9943af 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -144,9 +144,9 @@ #clock-cells = <1>; compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0xfcfe0430 4>; - clocks = <&b_clk>; - clock-indices = ; - clock-output-names = "ether"; + clocks = <&b_clk>, <&p1_clk>, <&p1_clk>; + clock-indices = ; + clock-output-names = "ether", "usb0", "usb1"; }; mstp8_clks: mstp8_clks@fcfe0434 { -- cgit v1.2.3 From e15ebbfa1febf16f1af42fcc6ffa7e267eb330ae Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 24 Apr 2017 17:26:32 +0200 Subject: ARM: dts: r8a7791: Add GyroADC clock and device node Add node for the GyroADC block and it's associated clock. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 540c5b27b842..b730c889a404 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -776,6 +776,15 @@ status = "disabled"; }; + adc: adc@e6e54000 { + compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc"; + reg = <0 0xe6e54000 0 64>; + clocks = <&mstp9_clks R8A7791_CLK_GYROADC>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + status = "disabled"; + }; + scif2: serial@e6e58000 { compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", "renesas,scif"; @@ -1425,13 +1434,15 @@ mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, + clocks = <&p_clk>, + <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; #clock-cells = <1>; clock-indices = < + R8A7791_CLK_GYROADC R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 @@ -1439,6 +1450,7 @@ R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 >; clock-output-names = + "gyroadc", "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; -- cgit v1.2.3 From 5cb275a9704c135e7d9a886c86796d1df0ed52cd Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 18 Apr 2017 14:55:38 +0900 Subject: ARM: dts: r8a7793: set maximum frequency for SDHI clocks Define the upper limit otherwise the driver cannot utilize max speeds. Signed-off-by: Simon Horman Acked-by: Wolfram Sang --- arch/arm/boot/dts/r8a7793.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 728b5bca5bdb..13b980f27bbc 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -542,6 +542,7 @@ dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -554,6 +555,7 @@ dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -566,6 +568,7 @@ dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; -- cgit v1.2.3 From 6d25a4182d797950aa757d92c30332587f4fa692 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 18 Apr 2017 14:55:39 +0900 Subject: ARM: dts: gose: Enable UHS-I SDR-50 and SDR-104 Add the "1v8" pinctrl state and sd-uhs-sdr50 property to SDHI{0,1,2}. And the sd-uhs-sdr104 property to SDHI0. Signed-off-by: Simon Horman Acked-by: Wolfram Sang --- arch/arm/boot/dts/r8a7793-gose.dts | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index 806c93f6ae8b..95e51b79c1d7 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -348,16 +348,37 @@ sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; }; sdhi1_pins: sd1 { groups = "sdhi1_data4", "sdhi1_ctrl"; function = "sdhi1"; + power-source = <3300>; + }; + + sdhi1_pins_uhs: sd1_uhs { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <1800>; }; sdhi2_pins: sd2 { groups = "sdhi2_data4", "sdhi2_ctrl"; function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; }; qspi_pins: qspi { @@ -416,33 +437,40 @@ &sdhi0 { pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi0>; vqmmc-supply = <&vccq_sdhi0>; cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + sd-uhs-sdr50; + sd-uhs-sdr104; status = "okay"; }; &sdhi1 { pinctrl-0 = <&sdhi1_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi1>; vqmmc-supply = <&vccq_sdhi1>; cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + sd-uhs-sdr50; status = "okay"; }; &sdhi2 { pinctrl-0 = <&sdhi2_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi2>; vqmmc-supply = <&vccq_sdhi2>; cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; + sd-uhs-sdr50; status = "okay"; }; -- cgit v1.2.3 From fbf6ad107fafc8f5541e2bab75c40998779d5831 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 26 Apr 2017 17:25:47 +0800 Subject: arm: dts: mt7623: add clock controller device nodes Add clock controller nodes for MT7623, including topckgen, infracfg, pericfg and apmixedsys. This patch also cleans up two oscillators that provide clocks for MT7623. Switch the uart clocks to the real ones while at it. Signed-off-by: John Crispin Signed-off-by: Sean Wang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 64 +++++++++++++++++++++++++++++++++++++------ 1 file changed, 55 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 402579ab70d2..b97b2babd0bb 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -14,6 +14,8 @@ #include #include +#include +#include #include "skeleton64.dtsi" / { @@ -53,16 +55,18 @@ #clock-cells = <0>; }; - rtc_clk: dummy32k { + rtc32k: oscillator@1 { compatible = "fixed-clock"; - clock-frequency = <32000>; #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "rtc32k"; }; - uart_clk: dummy26m { + clk26m: oscillator@0 { compatible = "fixed-clock"; - clock-frequency = <26000000>; #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; }; timer { @@ -74,6 +78,32 @@ ; }; + topckgen: syscon@10000000 { + compatible = "mediatek,mt7623-topckgen", + "mediatek,mt2701-topckgen", + "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt7623-infracfg", + "mediatek,mt2701-infracfg", + "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt7623-pericfg", + "mediatek,mt2701-pericfg", + "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt7623-wdt", "mediatek,mt6589-wdt"; @@ -85,7 +115,7 @@ "mediatek,mt6577-timer"; reg = <0 0x10008000 0 0x80>; interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; + clocks = <&system_clk>, <&rtc32k>; clock-names = "system-clk", "rtc-clk"; }; @@ -98,6 +128,14 @@ reg = <0 0x10200100 0 0x1c>; }; + apmixedsys: syscon@10209000 { + compatible = "mediatek,mt7623-apmixedsys", + "mediatek,mt2701-apmixedsys", + "syscon"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; + }; + gic: interrupt-controller@10211000 { compatible = "arm,cortex-a7-gic"; interrupt-controller; @@ -114,7 +152,9 @@ "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART0_SEL>, + <&pericfg CLK_PERI_UART0>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -123,7 +163,9 @@ "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART1_SEL>, + <&pericfg CLK_PERI_UART1>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -132,7 +174,9 @@ "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART2_SEL>, + <&pericfg CLK_PERI_UART2>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -141,7 +185,9 @@ "mediatek,mt6577-uart"; reg = <0 0x11005000 0 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART3_SEL>, + <&pericfg CLK_PERI_UART3>; + clock-names = "baud", "bus"; status = "disabled"; }; }; -- cgit v1.2.3 From 8bb656d957fa02a75d715d74f5464af7476d661f Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 26 Apr 2017 17:25:48 +0800 Subject: arm: dts: mt7623: add subsystem clock controller device nodes Add MT7623 subsystem clock controllers for hifsys and ethsys. Signed-off-by: John Crispin Signed-off-by: Sean Wang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index b97b2babd0bb..54cff6ad0611 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -190,4 +190,20 @@ clock-names = "baud", "bus"; status = "disabled"; }; + + hifsys: syscon@1a000000 { + compatible = "mediatek,mt7623-hifsys", + "mediatek,mt2701-hifsys", + "syscon"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + }; + + ethsys: syscon@1b000000 { + compatible = "mediatek,mt7623-ethsys", + "mediatek,mt2701-ethsys", + "syscon"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + }; }; -- cgit v1.2.3 From 608cc0c006e0b53712c6e339e642546feb1d4a64 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 26 Apr 2017 17:25:49 +0800 Subject: arm: dts: mt7623: add power domain controller device node Add power domain controller node (scpsys) for MT7623. Signed-off-by: John Crispin Signed-off-by: Sean Wang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 54cff6ad0611..adb23932c2ca 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include #include #include "skeleton64.dtsi" @@ -104,6 +105,19 @@ #reset-cells = <1>; }; + scpsys: scpsys@10006000 { + compatible = "mediatek,mt7623-scpsys", + "mediatek,mt2701-scpsys", + "syscon"; + #power-domain-cells = <1>; + reg = <0 0x10006000 0 0x1000>; + infracfg = <&infracfg>; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_MFG_SEL>, + <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "mm", "mfg", "ethif"; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt7623-wdt", "mediatek,mt6589-wdt"; -- cgit v1.2.3 From 7ed9672f885e4f9cc9688cb765fc6758888d9711 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 26 Apr 2017 17:25:51 +0800 Subject: arm: dts: mt7623: add pinctrl nodes to the mt7623 dtsi file Add pin controller node to the mt7623.dtsi file Signed-off-by: John Crispin Signed-off-by: Sean Wang Reviewed-by: Linus Walleij Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index adb23932c2ca..e77e242b3de1 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -15,7 +15,10 @@ #include #include #include +#include #include +#include +#include #include #include "skeleton64.dtsi" @@ -105,6 +108,26 @@ #reset-cells = <1>; }; + pio: pinctrl@10005000 { + compatible = "mediatek,mt7623-pinctrl", + "mediatek,mt2701-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl_a>; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + interrupts = , + ; + }; + + syscfg_pctl_a: syscfg@10005000 { + compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + scpsys: scpsys@10006000 { compatible = "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys", -- cgit v1.2.3 From cd294fb0f067003c44ff68d00810c0f9febd8ed2 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 26 Apr 2017 17:25:52 +0800 Subject: arm: dts: mt7623: add pmic wrapper nodes to the mt7623 dtsi file Add PMIC wrapper node to the mt7623.dtsi file which is necessary for the control of PMIC from Mediatek. Signed-off-by: John Crispin Signed-off-by: Sean Wang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index e77e242b3de1..1bc678691516 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -156,6 +156,19 @@ clock-names = "system-clk", "rtc-clk"; }; + pwrap: pwrap@1000d000 { + compatible = "mediatek,mt7623-pwrap", + "mediatek,mt2701-pwrap"; + reg = <0 0x1000d000 0 0x1000>; + reg-names = "pwrap"; + interrupts = ; + resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>; + reset-names = "pwrap"; + clocks = <&infracfg CLK_INFRA_PMICSPI>, + <&infracfg CLK_INFRA_PMICWRAP>; + clock-names = "spi", "wrap"; + }; + sysirq: interrupt-controller@10200100 { compatible = "mediatek,mt7623-sysirq", "mediatek,mt6577-sysirq"; -- cgit v1.2.3 From 076f87105a3b1197e43e74737ff3060dfea8050d Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 26 Apr 2017 17:25:53 +0800 Subject: arm: dts: mt7623: add i2c nodes to the mt7623.dtsi file Add I2C nodes to the mt7623.dtsi file. Signed-off-by: John Crispin Signed-off-by: Sean Wang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 1bc678691516..31a736410975 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -241,6 +241,51 @@ status = "disabled"; }; + i2c0: i2c@11007000 { + compatible = "mediatek,mt7623-i2c", + "mediatek,mt6577-i2c"; + reg = <0 0x11007000 0 0x70>, + <0 0x11000200 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C0>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt7623-i2c", + "mediatek,mt6577-i2c"; + reg = <0 0x11008000 0 0x70>, + <0 0x11000280 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C1>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt7623-i2c", + "mediatek,mt6577-i2c"; + reg = <0 0x11009000 0 0x70>, + <0 0x11000300 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C2>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + hifsys: syscon@1a000000 { compatible = "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", -- cgit v1.2.3 From 44893591ea863e183eb97df89bbfb37a33d824a0 Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Wed, 26 Apr 2017 17:25:54 +0800 Subject: arm: dts: mt7623: add spi nodes to the mt7623.dtsi file Add spi controller nodes to the mt7623.dtsi file Signed-off-by: John Crispin Signed-off-by: Sean Wang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 31a736410975..85b2d6d90a62 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -286,6 +286,48 @@ status = "disabled"; }; + spi0: spi@1100a000 { + compatible = "mediatek,mt7623-spi", + "mediatek,mt2701-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI0_SEL>, + <&pericfg CLK_PERI_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi1: spi@11016000 { + compatible = "mediatek,mt7623-spi", + "mediatek,mt2701-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11016000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI1_SEL>, + <&pericfg CLK_PERI_SPI1>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi2: spi@11017000 { + compatible = "mediatek,mt7623-spi", + "mediatek,mt2701-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11017000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI2_SEL>, + <&pericfg CLK_PERI_SPI2>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + hifsys: syscon@1a000000 { compatible = "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", -- cgit v1.2.3 From 1112db665677fb08bc34fe948b48d852bc71f11a Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 26 Apr 2017 17:25:55 +0800 Subject: arm: dts: mt7623: add nand nodes to the mt7623.dtsi file Add NAND/EEC nodes to the mt7623.dtsi file. Signed-off-by: John Crispin Signed-off-by: Sean Wang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 85b2d6d90a62..3da69863321b 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -328,6 +328,31 @@ status = "disabled"; }; + nandc: nfi@1100d000 { + compatible = "mediatek,mt7623-nfc", + "mediatek,mt2701-nfc"; + reg = <0 0x1100d000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; + clocks = <&pericfg CLK_PERI_NFI>, + <&pericfg CLK_PERI_NFI_PAD>; + clock-names = "nfi_clk", "pad_clk"; + status = "disabled"; + ecc-engine = <&bch>; + #address-cells = <1>; + #size-cells = <0>; + }; + + bch: ecc@1100e000 { + compatible = "mediatek,mt7623-ecc", + "mediatek,mt2701-ecc"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_NFI_ECC>; + clock-names = "nfiecc_clk"; + status = "disabled"; + }; + hifsys: syscon@1a000000 { compatible = "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", -- cgit v1.2.3 From ffa491c8df04f9a3989e0bba73843daba3b1a9c1 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 26 Apr 2017 17:25:56 +0800 Subject: arm: dts: mt7623: add mmc nodes to the mt7623.dtsi file Add e/MMC nodes to the mt7623.dtsi file. Signed-off-by: John Crispin Signed-off-by: Sean Wang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 3da69863321b..35ebaa7a166c 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -353,6 +353,28 @@ status = "disabled"; }; + mmc0: mmc@11230000 { + compatible = "mediatek,mt7623-mmc", + "mediatek,mt8135-mmc"; + reg = <0 0x11230000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_0>, + <&topckgen CLK_TOP_MSDC30_0_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt7623-mmc", + "mediatek,mt8135-mmc"; + reg = <0 0x11240000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_1>, + <&topckgen CLK_TOP_MSDC30_1_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + hifsys: syscon@1a000000 { compatible = "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", -- cgit v1.2.3 From 35fdd6c921b4ffa25eded3c1a51e93efd9df3ae5 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 26 Apr 2017 17:25:57 +0800 Subject: arm: dts: mt7623: add usb nodes to the mt7623.dtsi file Add USB nodes to the mt7623.dtsi file. Signed-off-by: John Crispin Signed-off-by: Sean Wang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 77 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 35ebaa7a166c..3ffa2275045c 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -375,12 +375,89 @@ status = "disabled"; }; + usb1: usb@1a1c0000 { + compatible = "mediatek,mt7623-xhci", + "mediatek,mt8173-xhci"; + reg = <0 0x1a1c0000 0 0x1000>, + <0 0x1a1c4700 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + clocks = <&hifsys CLK_HIFSYS_USB0PHY>, + <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "sys_ck", "free_ck"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + status = "disabled"; + }; + + u3phy1: usb-phy@1a1c4000 { + compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy"; + reg = <0 0x1a1c4000 0 0x0700>; + clocks = <&clk26m>; + clock-names = "u3phya_ref"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + u2port0: usb-phy@1a1c4800 { + reg = <0 0x1a1c4800 0 0x0100>; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: usb-phy@1a1c4900 { + reg = <0 0x1a1c4900 0 0x0700>; + #phy-cells = <1>; + status = "okay"; + }; + }; + + usb2: usb@1a240000 { + compatible = "mediatek,mt7623-xhci", + "mediatek,mt8173-xhci"; + reg = <0 0x1a240000 0 0x1000>, + <0 0x1a244700 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + clocks = <&hifsys CLK_HIFSYS_USB1PHY>, + <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "sys_ck", "free_ck"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; + phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; + status = "disabled"; + }; + + u3phy2: usb-phy@1a244000 { + compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy"; + reg = <0 0x1a244000 0 0x0700>; + clocks = <&clk26m>; + clock-names = "u3phya_ref"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + u2port1: usb-phy@1a244800 { + reg = <0 0x1a244800 0 0x0100>; + #phy-cells = <1>; + status = "okay"; + }; + + u3port1: usb-phy@1a244900 { + reg = <0 0x1a244900 0 0x0700>; + #phy-cells = <1>; + status = "okay"; + }; + }; + hifsys: syscon@1a000000 { compatible = "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", "syscon"; reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; ethsys: syscon@1b000000 { -- cgit v1.2.3 From ffdbc3cfc504245a883ed0ef49bfd3a913caf4b0 Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Wed, 26 Apr 2017 17:25:58 +0800 Subject: arm: dts: mt7623: add pwm nodes to the mt7623.dtsi file Add PWM nodes to the mt7623.dtsi file. Signed-off-by: Sean Wang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 3ffa2275045c..27823307d71e 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -241,6 +241,22 @@ status = "disabled"; }; + pwm: pwm@11006000 { + compatible = "mediatek,mt7623-pwm"; + reg = <0 0x11006000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&pericfg CLK_PERI_PWM>, + <&pericfg CLK_PERI_PWM1>, + <&pericfg CLK_PERI_PWM2>, + <&pericfg CLK_PERI_PWM3>, + <&pericfg CLK_PERI_PWM4>, + <&pericfg CLK_PERI_PWM5>; + clock-names = "top", "main", "pwm1", "pwm2", + "pwm3", "pwm4", "pwm5"; + status = "disabled"; + }; + i2c0: i2c@11007000 { compatible = "mediatek,mt7623-i2c", "mediatek,mt6577-i2c"; -- cgit v1.2.3 From 687976ae99823b76547f16dd3e767006244ec402 Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Wed, 26 Apr 2017 17:25:59 +0800 Subject: arm: dts: mt7623: add ethernet nodes to the mt7623.dtsi file Add ethernet nodes to the mt7623.dtsi file. Signed-off-by: Sean Wang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 27823307d71e..4d3011256470 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -483,4 +483,24 @@ reg = <0 0x1b000000 0 0x1000>; #clock-cells = <1>; }; + + eth: ethernet@1b100000 { + compatible = "mediatek,mt2701-eth", "syscon"; + reg = <0 0x1b100000 0 0x20000>; + interrupts = , + , + ; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <ðsys CLK_ETHSYS_ESW>, + <ðsys CLK_ETHSYS_GP1>, + <ðsys CLK_ETHSYS_GP2>, + <&apmixedsys CLK_APMIXED_TRGPLL>; + clock-names = "ethif", "esw", "gp1", "gp2", "trgpll"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; + mediatek,ethsys = <ðsys>; + mediatek,pctl = <&syscfg_pctl_a>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; -- cgit v1.2.3 From 465792e6f036402c6183316eaef0b0f3432ea481 Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Wed, 26 Apr 2017 17:26:00 +0800 Subject: arm: dts: mt7623: add crypto engine nodes to the mt7623.dtsi file Add crypto engine nodes to the mt7623.dtsi file. Signed-off-by: Sean Wang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 4d3011256470..f5b8eed27510 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -503,4 +503,19 @@ #size-cells = <0>; status = "disabled"; }; + + crypto: crypto@1b240000 { + compatible = "mediatek,mt7623-crypto"; + reg = <0 0x1b240000 0 0x20000>; + interrupts = , + , + , + , + ; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <ðsys CLK_ETHSYS_CRYPTO>; + clock-names = "ethif","cryp"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; + status = "disabled"; + }; }; -- cgit v1.2.3 From 91044f38dae78e95409855fdf30a88f771d7f20c Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Wed, 26 Apr 2017 17:26:01 +0800 Subject: arm: dts: mt7623: add ir nodes to the mt7623.dtsi file Add ir nodes to the mt7623.dtsi file. Signed-off-by: Sean Wang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index f5b8eed27510..95c6fca0738e 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -169,6 +169,15 @@ clock-names = "spi", "wrap"; }; + cir: cir@0x10013000 { + compatible = "mediatek,mt7623-cir"; + reg = <0 0x10013000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_IRRX>; + clock-names = "clk"; + status = "disabled"; + }; + sysirq: interrupt-controller@10200100 { compatible = "mediatek,mt7623-sysirq", "mediatek,mt6577-sysirq"; -- cgit v1.2.3 From 96c390a72d292d60d2fdc8880fb7dea64bb6ec13 Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Wed, 26 Apr 2017 17:26:02 +0800 Subject: arm: dts: mt7623: add afe nodes to the mt7623.dtsi file Add afe nodes to the mt7623.dtsi file. Which is the necessary node for I2S audio in/out. Signed-off-by: Sean Wang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 99 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 95c6fca0738e..5ed9821099c2 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -378,6 +378,105 @@ status = "disabled"; }; + afe: audio-controller@11220000 { + compatible = "mediatek,mt7623-audio", + "mediatek,mt2701-audio"; + reg = <0 0x11220000 0 0x2000>, + <0 0x112a0000 0 0x20000>; + interrupts = ; + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; + + clocks = <&infracfg CLK_INFRA_AUDIO>, + <&topckgen CLK_TOP_AUD_MUX1_SEL>, + <&topckgen CLK_TOP_AUD_MUX2_SEL>, + <&topckgen CLK_TOP_AUD_MUX1_DIV>, + <&topckgen CLK_TOP_AUD_MUX2_DIV>, + <&topckgen CLK_TOP_AUD_48K_TIMING>, + <&topckgen CLK_TOP_AUD_44K_TIMING>, + <&topckgen CLK_TOP_AUDPLL_MUX_SEL>, + <&topckgen CLK_TOP_APLL_SEL>, + <&topckgen CLK_TOP_AUD1PLL_98M>, + <&topckgen CLK_TOP_AUD2PLL_90M>, + <&topckgen CLK_TOP_HADDS2PLL_98M>, + <&topckgen CLK_TOP_HADDS2PLL_294M>, + <&topckgen CLK_TOP_AUDPLL>, + <&topckgen CLK_TOP_AUDPLL_D4>, + <&topckgen CLK_TOP_AUDPLL_D8>, + <&topckgen CLK_TOP_AUDPLL_D16>, + <&topckgen CLK_TOP_AUDPLL_D24>, + <&topckgen CLK_TOP_AUDINTBUS_SEL>, + <&clk26m>, + <&topckgen CLK_TOP_SYSPLL1_D4>, + <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K5_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K6_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K5_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K6_SRC_DIV>, + <&topckgen CLK_TOP_AUD_I2S1_MCLK>, + <&topckgen CLK_TOP_AUD_I2S2_MCLK>, + <&topckgen CLK_TOP_AUD_I2S3_MCLK>, + <&topckgen CLK_TOP_AUD_I2S4_MCLK>, + <&topckgen CLK_TOP_AUD_I2S5_MCLK>, + <&topckgen CLK_TOP_AUD_I2S6_MCLK>, + <&topckgen CLK_TOP_ASM_M_SEL>, + <&topckgen CLK_TOP_ASM_H_SEL>, + <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_UNIVPLL2_D2>, + <&topckgen CLK_TOP_SYSPLL_D5>; + + clock-names = "infra_sys_audio_clk", + "top_audio_mux1_sel", + "top_audio_mux2_sel", + "top_audio_mux1_div", + "top_audio_mux2_div", + "top_audio_48k_timing", + "top_audio_44k_timing", + "top_audpll_mux_sel", + "top_apll_sel", + "top_aud1_pll_98M", + "top_aud2_pll_90M", + "top_hadds2_pll_98M", + "top_hadds2_pll_294M", + "top_audpll", + "top_audpll_d4", + "top_audpll_d8", + "top_audpll_d16", + "top_audpll_d24", + "top_audintbus_sel", + "clk_26m", + "top_syspll1_d4", + "top_aud_k1_src_sel", + "top_aud_k2_src_sel", + "top_aud_k3_src_sel", + "top_aud_k4_src_sel", + "top_aud_k5_src_sel", + "top_aud_k6_src_sel", + "top_aud_k1_src_div", + "top_aud_k2_src_div", + "top_aud_k3_src_div", + "top_aud_k4_src_div", + "top_aud_k5_src_div", + "top_aud_k6_src_div", + "top_aud_i2s1_mclk", + "top_aud_i2s2_mclk", + "top_aud_i2s3_mclk", + "top_aud_i2s4_mclk", + "top_aud_i2s5_mclk", + "top_aud_i2s6_mclk", + "top_asm_m_sel", + "top_asm_h_sel", + "top_univpll2_d4", + "top_univpll2_d2", + "top_syspll_d5"; + }; + mmc0: mmc@11230000 { compatible = "mediatek,mt7623-mmc", "mediatek,mt8135-mmc"; -- cgit v1.2.3 From 88b43a7b179859ef49797cbac902106d243a6373 Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Wed, 26 Apr 2017 17:26:03 +0800 Subject: arm: dts: mt7623: add rng nodes to the mt7623.dtsi file Add rng nodes to the mt7623.dtsi file. Signed-off-by: Sean Wang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 5ed9821099c2..c21e19c8faba 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -195,6 +195,13 @@ #clock-cells = <1>; }; + rng: rng@1020f000 { + compatible = "mediatek,mt7623-rng"; + reg = <0 0x1020f000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_TRNG>; + clock-names = "rng"; + }; + gic: interrupt-controller@10211000 { compatible = "arm,cortex-a7-gic"; interrupt-controller; -- cgit v1.2.3 From 38b244b5da7377638fc24a8a637875ed03426236 Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Wed, 26 Apr 2017 17:26:04 +0800 Subject: arm: dts: mt7623: add auxadc nodes to the mt7623.dtsi file Add auxadc nodes to the mt7623.dtsi file. Signed-off-by: Sean Wang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index c21e19c8faba..25fb19bd2551 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -213,6 +213,15 @@ <0 0x10216000 0 0x2000>; }; + auxadc: adc@11001000 { + compatible = "mediatek,mt7623-auxadc", + "mediatek,mt2701-auxadc"; + reg = <0 0x11001000 0 0x1000>; + clocks = <&pericfg CLK_PERI_AUXADC>; + clock-names = "main"; + #io-channel-cells = <1>; + }; + uart0: serial@11002000 { compatible = "mediatek,mt7623-uart", "mediatek,mt6577-uart"; -- cgit v1.2.3 From 43c7a91b4b3a83e1f6f83c014cbede33a066a71f Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Wed, 26 Apr 2017 17:26:05 +0800 Subject: arm: dts: mt7623: add efuse nodes to the mt7623.dtsi file Add efuse nodes to the mt7623.dtsi file. Signed-off-by: Sean Wang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 25fb19bd2551..409d4d59cb63 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -187,6 +187,17 @@ reg = <0 0x10200100 0 0x1c>; }; + efuse: efuse@10206000 { + compatible = "mediatek,mt7623-efuse", + "mediatek,mt8173-efuse"; + reg = <0 0x10206000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + thermal_calibration_data: calib@424 { + reg = <0x424 0xc>; + }; + }; + apmixedsys: syscon@10209000 { compatible = "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys", -- cgit v1.2.3 From 9794a090d4931519155518e760eef3d4d6df9e5d Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Wed, 26 Apr 2017 17:26:06 +0800 Subject: arm: dts: mt7623: add thermal nodes to the mt7623.dtsi file Add thermal nodes to the mt7623.dtsi file. Signed-off-by: Sean Wang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 409d4d59cb63..8271903a3746 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -352,6 +352,22 @@ status = "disabled"; }; + thermal: thermal@1100b000 { + #thermal-sensor-cells = <1>; + compatible = "mediatek,mt7623-thermal", + "mediatek,mt2701-thermal"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; + clock-names = "therm", "auxadc"; + resets = <&pericfg MT2701_PERI_THERM_SW_RST>; + reset-names = "therm"; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + nvmem-cells = <&thermal_calibration_data>; + nvmem-cell-names = "calibration-data"; + }; + spi1: spi@11016000 { compatible = "mediatek,mt7623-spi", "mediatek,mt2701-spi"; -- cgit v1.2.3 From d4c794f30a9eac901356e809aa38d605333154c1 Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Wed, 26 Apr 2017 17:26:07 +0800 Subject: arm: dts: mt7623: add Sean as one of authors for mt7623.dtsi files Add Sean as one of the authors for the mt7623.dtsi Signed-off-by: Sean Wang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 8271903a3746..0d0cbeadc1d6 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -1,6 +1,7 @@ /* - * Copyright (c) 2016 MediaTek Inc. + * Copyright (c) 2017 MediaTek Inc. * Author: John Crispin + * Sean Wang * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as -- cgit v1.2.3 From 1b813f3ca8755b478a20355c21516d2a077f7431 Mon Sep 17 00:00:00 2001 From: Youlin Pei Date: Fri, 7 Apr 2017 16:06:37 +0800 Subject: ARM: dts: mt2701: Add mtk-cirq node for mt2701 This commit add mtk-cirq node to mt2701 dtsi. Signed-off-by: Youlin Pei Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt2701.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 803721050116..5daacfe05ea6 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -22,7 +22,7 @@ / { compatible = "mediatek,mt2701"; - interrupt-parent = <&sysirq>; + interrupt-parent = <&cirq>; cpus { #address-cells = <1>; @@ -210,6 +210,16 @@ reg = <0 0x10200100 0 0x1c>; }; + cirq: interrupt-controller@10204000 { + compatible = "mediatek,mt2701-cirq", + "mediatek,mtk-cirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&sysirq>; + reg = <0 0x10204000 0 0x400>; + mediatek,ext-irq-range = <32 200>; + }; + iommu: mmsys_iommu@10205000 { compatible = "mediatek,mt2701-m4u"; reg = <0 0x10205000 0 0x1000>; -- cgit v1.2.3 From df3074f06ffc038c3f24dd5ed7d366f3a25240b2 Mon Sep 17 00:00:00 2001 From: Guochun Mao Date: Wed, 25 Jan 2017 11:38:35 +0800 Subject: arm: dts: mt2701: add nor flash node Add Mediatek nor flash node. Signed-off-by: Guochun Mao Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt2701-evb.dts | 25 +++++++++++++++++++++++++ arch/arm/boot/dts/mt2701.dtsi | 12 ++++++++++++ 2 files changed, 37 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts index a4837985b7a7..0474fd2d602b 100644 --- a/arch/arm/boot/dts/mt2701-evb.dts +++ b/arch/arm/boot/dts/mt2701-evb.dts @@ -78,6 +78,31 @@ status = "disabled"; }; +&nor_flash { + pinctrl-names = "default"; + pinctrl-0 = <&nor_pins_default>; + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + }; +}; + +&pio { + nor_pins_default: nor { + pins1 { + pinmux = , + , + , + , + , + ; + drive-strength = ; + bias-pull-up; + }; + }; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 5daacfe05ea6..18a851b266d4 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -344,6 +344,18 @@ status = "disabled"; }; + nor_flash: spi@11014000 { + compatible = "mediatek,mt2701-nor", + "mediatek,mt8173-nor"; + reg = <0 0x11014000 0 0xe0>; + clocks = <&pericfg CLK_PERI_FLASH>, + <&topckgen CLK_TOP_FLASH_SEL>; + clock-names = "spi", "sf"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spi1: spi@11016000 { compatible = "mediatek,mt2701-spi"; #address-cells = <1>; -- cgit v1.2.3 From 8378be878a5dd66cdad8bf06fd01396c532159e6 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Mon, 15 May 2017 16:39:58 +0800 Subject: ARM: sun8i: v3s: restore the usage of CCU definitions All the used CCU definitions are stripped from the V3s DTSI file when it's merged, as the DTSI file and the CCU device tree binding headers went to different trees. As they're all in Linus's tree now, restore the usage of the definitions. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-v3s.dtsi | 64 +++++++++++++++++++++------------------- 1 file changed, 33 insertions(+), 31 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 71075969e5e6..3b50fa580261 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -41,6 +41,8 @@ */ #include +#include +#include / { #address-cells = <1>; @@ -55,7 +57,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; - clocks = <&ccu 14>; + clocks = <&ccu CLK_CPU>; }; }; @@ -96,15 +98,15 @@ mmc0: mmc@01c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; - clocks = <&ccu 22>, - <&ccu 45>, - <&ccu 47>, - <&ccu 46>; + clocks = <&ccu CLK_BUS_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ccu 7>; + resets = <&ccu RST_BUS_MMC0>; reset-names = "ahb"; interrupts = ; status = "disabled"; @@ -115,15 +117,15 @@ mmc1: mmc@01c10000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; - clocks = <&ccu 23>, - <&ccu 48>, - <&ccu 50>, - <&ccu 49>; + clocks = <&ccu CLK_BUS_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ccu 8>; + resets = <&ccu RST_BUS_MMC1>; reset-names = "ahb"; interrupts = ; status = "disabled"; @@ -134,15 +136,15 @@ mmc2: mmc@01c11000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; - clocks = <&ccu 24>, - <&ccu 51>, - <&ccu 53>, - <&ccu 52>; + clocks = <&ccu CLK_BUS_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ccu 9>; + resets = <&ccu RST_BUS_MMC2>; reset-names = "ahb"; interrupts = ; status = "disabled"; @@ -153,8 +155,8 @@ usb_otg: usb@01c19000 { compatible = "allwinner,sun8i-h3-musb"; reg = <0x01c19000 0x0400>; - clocks = <&ccu 29>; - resets = <&ccu 17>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; interrupts = ; interrupt-names = "mc"; phys = <&usbphy 0>; @@ -169,9 +171,9 @@ <0x01c1a800 0x4>; reg-names = "phy_ctrl", "pmu0"; - clocks = <&ccu 56>; + clocks = <&ccu CLK_USB_PHY0>; clock-names = "usb0_phy"; - resets = <&ccu 0>; + resets = <&ccu RST_USB_PHY0>; reset-names = "usb0_reset"; status = "disabled"; #phy-cells = <1>; @@ -198,7 +200,7 @@ reg = <0x01c20800 0x400>; interrupts = , ; - clocks = <&ccu 37>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; @@ -244,8 +246,8 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 40>; - resets = <&ccu 49>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; status = "disabled"; }; @@ -255,8 +257,8 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 41>; - resets = <&ccu 50>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; status = "disabled"; }; @@ -266,8 +268,8 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 42>; - resets = <&ccu 51>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; status = "disabled"; }; @@ -275,8 +277,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = ; - clocks = <&ccu 38>; - resets = <&ccu 46>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; status = "disabled"; @@ -288,8 +290,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = ; - clocks = <&ccu 39>; - resets = <&ccu 47>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 37eac4f9c6e819238fd8d02e9597b1d15e23b6e1 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Mon, 15 May 2017 16:39:59 +0800 Subject: ARM: sun8i: v3s: add LRADC device node Allwinner V3s features a LRADC like the ones in older SoCs. Add a device tree node for it. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-v3s.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 3b50fa580261..b9a3df941fb4 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -240,6 +240,13 @@ interrupts = ; }; + lradc: lradc@1c22800 { + compatible = "allwinner,sun4i-a10-lradc-keys"; + reg = <0x01c22800 0x400>; + interrupts = ; + status = "disabled"; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; -- cgit v1.2.3 From be3c1392b3b7a0243a5a4bf3ae6fe42ee983974d Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Mon, 15 May 2017 16:40:00 +0800 Subject: ARM: sun8i: v3s: add pinmux for mmc1 The dock board of Lichee Pi Zero features a MicroSD slot on MMC1, which can be used with a MicroSD card or the MicroSD-slot Wi-Fi card provided by Lichee Pi Zero. Add pinmux for the mmc1 controller, and specify it in the mmc1 device node as it's the only pinmux for mmc1. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-v3s.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index b9a3df941fb4..6ff50665e5e6 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -128,6 +128,8 @@ resets = <&ccu RST_BUS_MMC1>; reset-names = "ahb"; interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -224,6 +226,14 @@ drive-strength = <30>; bias-pull-up; }; + + mmc1_pins: mmc1 { + pins = "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; }; timer@01c20c00 { -- cgit v1.2.3 From 2ae0fcc57e00c11fae80678e2a9fabbeec82a185 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 14 May 2017 02:16:18 +0300 Subject: ARM: dts: renesas: Switch to panel-lvds bindings for Mitsubishi panels The aa104xd12 and aa121td01 panels are LVDS panels, not DPI panels. Use the correct DT bindings. Signed-off-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi | 3 ++- arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi b/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi index 65cb50f0c29f..238d14bb0ebe 100644 --- a/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi +++ b/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi @@ -10,10 +10,11 @@ / { panel { - compatible = "mitsubishi,aa104xd12", "panel-dpi"; + compatible = "mitsubishi,aa104xd12", "panel-lvds"; width-mm = <210>; height-mm = <158>; + data-mapping = "jeida-18"; panel-timing { /* 1024x768 @65Hz */ diff --git a/arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi b/arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi index a07ebf8f6938..04aafd479775 100644 --- a/arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi +++ b/arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi @@ -10,10 +10,11 @@ / { panel { - compatible = "mitsubishi,aa121td01", "panel-dpi"; + compatible = "mitsubishi,aa121td01", "panel-lvds"; width-mm = <261>; height-mm = <163>; + data-mapping = "jeida-18"; panel-timing { /* 1280x800 @60Hz */ -- cgit v1.2.3 From 43c3a448b3570654876eb5a111e94356dcbde37e Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 13 Apr 2017 22:04:29 -0300 Subject: ARM: dts: at91: Add generic compatible string for I2C EEPROM The at24 driver allows to register I2C EEPROM chips using different vendor and devices, but the I2C subsystem does not take the vendor into account when matching using the I2C table since it only has device entries. But when matching using an OF table, both the vendor and device has to be taken into account so the driver defines only a set of compatible strings using the "atmel" vendor as a generic fallback for compatible I2C devices. So add this generic fallback to the device node compatible string to make the device to match the driver using the OF device ID table. Signed-off-by: Javier Martinez Canillas Acked-by: Peter Rosin Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-linea.dtsi | 2 +- arch/arm/boot/dts/at91-tse850-3.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-linea.dtsi b/arch/arm/boot/dts/at91-linea.dtsi index 0721c8472509..9bf9aaeff3e8 100644 --- a/arch/arm/boot/dts/at91-linea.dtsi +++ b/arch/arm/boot/dts/at91-linea.dtsi @@ -31,7 +31,7 @@ status = "okay"; eeprom@51 { - compatible = "st,24c64"; + compatible = "st,24c64", "atmel,24c64"; reg = <0x51>; pagesize = <32>; }; diff --git a/arch/arm/boot/dts/at91-tse850-3.dts b/arch/arm/boot/dts/at91-tse850-3.dts index 498fba3e52b5..a5c0dd630253 100644 --- a/arch/arm/boot/dts/at91-tse850-3.dts +++ b/arch/arm/boot/dts/at91-tse850-3.dts @@ -239,7 +239,7 @@ }; eeprom@50 { - compatible = "nxp,24c02"; + compatible = "nxp,24c02", "atmel,24c02"; reg = <0x50>; pagesize = <16>; }; -- cgit v1.2.3 From bc6d5d7666b73cbd8d6ed6ee3aece84903fffe0b Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Mon, 24 Apr 2017 09:12:17 +0800 Subject: ARM: dts: at91: sama5d2: add m_can nodes Add nodes to support the Controller Area Network(M_CAN) on SAMA5D2. The version of M_CAN IP core is 3.1.0 (CREL = 0x31040730). As said in SAMA5D2 datasheet, the CAN clock is recommended to use frequencies of 20, 40 or 80 MHz. To achieve these frequencies, PMC GCLK3 must select the UPLLCK(480 MHz) as source clock and divide by 24, 12, or 6. So, the "assigned-clock-rates" property has three options: 20000000, 40000000, and 80000000. The "assigned-clock-parents" property should be referred to utmi fixedly. The MSBs [bits 31:16] of the CAN Message RAM for CAN0 and CAN1 are default configured in 0x00200000. To avoid conflict with SRAM map for PM, change them to 0x00210000 in the AT91Bootstrap via setting the CAN Memories Address-based Register(SFR_CAN) of SFR. Signed-off-by: Wenyou Yang Tested-by: Quentin Schulz Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 24 +++++++++++++ arch/arm/boot/dts/sama5d2.dtsi | 56 +++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index 0bef9e0b89c6..37de94fc9b5a 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -258,6 +258,12 @@ status = "okay"; }; + can0: can@f8054000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_default>; + status = "okay"; + }; + uart3: serial@fc008000 { atmel,use-dma-rx; atmel,use-dma-tx; @@ -322,6 +328,18 @@ bias-disable; }; + pinctrl_can0_default: can0_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_can1_default: can1_default { + pinmux = , + ; + bias-disable; + }; + pinctrl_charger_chglev: charger_chglev { pinmux = ; bias-disable; @@ -469,6 +487,12 @@ }; }; + + can1: can@fc050000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; + status = "okay"; + }; }; }; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 8067c71c3a38..ce95dcb8bdf9 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -762,6 +762,18 @@ atmel,clk-output-range = <0 83000000>; }; + can0_clk: can0_clk { + #clock-cells = <0>; + reg = <56>; + atmel,clk-output-range = <0 83000000>; + }; + + can1_clk: can1_clk { + #clock-cells = <0>; + reg = <57>; + atmel,clk-output-range = <0 83000000>; + }; + classd_clk: classd_clk { #clock-cells = <0>; reg = <59>; @@ -890,6 +902,18 @@ #clock-cells = <0>; reg = <55>; }; + + can0_gclk: can0_gclk { + #clock-cells = <0>; + reg = <56>; + atmel,clk-output-range = <0 80000000>; + }; + + can1_gclk: can1_gclk { + #clock-cells = <0>; + reg = <57>; + atmel,clk-output-range = <0 80000000>; + }; }; }; @@ -1144,6 +1168,22 @@ clocks = <&clk32k>; }; + can0: can@f8054000 { + compatible = "bosch,m_can"; + reg = <0xf8054000 0x4000>, <0x210000 0x4000>; + reg-names = "m_can", "message_ram"; + interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>, + <64 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-names = "int0", "int1"; + clocks = <&can0_clk>, <&can0_gclk>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&can0_gclk>; + assigned-clock-parents = <&utmi>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; + status = "disabled"; + }; + spi1: spi@fc000000 { compatible = "atmel,at91rm9200-spi"; reg = <0xfc000000 0x100>; @@ -1305,6 +1345,22 @@ status = "okay"; }; + can1: can@fc050000 { + compatible = "bosch,m_can"; + reg = <0xfc050000 0x4000>, <0x210000 0x4000>; + reg-names = "m_can", "message_ram"; + interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>, + <65 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-names = "int0", "int1"; + clocks = <&can1_clk>, <&can1_gclk>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&can1_gclk>; + assigned-clock-parents = <&utmi>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>; + status = "disabled"; + }; + sfrbu: sfr@fc05c000 { compatible = "atmel,sama5d2-sfrbu", "syscon"; reg = <0xfc05c000 0x20>; -- cgit v1.2.3 From d72ea669fb9db51385d02cb2fe6ca484010259ac Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 5 May 2017 10:43:42 +0200 Subject: ARM: configs: at91: make system tickless when idle This makes Atmel sama5 platforms' system tickless when idle. Signed-off-by: Quentin Schulz Signed-off-by: Alexandre Belloni --- arch/arm/configs/sama5_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index 777c9e986425..2e1f096c96cb 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -3,6 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_FHANDLE=y CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_NO_HZ_IDLE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_CGROUPS=y CONFIG_BLK_DEV_INITRD=y -- cgit v1.2.3 From 60610a996177ddd561774b3ec732e09b94acadae Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 5 May 2017 10:43:43 +0200 Subject: ARM: configs: at91: enable HIGH_RES_TIMERS This enables by default the high resolution timers on sama5d2 platforms. Signed-off-by: Quentin Schulz Signed-off-by: Alexandre Belloni --- arch/arm/configs/sama5_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index 2e1f096c96cb..4c914da669ea 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -4,6 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_FHANDLE=y CONFIG_IRQ_DOMAIN_DEBUG=y CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_CGROUPS=y CONFIG_BLK_DEV_INITRD=y -- cgit v1.2.3 From 24a0f5c539f944248cbb2e3502830dcb7fd2a96e Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 27 Sep 2016 12:29:50 +0200 Subject: ARM: at91: pm: Add sama5d2 backup mode The sama5d2 has a mode were it is possible to cut power to the SoC while keeping the RAM in self refresh. Resuming from that mode needs support in the firmware/bootloader. Signed-off-by: Alexandre Belloni Acked-by: Wenyou Yang --- arch/arm/mach-at91/generic.h | 2 + arch/arm/mach-at91/pm.c | 109 ++++++++++++++++++++++++++++++++++- arch/arm/mach-at91/pm.h | 4 ++ arch/arm/mach-at91/pm_data-offsets.c | 3 + arch/arm/mach-at91/pm_suspend.S | 73 +++++++++++++++++------ arch/arm/mach-at91/sama5.c | 19 +++++- 6 files changed, 187 insertions(+), 23 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index f1ead0f13c19..e2bd17237964 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -15,10 +15,12 @@ extern void __init at91rm9200_pm_init(void); extern void __init at91sam9_pm_init(void); extern void __init sama5_pm_init(void); +extern void __init sama5d2_pm_init(void); #else static inline void __init at91rm9200_pm_init(void) { } static inline void __init at91sam9_pm_init(void) { } static inline void __init sama5_pm_init(void) { } +static inline void __init sama5d2_pm_init(void) { } #endif #endif /* _AT91_GENERIC_H */ diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 2cd27c830ab6..d138d19fa9f0 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "generic.h" #include "pm.h" @@ -58,6 +59,14 @@ static int at91_pm_valid_state(suspend_state_t state) } } +static int canary = 0xA5A5A5A5; + +static struct at91_pm_bu { + int suspended; + unsigned long reserved; + phys_addr_t canary; + phys_addr_t resume; +} *pm_bu; static suspend_state_t target_state; @@ -123,15 +132,39 @@ static void (*at91_suspend_sram_fn)(struct at91_pm_data *); extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data); extern u32 at91_pm_suspend_in_sram_sz; -static void at91_pm_suspend(suspend_state_t state) +static int at91_suspend_finish(unsigned long val) { - pm_data.mode = (state == PM_SUSPEND_MEM) ? AT91_PM_SLOW_CLOCK : 0; - flush_cache_all(); outer_disable(); at91_suspend_sram_fn(&pm_data); + return 0; +} + +static void at91_pm_suspend(suspend_state_t state) +{ + if (pm_data.deepest_state == AT91_PM_BACKUP) + if (state == PM_SUSPEND_MEM) + pm_data.mode = AT91_PM_BACKUP; + else + pm_data.mode = AT91_PM_SLOW_CLOCK; + else + pm_data.mode = (state == PM_SUSPEND_MEM) ? AT91_PM_SLOW_CLOCK : 0; + + if (pm_data.mode == AT91_PM_BACKUP) { + pm_bu->suspended = 1; + + cpu_suspend(0, at91_suspend_finish); + + /* The SRAM is lost between suspend cycles */ + at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, + &at91_pm_suspend_in_sram, + at91_pm_suspend_in_sram_sz); + } else { + at91_suspend_finish(0); + } + outer_resume(); } @@ -436,6 +469,70 @@ static void __init at91_pm_sram_init(void) &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz); } +static void __init at91_pm_backup_init(void) +{ + struct gen_pool *sram_pool; + struct device_node *np; + struct platform_device *pdev = NULL; + + pm_bu = NULL; + + np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-shdwc"); + if (!np) { + pr_warn("%s: failed to find shdwc!\n", __func__); + return; + } + + pm_data.shdwc = of_iomap(np, 0); + of_node_put(np); + + np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu"); + if (!np) { + pr_warn("%s: failed to find sfrbu!\n", __func__); + goto sfrbu_fail; + } + + pm_data.sfrbu = of_iomap(np, 0); + of_node_put(np); + pm_bu = NULL; + + np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam"); + if (!np) + goto securam_fail; + + pdev = of_find_device_by_node(np); + of_node_put(np); + if (!pdev) { + pr_warn("%s: failed to find securam device!\n", __func__); + goto securam_fail; + } + + sram_pool = gen_pool_get(&pdev->dev, NULL); + if (!sram_pool) { + pr_warn("%s: securam pool unavailable!\n", __func__); + goto securam_fail; + } + + pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu)); + if (!pm_bu) { + pr_warn("%s: unable to alloc securam!\n", __func__); + goto securam_fail; + } + + pm_bu->suspended = 0; + pm_bu->canary = virt_to_phys(&canary); + pm_bu->resume = virt_to_phys(cpu_resume); + + return; + +sfrbu_fail: + iounmap(pm_data.shdwc); + pm_data.shdwc = NULL; +securam_fail: + iounmap(pm_data.sfrbu); + pm_data.sfrbu = NULL; +} + struct pmc_info { unsigned long uhp_udp_mask; }; @@ -510,3 +607,9 @@ void __init sama5_pm_init(void) at91_dt_ramc(); at91_pm_init(NULL); } + +void __init sama5d2_pm_init(void) +{ + at91_pm_backup_init(); + sama5_pm_init(); +} diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index fc0f7d048187..d9c6612ef62f 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -22,6 +22,7 @@ #define AT91_MEMCTRL_DDRSDR 2 #define AT91_PM_SLOW_CLOCK 0x01 +#define AT91_PM_BACKUP 0x02 #ifndef __ASSEMBLY__ struct at91_pm_data { @@ -30,6 +31,9 @@ struct at91_pm_data { unsigned long uhp_udp_mask; unsigned int memctrl; unsigned int mode; + void __iomem *shdwc; + void __iomem *sfrbu; + unsigned int deepest_state; }; #endif diff --git a/arch/arm/mach-at91/pm_data-offsets.c b/arch/arm/mach-at91/pm_data-offsets.c index 30302cb16df0..c0a73e62b725 100644 --- a/arch/arm/mach-at91/pm_data-offsets.c +++ b/arch/arm/mach-at91/pm_data-offsets.c @@ -9,5 +9,8 @@ int main(void) DEFINE(PM_DATA_RAMC1, offsetof(struct at91_pm_data, ramc[1])); DEFINE(PM_DATA_MEMCTRL, offsetof(struct at91_pm_data, memctrl)); DEFINE(PM_DATA_MODE, offsetof(struct at91_pm_data, mode)); + DEFINE(PM_DATA_SHDWC, offsetof(struct at91_pm_data, shdwc)); + DEFINE(PM_DATA_SFRBU, offsetof(struct at91_pm_data, sfrbu)); + return 0; } diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S index 96781daa671a..daca91feea6a 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -97,15 +97,61 @@ ENTRY(at91_pm_suspend_in_sram) str tmp1, .memtype ldr tmp1, [r0, #PM_DATA_MODE] str tmp1, .pm_mode + /* Both ldrne below are here to preload their address in the TLB */ + ldr tmp1, [r0, #PM_DATA_SHDWC] + str tmp1, .shdwc + cmp tmp1, #0 + ldrne tmp2, [tmp1, #0] + ldr tmp1, [r0, #PM_DATA_SFRBU] + str tmp1, .sfr + cmp tmp1, #0 + ldrne tmp2, [tmp1, #0x10] /* Active the self-refresh mode */ mov r0, #SRAMC_SELF_FRESH_ACTIVE bl at91_sramc_self_refresh ldr r0, .pm_mode - tst r0, #AT91_PM_SLOW_CLOCK - beq skip_disable_main_clock + cmp r0, #AT91_PM_SLOW_CLOCK + beq slow_clock + cmp r0, #AT91_PM_BACKUP + beq backup_mode + /* Wait for interrupt */ + ldr pmc, .pmc_base + at91_cpu_idle + b exit_suspend + +slow_clock: + bl at91_slowck_mode + b exit_suspend +backup_mode: + bl at91_backup_mode + b exit_suspend + +exit_suspend: + /* Exit the self-refresh mode */ + mov r0, #SRAMC_SELF_FRESH_EXIT + bl at91_sramc_self_refresh + + /* Restore registers, and return */ + ldmfd sp!, {r4 - r12, pc} +ENDPROC(at91_pm_suspend_in_sram) + +ENTRY(at91_backup_mode) + /*BUMEN*/ + ldr r0, .sfr + mov tmp1, #0x1 + str tmp1, [r0, #0x10] + + /* Shutdown */ + ldr r0, .shdwc + mov tmp1, #0xA5000000 + add tmp1, tmp1, #0x1 + str tmp1, [r0, #0] +ENDPROC(at91_backup_mode) + +ENTRY(at91_slowck_mode) ldr pmc, .pmc_base /* Save Master clock setting */ @@ -134,18 +180,9 @@ ENTRY(at91_pm_suspend_in_sram) orr tmp1, tmp1, #AT91_PMC_KEY str tmp1, [pmc, #AT91_CKGR_MOR] -skip_disable_main_clock: - ldr pmc, .pmc_base - /* Wait for interrupt */ at91_cpu_idle - ldr r0, .pm_mode - tst r0, #AT91_PM_SLOW_CLOCK - beq skip_enable_main_clock - - ldr pmc, .pmc_base - /* Turn on the main oscillator */ ldr tmp1, [pmc, #AT91_CKGR_MOR] orr tmp1, tmp1, #AT91_PMC_MOSCEN @@ -174,14 +211,8 @@ skip_disable_main_clock: wait_mckrdy -skip_enable_main_clock: - /* Exit the self-refresh mode */ - mov r0, #SRAMC_SELF_FRESH_EXIT - bl at91_sramc_self_refresh - - /* Restore registers, and return */ - ldmfd sp!, {r4 - r12, pc} -ENDPROC(at91_pm_suspend_in_sram) + mov pc, lr +ENDPROC(at91_slowck_mode) /* * void at91_sramc_self_refresh(unsigned int is_active) @@ -314,6 +345,10 @@ ENDPROC(at91_sramc_self_refresh) .word 0 .sramc1_base: .word 0 +.shdwc: + .word 0 +.sfr: + .word 0 .memtype: .word 0 .pm_mode: diff --git a/arch/arm/mach-at91/sama5.c b/arch/arm/mach-at91/sama5.c index 6d157d0ead8e..3d0bf95a56ae 100644 --- a/arch/arm/mach-at91/sama5.c +++ b/arch/arm/mach-at91/sama5.c @@ -34,7 +34,6 @@ DT_MACHINE_START(sama5_dt, "Atmel SAMA5") MACHINE_END static const char *const sama5_alt_dt_board_compat[] __initconst = { - "atmel,sama5d2", "atmel,sama5d4", NULL }; @@ -45,3 +44,21 @@ DT_MACHINE_START(sama5_alt_dt, "Atmel SAMA5") .dt_compat = sama5_alt_dt_board_compat, .l2c_aux_mask = ~0UL, MACHINE_END + +static void __init sama5d2_init(void) +{ + of_platform_default_populate(NULL, NULL, NULL); + sama5d2_pm_init(); +} + +static const char *const sama5d2_compat[] __initconst = { + "atmel,sama5d2", + NULL +}; + +DT_MACHINE_START(sama5d2, "Atmel SAMA5") + /* Maintainer: Atmel */ + .init_machine = sama5d2_init, + .dt_compat = sama5d2_compat, + .l2c_aux_mask = ~0UL, +MACHINE_END -- cgit v1.2.3 From 7693e18e8c2e2f3188f69bd572ff77dac481da6e Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 26 Apr 2017 16:31:03 +0200 Subject: ARM: at91: pm: allow selecting standby and suspend modes While we can only select between "standby" and "mem" states for power management, the atmel platforms can actually support more modes. For both standby and mem, allow selecting which mode will be used using the atmel.pm_modes kernel parameter. By default, keep the current modes. Signed-off-by: Alexandre Belloni Acked-by: Wenyou Yang --- arch/arm/mach-at91/pm.c | 110 +++++++++++++++++++++++++++++++++--------------- arch/arm/mach-at91/pm.h | 3 +- 2 files changed, 78 insertions(+), 35 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index d138d19fa9f0..ef9c1d29cc67 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -38,7 +39,17 @@ extern void at91_pinctrl_gpio_suspend(void); extern void at91_pinctrl_gpio_resume(void); #endif -static struct at91_pm_data pm_data; +static const match_table_t pm_modes __initconst = { + { 0, "standby" }, + { AT91_PM_SLOW_CLOCK, "ulp0" }, + { AT91_PM_BACKUP, "backup" }, + { -1, NULL }, +}; + +static struct at91_pm_data pm_data = { + .standby_mode = 0, + .suspend_mode = AT91_PM_SLOW_CLOCK, +}; #define at91_ramc_read(id, field) \ __raw_readl(pm_data.ramc[id] + field) @@ -68,14 +79,24 @@ static struct at91_pm_bu { phys_addr_t resume; } *pm_bu; -static suspend_state_t target_state; - /* * Called after processes are frozen, but before we shutdown devices. */ static int at91_pm_begin(suspend_state_t state) { - target_state = state; + switch (state) { + case PM_SUSPEND_MEM: + pm_data.mode = pm_data.suspend_mode; + break; + + case PM_SUSPEND_STANDBY: + pm_data.mode = pm_data.standby_mode; + break; + + default: + pm_data.mode = -1; + } + return 0; } @@ -124,7 +145,7 @@ static int at91_pm_verify_clocks(void) */ int at91_suspend_entering_slow_clock(void) { - return (target_state == PM_SUSPEND_MEM); + return (pm_data.mode >= AT91_PM_SLOW_CLOCK); } EXPORT_SYMBOL(at91_suspend_entering_slow_clock); @@ -144,14 +165,6 @@ static int at91_suspend_finish(unsigned long val) static void at91_pm_suspend(suspend_state_t state) { - if (pm_data.deepest_state == AT91_PM_BACKUP) - if (state == PM_SUSPEND_MEM) - pm_data.mode = AT91_PM_BACKUP; - else - pm_data.mode = AT91_PM_SLOW_CLOCK; - else - pm_data.mode = (state == PM_SUSPEND_MEM) ? AT91_PM_SLOW_CLOCK : 0; - if (pm_data.mode == AT91_PM_BACKUP) { pm_bu->suspended = 1; @@ -168,38 +181,37 @@ static void at91_pm_suspend(suspend_state_t state) outer_resume(); } +/* + * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup' + * event sources; and reduces DRAM power. But otherwise it's identical to + * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks. + * + * AT91_PM_SLOW_CLOCK is like STANDBY plus slow clock mode, so drivers must + * suspend more deeply, the master clock switches to the clk32k and turns off + * the main oscillator + * + * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh + */ static int at91_pm_enter(suspend_state_t state) { #ifdef CONFIG_PINCTRL_AT91 at91_pinctrl_gpio_suspend(); #endif + switch (state) { - /* - * Suspend-to-RAM is like STANDBY plus slow clock mode, so - * drivers must suspend more deeply, the master clock switches - * to the clk32k and turns off the main oscillator - */ case PM_SUSPEND_MEM: + case PM_SUSPEND_STANDBY: /* * Ensure that clocks are in a valid state. */ - if (!at91_pm_verify_clocks()) + if ((pm_data.mode >= AT91_PM_SLOW_CLOCK) && + !at91_pm_verify_clocks()) goto error; at91_pm_suspend(state); break; - /* - * STANDBY mode has *all* drivers suspended; ignores irqs not - * marked as 'wakeup' event sources; and reduces DRAM power. - * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and - * nothing fancy done with main or cpu clocks. - */ - case PM_SUSPEND_STANDBY: - at91_pm_suspend(state); - break; - case PM_SUSPEND_ON: cpu_do_idle(); break; @@ -210,8 +222,6 @@ static int at91_pm_enter(suspend_state_t state) } error: - target_state = PM_SUSPEND_ON; - #ifdef CONFIG_PINCTRL_AT91 at91_pinctrl_gpio_resume(); #endif @@ -223,7 +233,6 @@ error: */ static void at91_pm_end(void) { - target_state = PM_SUSPEND_ON; } @@ -475,6 +484,10 @@ static void __init at91_pm_backup_init(void) struct device_node *np; struct platform_device *pdev = NULL; + if ((pm_data.standby_mode != AT91_PM_BACKUP) && + (pm_data.suspend_mode != AT91_PM_BACKUP)) + return; + pm_bu = NULL; np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-shdwc"); @@ -578,10 +591,14 @@ static void __init at91_pm_init(void (*pm_idle)(void)) at91_pm_sram_init(); - if (at91_suspend_sram_fn) + if (at91_suspend_sram_fn) { suspend_set_ops(&at91_pm_ops); - else + pr_info("AT91: PM: standby: %s, suspend: %s\n", + pm_modes[pm_data.standby_mode].pattern, + pm_modes[pm_data.suspend_mode].pattern); + } else { pr_info("AT91: PM not supported, due to no SRAM allocated\n"); + } } void __init at91rm9200_pm_init(void) @@ -613,3 +630,28 @@ void __init sama5d2_pm_init(void) at91_pm_backup_init(); sama5_pm_init(); } + +static int __init at91_pm_modes_select(char *str) +{ + char *s; + substring_t args[MAX_OPT_ARGS]; + int standby, suspend; + + if (!str) + return 0; + + s = strsep(&str, ","); + standby = match_token(s, pm_modes, args); + if (standby < 0) + return 0; + + suspend = match_token(str, pm_modes, args); + if (suspend < 0) + return 0; + + pm_data.standby_mode = standby; + pm_data.suspend_mode = suspend; + + return 0; +} +early_param("atmel.pm_modes", at91_pm_modes_select); diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index d9c6612ef62f..f95d31496f08 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -33,7 +33,8 @@ struct at91_pm_data { unsigned int mode; void __iomem *shdwc; void __iomem *sfrbu; - unsigned int deepest_state; + unsigned int standby_mode; + unsigned int suspend_mode; }; #endif -- cgit v1.2.3 From 287322386d303891e9cdc81313137054da9d5467 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 26 Apr 2017 16:34:24 +0200 Subject: ARM: at91: pm: fallback to slowclock when backup mode fails If the backup sram allocation fails, ensure we can suspend by falling back to the usual slow clock mode. Signed-off-by: Alexandre Belloni Acked-by: Wenyou Yang --- arch/arm/mach-at91/pm.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index ef9c1d29cc67..fc4026478579 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -544,6 +544,11 @@ sfrbu_fail: securam_fail: iounmap(pm_data.sfrbu); pm_data.sfrbu = NULL; + + if (pm_data.standby_mode == AT91_PM_BACKUP) + pm_data.standby_mode = AT91_PM_SLOW_CLOCK; + if (pm_data.suspend_mode == AT91_PM_BACKUP) + pm_data.suspend_mode = AT91_PM_SLOW_CLOCK; } struct pmc_info { -- cgit v1.2.3 From 0f286c4cb620c18206659d9ee91cf0f51d8839b6 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Mon, 15 May 2017 18:12:46 +0800 Subject: ARM: configs: at91: add MCAN driver to sama5_defconfig Add the Controller Area Network (MCAN) driver compilation for sama5 default configuration. Is used by sama5d2 SoC for instance. Signed-off-by: Wenyou Yang Signed-off-by: Alexandre Belloni --- arch/arm/configs/sama5_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index 4c914da669ea..e04494b830ab 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -54,6 +54,7 @@ CONFIG_IP_PNP_RARP=y CONFIG_IPV6_SIT_6RD=y CONFIG_CAN=y CONFIG_CAN_AT91=y +CONFIG_CAN_M_CAN=y CONFIG_CFG80211=y CONFIG_MAC80211=y CONFIG_MAC80211_LEDS=y -- cgit v1.2.3 From 79935915300c5eb88a0e94fa9148a7505c14a02a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 14 May 2017 11:50:50 -0300 Subject: ARM: dts: imx6qdl-wandboard: Fix audio channel swap When running a stress playback/stop loop test on a mx6wandboard channel swaps can be noticed randomly. Increasing the SGTL5000 LRCLK pad strength to its maximum value fixes the issue, so add the 'lrclk-strength' property to avoid the audio channel swaps. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index 82dc5744ae19..850ceadbc2cf 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -88,6 +88,7 @@ clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; + lrclk-strength = <3>; }; }; -- cgit v1.2.3 From 7d098b9108215ce8c5de545a46737f330f83ba2a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 14 May 2017 11:50:51 -0300 Subject: ARM: dts: imx6qdl-colibri: Fix audio channel swap When running a stress playback/stop loop test on a mx6colibri channel swaps can be noticed randomly. Increasing the SGTL5000 LRCLK pad strength to its maximum value fixes the issue, so add the 'lrclk-strength' property to avoid the audio channel swaps. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index e8078758f26c..ad84eddb6836 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -254,6 +254,7 @@ clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; + lrclk-strength = <3>; }; /* STMPE811 touch screen controller */ -- cgit v1.2.3 From a4c584e43e710bef1962049d293a03d1427e129c Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 14 May 2017 15:13:49 +0000 Subject: ARM: mxs_defconfig: Enable CONFIG_CGROUPS In order to support systemd we need to enable CONFIG_CGROUPS. Signed-off-by: Stefan Wahren Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/configs/mxs_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index 6e0f751be229..7b36ebbdcc1d 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig @@ -8,6 +8,7 @@ CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y # CONFIG_UTS_NS is not set # CONFIG_IPC_NS is not set # CONFIG_PID_NS is not set -- cgit v1.2.3 From a85ccf3a216d348fc26d857eb13ec3d72e87656d Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 14 May 2017 15:13:50 +0000 Subject: ARM: mxs_defconfig: Re-enable MXS LRADC The MXS LRADC driver left staging and has been split. So re-enable the driver and remove the obsolete entries. Signed-off-by: Stefan Wahren Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/configs/mxs_defconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index 7b36ebbdcc1d..aef2b54a691c 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig @@ -76,6 +76,7 @@ CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_MXS_LRADC=y CONFIG_TOUCHSCREEN_TSC2007=m # CONFIG_SERIO is not set CONFIG_DEVPTS_MULTIPLE_INSTANCES=y @@ -96,6 +97,7 @@ CONFIG_GPIO_SYSFS=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y CONFIG_STMP3XXX_RTC_WATCHDOG=y +CONFIG_MFD_MXS_LRADC=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_FB=y @@ -137,10 +139,9 @@ CONFIG_RTC_DRV_DS1307=m CONFIG_RTC_DRV_STMP=y CONFIG_DMADEVICES=y CONFIG_MXS_DMA=y -CONFIG_STAGING=y -CONFIG_MXS_LRADC=y CONFIG_IIO=y CONFIG_IIO_SYSFS_TRIGGER=y +CONFIG_MXS_LRADC_ADC=y CONFIG_PWM=y CONFIG_PWM_MXS=y CONFIG_NVMEM=y -- cgit v1.2.3 From 8ebe5c541a00bdffa41a34d192ea674a8400b94a Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Mon, 20 Mar 2017 11:56:42 +0100 Subject: ARM: dts: exynos: Remove MFC reserved buffers During my research I found that some of the requirements for the memory buffers for MFC v6+ devices were blindly copied from the previous (v5) version and simply turned out to be excessive. The relaxed requirements are applied by the recent patches to the MFC driver and the driver is now fully functional even without the reserved memory blocks for all v6+ variants. This patch removes those reserved memory nodes from all boards having MFC v6+ hardware block. Signed-off-by: Marek Szyprowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas Acked-by: Andrzej Hajda Tested-by: Smitha T Murthy Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5250-arndale.dts | 1 - arch/arm/boot/dts/exynos5250-smdk5250.dts | 1 - arch/arm/boot/dts/exynos5250-spring.dts | 1 - arch/arm/boot/dts/exynos5420-arndale-octa.dts | 1 - arch/arm/boot/dts/exynos5420-peach-pit.dts | 1 - arch/arm/boot/dts/exynos5420-smdk5420.dts | 1 - arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 1 - arch/arm/boot/dts/exynos5800-peach-pi.dts | 1 - 8 files changed, 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 6098dacd09f1..6a432460eb77 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -14,7 +14,6 @@ #include #include #include "exynos5250.dtsi" -#include "exynos-mfc-reserved-memory.dtsi" / { model = "Insignal Arndale evaluation board based on EXYNOS5250"; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index a97a785ccc6b..6632f657394e 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -13,7 +13,6 @@ #include #include #include "exynos5250.dtsi" -#include "exynos-mfc-reserved-memory.dtsi" / { model = "SAMSUNG SMDK5250 board based on EXYNOS5250"; diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index 4d7bdb735ed3..95c3bcace9dc 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -14,7 +14,6 @@ #include #include #include "exynos5250.dtsi" -#include "exynos-mfc-reserved-memory.dtsi" / { model = "Google Spring"; diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 9cc83c51c925..ee1bb9b8b366 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -16,7 +16,6 @@ #include #include #include -#include "exynos-mfc-reserved-memory.dtsi" / { model = "Insignal Arndale Octa evaluation board based on EXYNOS5420"; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 1f964ec35c5e..2cd65699a29c 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -16,7 +16,6 @@ #include #include "exynos5420.dtsi" #include "exynos5420-cpus.dtsi" -#include "exynos-mfc-reserved-memory.dtsi" / { model = "Google Peach Pit Rev 6+"; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index aaccd0da41e5..08c8ab173e87 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -13,7 +13,6 @@ #include "exynos5420.dtsi" #include "exynos5420-cpus.dtsi" #include -#include "exynos-mfc-reserved-memory.dtsi" / { model = "Samsung SMDK5420 board based on EXYNOS5420"; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 05b9afdd6757..657535e2e3cc 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -18,7 +18,6 @@ #include #include "exynos5800.dtsi" #include "exynos5422-cpus.dtsi" -#include "exynos-mfc-reserved-memory.dtsi" / { memory@40000000 { diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index f9ff7f07ae0c..ecf1c916e8fc 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -16,7 +16,6 @@ #include #include "exynos5800.dtsi" #include "exynos5420-cpus.dtsi" -#include "exynos-mfc-reserved-memory.dtsi" / { model = "Google Peach Pi Rev 10+"; -- cgit v1.2.3 From 7508a6a72c76fa051fe0186ee128d77cbbe760ac Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 25 Mar 2017 19:26:53 +0300 Subject: ARM: exynos_defconfig: Enable Exynos RNG and user-space crypto API Enable the new Exynos pseudo random number generator driver and user-space API to access crypto algorithms and devices (not only RNG). Signed-off-by: Krzysztof Kozlowski --- arch/arm/configs/exynos_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 6dc661c4a2c1..960d55445e05 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -265,6 +265,12 @@ CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_USER=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_DEV_EXYNOS_RNG=y CONFIG_CRYPTO_DEV_S5P=y CONFIG_ARM_CRYPTO=y CONFIG_CRYPTO_SHA1_ARM_NEON=m -- cgit v1.2.3 From f33160d14f959991e88074fc419546c8d62312a5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 25 Mar 2017 19:26:54 +0300 Subject: ARM: multi_v7_defconfig: Enable Exynos RNG and user-space crypto API Enable the new Exynos pseudo random number generator driver and user-space API to access crypto algorithms and devices (not only RNG). Signed-off-by: Krzysztof Kozlowski --- arch/arm/configs/multi_v7_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 2685e03600b1..705d908e004a 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -935,7 +935,13 @@ CONFIG_CPUFREQ_DT=y CONFIG_KEYSTONE_IRQ=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_ST=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m CONFIG_CRYPTO_DEV_MARVELL_CESA=m +CONFIG_CRYPTO_DEV_EXYNOS_RNG=m CONFIG_CRYPTO_DEV_S5P=m CONFIG_CRYPTO_DEV_SUN4I_SS=m CONFIG_CRYPTO_DEV_ROCKCHIP=m -- cgit v1.2.3 From 072f58af1dfbc39f8daf6be170d90c2465df4771 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 25 Apr 2017 09:45:08 -0700 Subject: ARM: dts: Add devicetree for the Raspberry Pi 3, for arm32 (v6) Raspbian and Fedora have decided to support the Pi3 in 32-bit mode for now, so it's useful to be able to test that mode on an upstream kernel. It's also been useful for me to use the same board for 32-bit and 64-bit development. Signed-off-by: Eric Anholt Acked-by: Olof Johansson --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/bcm2837-rpi-3-b.dts | 1 + 2 files changed, 2 insertions(+) create mode 100644 arch/arm/boot/dts/bcm2837-rpi-3-b.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9c5e1d944d1c..a3db77b7d3d1 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -72,6 +72,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ bcm2835-rpi-b-plus.dtb \ bcm2835-rpi-a-plus.dtb \ bcm2836-rpi-2-b.dtb \ + bcm2837-rpi-3-b.dtb \ bcm2835-rpi-zero.dtb dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm4708-asus-rt-ac56u.dtb \ diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts new file mode 100644 index 000000000000..c72a27d908b6 --- /dev/null +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts @@ -0,0 +1 @@ +#include "arm64/broadcom/bcm2837-rpi-3-b.dts" -- cgit v1.2.3 From 0fe4d2181cc4cb3eba303c0e03f878d2558d0f3a Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Fri, 31 Mar 2017 20:03:04 +0000 Subject: ARM: dts: bcm283x: Add CPU thermal zone with 1 trip point As suggested by Eduardo Valentin this adds the thermal zone for the bcm2835 SoC with its single thermal sensor. We start with the criticial trip point and leave the cooling devices empty since we don't have any at the moment. Since the coefficients could vary depending on the SoC we need to define them separate. Signed-off-by: Stefan Wahren Signed-off-by: Eric Anholt Acked-by: Eduardo Valentin --- arch/arm/boot/dts/bcm2835.dtsi | 4 ++++ arch/arm/boot/dts/bcm2836.dtsi | 4 ++++ arch/arm/boot/dts/bcm283x.dtsi | 21 +++++++++++++++++++++ 3 files changed, 29 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index 0890d97e674d..659b6e9513b1 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -24,6 +24,10 @@ }; }; +&cpu_thermal { + coefficients = <(-538) 407000>; +}; + /* enable thermal sensor with the correct compatible property set */ &thermal { compatible = "brcm,bcm2835-thermal"; diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/bcm2836.dtsi index 519a44f5d25a..da3deeb42592 100644 --- a/arch/arm/boot/dts/bcm2836.dtsi +++ b/arch/arm/boot/dts/bcm2836.dtsi @@ -77,6 +77,10 @@ interrupts = <8>; }; +&cpu_thermal { + coefficients = <(-538) 407000>; +}; + /* enable thermal sensor with the correct compatible property set */ &thermal { compatible = "brcm,bcm2836-thermal"; diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index 561f27d8d922..86a5db53da8f 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -19,6 +19,26 @@ bootargs = "earlyprintk console=ttyAMA0"; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <80000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -430,6 +450,7 @@ compatible = "brcm,bcm2835-thermal"; reg = <0x7e212000 0x8>; clocks = <&clocks BCM2835_CLOCK_TSENS>; + #thermal-sensor-cells = <0>; status = "disabled"; }; -- cgit v1.2.3 From 82985258390e85289940d3663344197344e071f2 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Fri, 7 Apr 2017 17:20:01 -0400 Subject: kill strlen_user() no callers, no consistent semantics, no sane way to use it... Signed-off-by: Al Viro --- arch/arm/include/asm/uaccess.h | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index 2577405d082d..6838abc04279 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -526,7 +526,6 @@ static inline unsigned long __must_check clear_user(void __user *to, unsigned lo /* These are from lib/ code, and use __get_user() and friends */ extern long strncpy_from_user(char *dest, const char __user *src, long count); -extern __must_check long strlen_user(const char __user *str); extern __must_check long strnlen_user(const char __user *str, long n); #endif /* _ASMARM_UACCESS_H */ -- cgit v1.2.3 From d2e19368848ce6065daa785efca26faed54732b6 Mon Sep 17 00:00:00 2001 From: James Morse Date: Tue, 25 Apr 2017 18:02:44 +0100 Subject: KVM: arm: Restore banked registers and physical timer access on hyp_panic() When KVM panics, it hurridly restores the host context and parachutes into the host's panic() code. This looks like it was copied from arm64, the 32bit KVM panic code needs to restore the host's banked registers too. At some point panic() touches the physical timer/counter, this will trap back to HYP. If we're lucky, we panic again. Add a __timer_save_state() call to KVMs hyp_panic() path, this saves the guest registers and disables the traps for the host. Fixes: c36b6db5f3e4 ("ARM: KVM: Add panic handling code") Signed-off-by: James Morse Reviewed-by: Marc Zyngier Reviewed-by: Christoffer Dall Signed-off-by: Christoffer Dall --- arch/arm/kvm/hyp/switch.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/kvm/hyp/switch.c b/arch/arm/kvm/hyp/switch.c index 92678b7bd046..c8f15bb5c8b3 100644 --- a/arch/arm/kvm/hyp/switch.c +++ b/arch/arm/kvm/hyp/switch.c @@ -235,8 +235,10 @@ void __hyp_text __noreturn __hyp_panic(int cause) vcpu = (struct kvm_vcpu *)read_sysreg(HTPIDR); host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context); + __timer_save_state(vcpu); __deactivate_traps(vcpu); __deactivate_vm(vcpu); + __banked_restore_state(host_ctxt); __sysreg_restore_state(host_ctxt); } -- cgit v1.2.3 From 49b2c1305e69da4df1457ce3970f7258c3998460 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 19 Apr 2017 22:30:12 +0200 Subject: ARM: dts: am335x-phycore-som: fix rv4162 compatible The rv4162 compatbile string is missing the vendor part, add it. Signed-off-by: Alexandre Belloni Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-phycore-som.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi index 14533ff6d0ad..428a25e952b0 100644 --- a/arch/arm/boot/dts/am335x-phycore-som.dtsi +++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi @@ -138,7 +138,7 @@ }; i2c_rtc: rtc@68 { - compatible = "rv4162"; + compatible = "microcrystal,rv4162"; reg = <0x68>; status = "disabled"; }; -- cgit v1.2.3 From b9cb2ba7184841ecddaaacfea2ee7d38e1eefd7c Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Thu, 20 Apr 2017 16:25:06 +0530 Subject: ARM: dts: Use - instead of @ for DT OPP entries for TI SoCs Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by: Krzysztof Kozlowski Reported-by: Masahiro Yamada Suggested-by: Mark Rutland Signed-off-by: Viresh Kumar Acked-by: Rob Herring Acked-by: Tony Lindgren Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-boneblack.dts | 2 +- arch/arm/boot/dts/am33xx.dtsi | 20 ++++++++++---------- arch/arm/boot/dts/am4372.dtsi | 10 +++++----- arch/arm/boot/dts/dra7.dtsi | 4 ++-- 4 files changed, 18 insertions(+), 18 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts index 935ed17d22e4..d154d3133c16 100644 --- a/arch/arm/boot/dts/am335x-boneblack.dts +++ b/arch/arm/boot/dts/am335x-boneblack.dts @@ -22,7 +22,7 @@ * BeagleBone Blacks have PG 2.0 silicon which is guaranteed * to support 1GHz OPP so enable it for PG 2.0 on this board. */ - oppnitro@1000000000 { + oppnitro-1000000000 { opp-supported-hw = <0x06 0x0100>; }; }; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 9e242943dcec..bdacb3dd689c 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -64,64 +64,64 @@ * because the can not be enabled simultaneously on a * single SoC. */ - opp50@300000000 { + opp50-300000000 { opp-hz = /bits/ 64 <300000000>; opp-microvolt = <950000 931000 969000>; opp-supported-hw = <0x06 0x0010>; opp-suspend; }; - opp100@275000000 { + opp100-275000000 { opp-hz = /bits/ 64 <275000000>; opp-microvolt = <1100000 1078000 1122000>; opp-supported-hw = <0x01 0x00FF>; opp-suspend; }; - opp100@300000000 { + opp100-300000000 { opp-hz = /bits/ 64 <300000000>; opp-microvolt = <1100000 1078000 1122000>; opp-supported-hw = <0x06 0x0020>; opp-suspend; }; - opp100@500000000 { + opp100-500000000 { opp-hz = /bits/ 64 <500000000>; opp-microvolt = <1100000 1078000 1122000>; opp-supported-hw = <0x01 0xFFFF>; }; - opp100@600000000 { + opp100-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1100000 1078000 1122000>; opp-supported-hw = <0x06 0x0040>; }; - opp120@600000000 { + opp120-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1200000 1176000 1224000>; opp-supported-hw = <0x01 0xFFFF>; }; - opp120@720000000 { + opp120-720000000 { opp-hz = /bits/ 64 <720000000>; opp-microvolt = <1200000 1176000 1224000>; opp-supported-hw = <0x06 0x0080>; }; - oppturbo@720000000 { + oppturbo-720000000 { opp-hz = /bits/ 64 <720000000>; opp-microvolt = <1260000 1234800 1285200>; opp-supported-hw = <0x01 0xFFFF>; }; - oppturbo@800000000 { + oppturbo-800000000 { opp-hz = /bits/ 64 <800000000>; opp-microvolt = <1260000 1234800 1285200>; opp-supported-hw = <0x06 0x0100>; }; - oppnitro@1000000000 { + oppnitro-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <1325000 1298500 1351500>; opp-supported-hw = <0x04 0x0200>; diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 176e09e9a45e..e5b061469bf8 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -59,32 +59,32 @@ compatible = "operating-points-v2-ti-cpu"; syscon = <&scm_conf>; - opp50@300000000 { + opp50-300000000 { opp-hz = /bits/ 64 <300000000>; opp-microvolt = <950000 931000 969000>; opp-supported-hw = <0xFF 0x01>; opp-suspend; }; - opp100@600000000 { + opp100-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1100000 1078000 1122000>; opp-supported-hw = <0xFF 0x04>; }; - opp120@720000000 { + opp120-720000000 { opp-hz = /bits/ 64 <720000000>; opp-microvolt = <1200000 1176000 1224000>; opp-supported-hw = <0xFF 0x08>; }; - oppturbo@800000000 { + oppturbo-800000000 { opp-hz = /bits/ 64 <800000000>; opp-microvolt = <1260000 1234800 1285200>; opp-supported-hw = <0xFF 0x10>; }; - oppnitro@1000000000 { + oppnitro-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <1325000 1298500 1351500>; opp-supported-hw = <0xFF 0x20>; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 57892f264cea..25908dd338ee 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -99,14 +99,14 @@ compatible = "operating-points-v2-ti-cpu"; syscon = <&scm_wkup>; - opp_nom@1000000000 { + opp_nom-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <1060000 850000 1150000>; opp-supported-hw = <0xFF 0x01>; opp-suspend; }; - opp_od@1176000000 { + opp_od-1176000000 { opp-hz = /bits/ 64 <1176000000>; opp-microvolt = <1160000 885000 1160000>; opp-supported-hw = <0xFF 0x02>; -- cgit v1.2.3 From e1a9e61e141d2b61780602b0af2befd7133c0bae Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Tue, 28 Mar 2017 20:57:54 -0500 Subject: ARM: OMAP: Wakeupgen: Add context save/restore for AM43XX AM43XX has the same wakeupgen IP as OMAP4/5. The only notable difference is the presence of 7 register banks and lack of SAR area which has been used in OMAP4/5 for saving and restoring the context around low power states. In case of AM43XX the context is saved and restored by the kernel. Introduce wakeupgen_ops so that context save and restore can be set on a per-SoC basis during init. Signed-off-by: Dave Gerlach Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap-wakeupgen.c | 68 ++++++++++++++++++++++++++++++++---- 1 file changed, 62 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c index 369f95a703ac..33ed5d53fa45 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.c +++ b/arch/arm/mach-omap2/omap-wakeupgen.c @@ -58,6 +58,17 @@ static unsigned int irq_banks = DEFAULT_NR_REG_BANKS; static unsigned int max_irqs = DEFAULT_IRQS; static unsigned int omap_secure_apis; +#ifdef CONFIG_CPU_PM +static unsigned int wakeupgen_context[MAX_NR_REG_BANKS]; +#endif + +struct omap_wakeupgen_ops { + void (*save_context)(void); + void (*restore_context)(void); +}; + +static struct omap_wakeupgen_ops *wakeupgen_ops; + /* * Static helper functions. */ @@ -264,6 +275,16 @@ static inline void omap5_irq_save_context(void) } +static inline void am43xx_irq_save_context(void) +{ + u32 i; + + for (i = 0; i < irq_banks; i++) { + wakeupgen_context[i] = wakeupgen_readl(i, 0); + wakeupgen_writel(0, i, CPU0_ID); + } +} + /* * Save WakeupGen interrupt context in SAR BANK3. Restore is done by * ROM code. WakeupGen IP is integrated along with GIC to manage the @@ -280,11 +301,8 @@ static void irq_save_context(void) if (!sar_base) sar_base = omap4_get_sar_ram_base(); - - if (soc_is_omap54xx()) - omap5_irq_save_context(); - else - omap4_irq_save_context(); + if (wakeupgen_ops && wakeupgen_ops->save_context) + wakeupgen_ops->save_context(); } /* @@ -306,6 +324,20 @@ static void irq_sar_clear(void) writel_relaxed(val, sar_base + offset); } +static void am43xx_irq_restore_context(void) +{ + u32 i; + + for (i = 0; i < irq_banks; i++) + wakeupgen_writel(wakeupgen_context[i], i, CPU0_ID); +} + +static void irq_restore_context(void) +{ + if (wakeupgen_ops && wakeupgen_ops->restore_context) + wakeupgen_ops->restore_context(); +} + /* * Save GIC and Wakeupgen interrupt context using secure API * for HS/EMU devices. @@ -319,6 +351,26 @@ static void irq_save_secure_context(void) if (ret != API_HAL_RET_VALUE_OK) pr_err("GIC and Wakeupgen context save failed\n"); } + +/* Define ops for context save and restore for each SoC */ +static struct omap_wakeupgen_ops omap4_wakeupgen_ops = { + .save_context = omap4_irq_save_context, + .restore_context = irq_sar_clear, +}; + +static struct omap_wakeupgen_ops omap5_wakeupgen_ops = { + .save_context = omap5_irq_save_context, + .restore_context = irq_sar_clear, +}; + +static struct omap_wakeupgen_ops am43xx_wakeupgen_ops = { + .save_context = am43xx_irq_save_context, + .restore_context = am43xx_irq_restore_context, +}; +#else +static struct omap_wakeupgen_ops omap4_wakeupgen_ops = {}; +static struct omap_wakeupgen_ops omap5_wakeupgen_ops = {}; +static struct omap_wakeupgen_ops am43xx_wakeupgen_ops = {}; #endif #ifdef CONFIG_HOTPLUG_CPU @@ -359,7 +411,7 @@ static int irq_notifier(struct notifier_block *self, unsigned long cmd, void *v) break; case CPU_CLUSTER_PM_EXIT: if (omap_type() == OMAP2_DEVICE_TYPE_GP) - irq_sar_clear(); + irq_restore_context(); break; } return NOTIFY_OK; @@ -494,9 +546,13 @@ static int __init wakeupgen_init(struct device_node *node, irq_banks = OMAP4_NR_BANKS; max_irqs = OMAP4_NR_IRQS; omap_secure_apis = 1; + wakeupgen_ops = &omap4_wakeupgen_ops; + } else if (soc_is_omap54xx()) { + wakeupgen_ops = &omap5_wakeupgen_ops; } else if (soc_is_am43xx()) { irq_banks = AM43XX_NR_REG_BANKS; max_irqs = AM43XX_IRQS; + wakeupgen_ops = &am43xx_wakeupgen_ops; } domain = irq_domain_add_hierarchy(parent_domain, 0, max_irqs, -- cgit v1.2.3 From 12b28ba6d6164d3aa54b7e32032bcbd9b7c2a320 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Tue, 28 Mar 2017 20:57:55 -0500 Subject: ARM: OMAP2+: timer: Add suspend-resume callbacks for clkevent device OMAP timer code registers two timers - one as clocksource and one as clockevent. Since AM33XX has only one usable timer in the WKUP domain one of the timers needs suspend-resume support to restore the configuration to pre-suspend state. commit adc78e6b9946 ("timekeeping: Add suspend and resume of clock event devices") introduced .suspend and .resume callbacks for clock event devices. Leverage these callbacks to have AM33XX clockevent timer behave properly across system suspend. Extend the use of the .suspend and .resume callbacks used by am335x clockevent to am437x as well. Signed-off-by: Dave Gerlach Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/timer.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 07dd692c4737..70670dfd7135 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -68,6 +68,9 @@ static struct omap_dm_timer clkev; static struct clock_event_device clockevent_gpt; +/* Clockevent hwmod for am335x and am437x suspend */ +static struct omap_hwmod *clockevent_gpt_hwmod; + #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER static unsigned long arch_timer_freq; @@ -125,6 +128,23 @@ static int omap2_gp_timer_set_periodic(struct clock_event_device *evt) return 0; } +static void omap_clkevt_idle(struct clock_event_device *unused) +{ + if (!clockevent_gpt_hwmod) + return; + + omap_hwmod_idle(clockevent_gpt_hwmod); +} + +static void omap_clkevt_unidle(struct clock_event_device *unused) +{ + if (!clockevent_gpt_hwmod) + return; + + omap_hwmod_enable(clockevent_gpt_hwmod); + __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); +} + static struct clock_event_device clockevent_gpt = { .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, @@ -358,6 +378,14 @@ static void __init omap2_gp_clockevent_init(int gptimer_id, 3, /* Timer internal resynch latency */ 0xffffffff); + if (soc_is_am33xx() || soc_is_am43xx()) { + clockevent_gpt.suspend = omap_clkevt_idle; + clockevent_gpt.resume = omap_clkevt_unidle; + + clockevent_gpt_hwmod = + omap_hwmod_lookup(clockevent_gpt.name); + } + pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name, clkev.rate); } -- cgit v1.2.3 From 33d3842d640e981e2c5ee772befff756b7f2d6f3 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Tue, 28 Mar 2017 20:57:56 -0500 Subject: ARM: OMAP2+: pm: Remove __init from omap_pm_clkdms_setup omap_pm_clkdms_setup gets called from pm init functions and now that pm33xx and pm43xx can be loaded as modules this must be kept to be called at any point during runtime. Signed-off-by: Dave Gerlach Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 63027e60cc20..366158a54fcd 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -71,7 +71,7 @@ void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) } #endif -int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused) +int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused) { clkdm_allow_idle(clkdm); return 0; -- cgit v1.2.3 From a6f627e24139dd8f60057f4812f3fc573c2ad2e3 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 11 Apr 2017 16:16:15 +0300 Subject: ARM: dts: dra7x-evm: Enable dual-role mode for USB1 USB1 port is micro-AB type and can function as peripheral as well as host. Enable dual-role mode for USB1. We don't want to use the OTG controller block on this platform as it limits host mode to high-speed. Instead we rely on extcon framework to give us ID events for dual-role mode detection. Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-evm.dts | 3 ++- arch/arm/boot/dts/dra72-evm-common.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 4bc4b575c99b..c408aaa1992b 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -527,7 +527,8 @@ }; &usb1 { - dr_mode = "peripheral"; + dr_mode = "otg"; + extcon = <&extcon_usb1>; }; &usb2 { diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index ad24544adf0f..85780549bc26 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -392,7 +392,8 @@ }; &usb1 { - dr_mode = "peripheral"; + dr_mode = "otg"; + extcon = <&extcon_usb1>; }; &usb2 { -- cgit v1.2.3 From decd2db7ba3825f5a87f5d2ec159febbe8506d1e Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 3 May 2017 16:22:26 +0200 Subject: ARM: dts: omap4-droid4: Add bluetooth Droid 4 has WL 1285C connected to the OMAP's UART4 port, which is used for Bluetooth and most likely can also be used for controlling the FM radio and GPS receivers. Signed-off-by: Sebastian Reichel Reviewed-by: Rob Herring Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-droid4-xt894.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts index 89eb607f4a9e..13f8d8640208 100644 --- a/arch/arm/boot/dts/omap4-droid4-xt894.dts +++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts @@ -453,6 +453,15 @@ OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7) >; }; + + uart4_pins: pinmux_uart4_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx */ + OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx */ + OMAP4_IOPAD(0x110, PIN_INPUT_PULLUP | MUX_MODE5) /* uart4_cts */ + OMAP4_IOPAD(0x112, PIN_OUTPUT_PULLUP | MUX_MODE5) /* uart4_rts */ + >; + }; }; &omap4_pmx_wkup { @@ -469,6 +478,17 @@ &omap4_pmx_core 0x17c>; }; +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + + bluetooth { + compatible = "ti,wl1285-st"; + enable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; /* gpio 174 */ + max-speed = <3686400>; + }; +}; + &usbhsehci { phys = <&hsusb1_phy>; }; -- cgit v1.2.3 From 27a8133136823cd8c9296555efdc0cee42e88a0f Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Mon, 15 May 2017 10:31:16 +0200 Subject: =?UTF-8?q?ARM:=20dts:=20OMAP5:=20uevm:=20add=20=C2=B5SD=20card=20?= =?UTF-8?q?detect?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If we have Linux installed in eMMC we can boot without µSD card, but inserting one is not recognised. The reason is that the card detect gpio (gpio5_152) is not configured and attached to the mmc1 interface driver and the mmc driver does not poll by default. Hence we add pinmux and gpio setup for the SDCARD_NCD signal. Signed-off-by: H. Nikolaus Schaller Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-uevm.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 0d42c46f13e7..ec2c8baef62a 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -137,6 +137,13 @@ }; }; +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + + cd-gpios = <&gpio5 24 GPIO_ACTIVE_LOW>; /* gpio5_152 */ +}; + &omap5_pmx_core { evm_keys_pins: pinmux_evm_keys_gpio_pins { pinctrl-single,pins = < @@ -150,6 +157,12 @@ OMAP5_IOPAD(0x1c8, PIN_INPUT | MUX_MODE0) /* i2c5_sda */ >; }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x1d4, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio5_152 */ + >; + }; }; &tpd12s015 { -- cgit v1.2.3 From a19adf8d86e822eba502486524127595372c85f6 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Wed, 8 Mar 2017 10:19:10 +0100 Subject: ARM: dts: bcm283x: switch from &sdhci to &sdhost sdcard access with the sdhost controller is faster. Read access (dd with 64k blocks on rpi2): CONFIG_MMC_SDHCI_IPROC: 11-12 MB/s CONFIG_MMC_BCM2835: 19-20 MB/s Differences on write access are pretty much in the noise. Signed-off-by: Gerd Hoffmann Acked-by: Eric Anholt --- arch/arm/boot/dts/bcm2835-rpi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi index a7b5ce133784..e55b362b9d6e 100644 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -65,13 +65,13 @@ &sdhci { pinctrl-names = "default"; pinctrl-0 = <&emmc_gpio48>; - status = "okay"; bus-width = <4>; }; &sdhost { pinctrl-names = "default"; pinctrl-0 = <&sdhost_gpio48>; + status = "okay"; bus-width = <4>; }; -- cgit v1.2.3 From d8d673433e967a448f0342d0c722f1168f9fe149 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Mon, 15 May 2017 16:53:26 -0500 Subject: ARM: davinci_all_defconfig: enable LEGO MINDSTORMS EV3 battery module This enables the power supply module for the LEGO MINDSTORMS EV3 battery. Signed-off-by: David Lechner Signed-off-by: Sekhar Nori --- arch/arm/configs/davinci_all_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index 67db82999c06..88575865c241 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig @@ -122,6 +122,7 @@ CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCA953X_IRQ=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO=y +CONFIG_BATTERY_LEGO_EV3=m CONFIG_WATCHDOG=y CONFIG_DAVINCI_WATCHDOG=m CONFIG_MFD_DM355EVM_MSP=y -- cgit v1.2.3 From b8a46eea52fce1de30b2c4d0c9438d2a011a86ba Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 11 Apr 2017 16:05:23 -0500 Subject: ARM: dts: da850-lego-ev3: Add node for LEGO MINDSTORMS EV3 Battery This adds a new node to the LEGO MINDSTORMS EV3 device tree for the battery. Signed-off-by: David Lechner [nsekhar@ti.com: minor headline fix] Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850-lego-ev3.dts | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/da850-lego-ev3.dts b/arch/arm/boot/dts/da850-lego-ev3.dts index 512604ad8b71..45983c04a8a7 100644 --- a/arch/arm/boot/dts/da850-lego-ev3.dts +++ b/arch/arm/boot/dts/da850-lego-ev3.dts @@ -172,6 +172,18 @@ gpio = <&gpio 111 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + /* + * The EV3 can use 6-AA batteries or a rechargeable Li-ion battery pack. + */ + battery { + pinctrl-names = "default"; + pintctrl-0 = <&battery_pins>; + compatible = "lego,ev3-battery"; + io-channels = <&adc 4>, <&adc 3>; + io-channel-names = "voltage", "current"; + rechargeable-gpios = <&gpio 136 GPIO_ACTIVE_LOW>; + }; }; &pmx_core { @@ -228,6 +240,15 @@ 0x34 0x00000008 0x0000000f >; }; + + battery_pins: pinmux_battery_pins { + pinctrl-single,bits = < + /* GP0[6] */ + 0x04 0x00000080 0x000000f0 + /* GP8[8] */ + 0x4c 0x00000080 0x000000f0 + >; + }; }; &pinconf { @@ -342,6 +363,13 @@ &gpio { status = "okay"; + + /* Don't pull down battery voltage adc io channel */ + batt_volt_en { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-low; + }; }; &usb_phy { -- cgit v1.2.3 From 9d420e9b4140f8938ad6aa0d29e2428a2af6122b Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Wed, 17 May 2017 17:52:24 +0800 Subject: ARM: dts: rockchip: fix rk322x i2s1 pinctrl error Refer to Chapter 5.3.2 of rk3229 TRM, we can see that GPIO1A[2,4,5] using RK_FUNC_2 not RK_FUNC_1. This patch fixes it. Signed-off-by: Sugar Zhang Signed-off-by: Frank Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 48a0c1cf4301..cc6a27dbcc29 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -621,9 +621,9 @@ <0 12 RK_FUNC_1 &pcfg_pull_none>, <0 13 RK_FUNC_1 &pcfg_pull_none>, <0 14 RK_FUNC_1 &pcfg_pull_none>, - <1 2 RK_FUNC_1 &pcfg_pull_none>, - <1 4 RK_FUNC_1 &pcfg_pull_none>, - <1 5 RK_FUNC_1 &pcfg_pull_none>; + <1 2 RK_FUNC_2 &pcfg_pull_none>, + <1 4 RK_FUNC_2 &pcfg_pull_none>, + <1 5 RK_FUNC_2 &pcfg_pull_none>; }; }; -- cgit v1.2.3 From fa206984331b2fd5c8821f0ca63c8f0eec837f2b Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Wed, 17 May 2017 17:52:26 +0800 Subject: ARM: dts: rockchip: add watchdog device node on rk322x Add watchdog device node for rk322x SoC. Signed-off-by: Frank Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index cc6a27dbcc29..1b46bf81932a 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -280,6 +280,14 @@ status = "disabled"; }; + wdt: watchdog@110a0000 { + compatible = "snps,dw-wdt"; + reg = <0x110a0000 0x100>; + interrupts = ; + clocks = <&cru PCLK_CPU>; + status = "disabled"; + }; + pwm0: pwm@110b0000 { compatible = "rockchip,rk3288-pwm"; reg = <0x110b0000 0x10>; -- cgit v1.2.3 From 02131477b9028720037438948047a6233e8bdb81 Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Wed, 17 May 2017 17:52:25 +0800 Subject: ARM: dts: rockchip: correct rk322x uart2 pinctrl Correct UART2 PINCTRL flag to use the correct pull up setting Signed-off-by: Frank Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 1b46bf81932a..5300a1e765ec 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -701,7 +701,7 @@ uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, <1 19 RK_FUNC_2 &pcfg_pull_none>; }; -- cgit v1.2.3 From 738e451174d428881910b9b7558965668216ed5b Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Wed, 17 May 2017 17:52:25 +0800 Subject: ARM: dts: rockchip: add second uart2 pinctrl on rk322x Add secondary pinctrl set for UART2 which can be used to prevent conflicts with sdmmc pins. Signed-off-by: Frank Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 5300a1e765ec..816b0796d816 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -705,6 +705,11 @@ <1 19 RK_FUNC_2 &pcfg_pull_none>; }; + uart21_xfer: uart21-xfer { + rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>, + <1 9 RK_FUNC_2 &pcfg_pull_none>; + }; + uart2_cts: uart2-cts { rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; }; -- cgit v1.2.3 From 87ac8e18ee7217187170e038f2fa9a1faf59dcc7 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Mon, 15 May 2017 16:40:01 +0800 Subject: ARM: sun8i: v3s: add support for Lichee Pi Zero w/ dock board The Lichee Pi Zero board has a "dock board" which needs to be soldered with the 1.27mm stamp holes on a Lichee Pi Zero board. It features: - Onboard MIC and headphone jack (not supported yet) - Ethernet port (not supported yet) - An extra MicroSD slot connected to MMC1 controller - four keys connected to the LRADC. As it needs to be soldered with the main board to use, add a stand-alone device tree for it. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 96 ++++++++++++++++++++++ 2 files changed, 98 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9c5e1d944d1c..929a4167fcaa 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -905,7 +905,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-orangepi-plus.dtb \ sun8i-h3-orangepi-plus2e.dtb \ sun8i-r16-parrot.dtb \ - sun8i-v3s-licheepi-zero.dtb + sun8i-v3s-licheepi-zero.dtb \ + sun8i-v3s-licheepi-zero-dock.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts new file mode 100644 index 000000000000..d1311098ea45 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2016 Icenowy Zheng + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun8i-v3s-licheepi-zero.dts" + +#include + +/ { + model = "Lichee Pi Zero with Dock"; + compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero", + "allwinner,sun8i-v3s"; + + leds { + /* The LEDs use PG0~2 pins, which conflict with MMC1 */ + status = "disbaled"; + }; +}; + +&mmc1 { + broken-cd; + bus-width = <4>; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button@200 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <200000>; + }; + + button@400 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <400000>; + }; + + button@600 { + label = "Select"; + linux,code = ; + channel = <0>; + voltage = <600000>; + }; + + button@800 { + label = "Start"; + linux,code = ; + channel = <0>; + voltage = <800000>; + }; +}; -- cgit v1.2.3 From 2a451bfa9870a766acc54243ed5e75435e9a1b03 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 17 May 2017 21:52:57 +0800 Subject: ARM: sun8i: v3s: enable SPI Allwinner V3s SoC has a SPI controller, muxed with the MMC2 controller at PC bank. The controller itself is identical to the one in H3 SoC. Add device tree node and the only pinmux node for it. Tested with a Winbond W25Q128FV SPI NOR soldered on the Lichee Pi early sample. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 6ff50665e5e6..a49ebef53c91 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -234,6 +234,11 @@ drive-strength = <30>; bias-pull-up; }; + + spi0_pins: spi0 { + pins = "PC0", "PC1", "PC2", "PC3"; + function = "spi0"; + }; }; timer@01c20c00 { @@ -314,6 +319,20 @@ #size-cells = <0>; }; + spi0: spi@1c68000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x01c68000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + gic: interrupt-controller@01c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, -- cgit v1.2.3 From e663bc04ec448f08f465d26916bded59e182f008 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 15 May 2017 11:25:09 -0300 Subject: ARM: dts: imx6sx-sdb: Properly model the ARM and SOC regulator supplies On imx6sx-sdb rev B/C the VDD_ARM_IN and VDD_SOC_IN supplies are connected together and both are supplied by the SW1A PMIC output, so model this correctly in the device tree. Suggested-by: Marek Vasut Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx-sdb.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index 5bb8fd57e7f5..64bda498f5d3 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -145,3 +145,11 @@ reg = <1>; }; }; + +®_arm { + vin-supply = <&sw1a_reg>; +}; + +®_soc { + vin-supply = <&sw1a_reg>; +}; -- cgit v1.2.3 From 0d2c6f023ea173ef59a930b67e2e02a943f60b63 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 17 May 2017 09:40:49 +0200 Subject: ARM: sun5i: a10s: Add the HDMI controller node The A10s has an HDMI controller connected to the second TCON channel. Add it to our DT. Since the TV Encoder was the only channel 1 user so far, also add the property now that we have several users. Signed-off-by: Maxime Ripard [wens@csie.org: Replaced CLK_PLL_VIDEO[01]_2X with raw numbers for now Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i-a10s.dtsi | 47 +++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/sun5i.dtsi | 1 + 2 files changed, 48 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 1e38ff80366c..18f25c5e75ae 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -71,7 +71,46 @@ }; }; + display-engine { + compatible = "allwinner,sun5i-a10s-display-engine"; + allwinner,pipelines = <&fe0>; + }; + soc@01c00000 { + hdmi: hdmi@01c16000 { + compatible = "allwinner,sun5i-a10s-hdmi"; + reg = <0x01c16000 0x1000>; + interrupts = <58>; + clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>, + <&ccu 9>, + <&ccu 16>; + clock-names = "ahb", "mod", "pll-0", "pll-1"; + dmas = <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_DEDICATED 24>; + dma-names = "ddc-tx", "ddc-rx", "audio-tx"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + + hdmi_in_tcon0: endpoint { + remote-endpoint = <&tcon0_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + pwm: pwm@01c20e00 { compatible = "allwinner,sun5i-a10s-pwm"; reg = <0x01c20e00 0xc>; @@ -128,3 +167,11 @@ &sram_a { }; + +&tcon0_out { + tcon0_out_hdmi: endpoint@2 { + reg = <2>; + remote-endpoint = <&hdmi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; +}; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 5175f9cc9bed..0e29f1d98a9e 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -272,6 +272,7 @@ tcon0_out_tve0: endpoint@1 { reg = <1>; remote-endpoint = <&tve0_in_tcon0>; + allwinner,tcon-channel = <1>; }; }; }; -- cgit v1.2.3 From d050971c42b0df9056114086ce835a8db0074b84 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 17 May 2017 09:40:50 +0200 Subject: ARM: sun5i: a10s-olinuxino: Enable HDMI The A10s Olinuxino has an HDMI connector. Make sure we can use it. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 29 ++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index eff36fe1aaa3..da95118af4dc 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -63,6 +63,17 @@ stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -76,6 +87,10 @@ }; }; +&be0 { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -91,6 +106,16 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -248,6 +273,10 @@ status = "okay"; }; +&tcon0 { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; -- cgit v1.2.3 From 1a8c176b2f15b879746b85b4c0d585f2016b65e3 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 19 May 2017 15:06:10 +0800 Subject: ARM: sun8i: a83t: Add CCU device nodes Now that we have support for the A83T CCU, add a device node for it, and replace any existing placeholder clock phandles with the correct ones. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index c0a1e4f74b89..c9a5d07b2ada 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -162,13 +162,23 @@ #size-cells = <1>; ranges; + ccu: clock@1c20000 { + compatible = "allwinner,sun8i-a83t-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc16Md512>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + pio: pinctrl@1c20800 { compatible = "allwinner,sun8i-a83t-pinctrl"; interrupts = , , ; reg = <0x01c20800 0x400>; - clocks = <&osc24M>; + clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>; + clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; @@ -214,7 +224,8 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&ccu 53>; + resets = <&ccu 40>; status = "disabled"; }; -- cgit v1.2.3 From c31d488470820ab18eabd2c5bb9a08834d554d28 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 19 May 2017 15:06:11 +0800 Subject: ARM: sun8i: a83t: Set clock accuracy for 24MHz oscillator The datasheets for Allwinner SoCs set strict requirements on the stability of the external crystal oscillators. Add the accuracy for the main 24MHz oscillator to the device tree. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index c9a5d07b2ada..e12dd7170b8f 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -126,6 +126,7 @@ #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; + clock-accuracy = <50000>; clock-output-names = "osc24M"; }; -- cgit v1.2.3 From 30ee58146b53d83e90fc5326488e1e48a5a3aba4 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Wed, 17 May 2017 18:16:14 +0800 Subject: ARM: dts: rockchip: set default rates for core clocks on rk322x Set sane default frequencies for CPLL, GPLL and some other core clocks on the rk322x. Signed-off-by: Elaine Zhang Signed-off-by: Frank Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 816b0796d816..c256df9a2cd8 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -346,8 +346,18 @@ rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>; - assigned-clock-rates = <594000000>; + assigned-clocks = + <&cru PLL_GPLL>, <&cru ARMCLK>, + <&cru PLL_CPLL>, <&cru ACLK_PERI>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>, + <&cru ACLK_CPU>, <&cru HCLK_CPU>, + <&cru PCLK_CPU>; + assigned-clock-rates = + <594000000>, <816000000>, + <500000000>, <150000000>, + <150000000>, <75000000>, + <150000000>, <150000000>, + <75000000>; }; thermal-zones { -- cgit v1.2.3 From 9f12da43c327b4eed4c7dc47a8ac37b05e39c3d0 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 17 May 2017 18:16:15 +0800 Subject: ARM: dts: rockchip: add operating-points-v2 for cpu on rk322x This patch adds a new opp table for cpu on rk322x SoC. Signed-off-by: Finley Xiao Signed-off-by: Frank Wang Acked-by: Viresh Kumar Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index c256df9a2cd8..c09e17cc4ab0 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -66,10 +66,7 @@ compatible = "arm,cortex-a7"; reg = <0xf00>; resets = <&cru SRST_CORE0>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; + operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; /* min followed by max */ clock-latency = <40000>; clocks = <&cru ARMCLK>; @@ -80,6 +77,7 @@ compatible = "arm,cortex-a7"; reg = <0xf01>; resets = <&cru SRST_CORE1>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu2: cpu@f02 { @@ -87,6 +85,7 @@ compatible = "arm,cortex-a7"; reg = <0xf02>; resets = <&cru SRST_CORE2>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu3: cpu@f03 { @@ -94,6 +93,35 @@ compatible = "arm,cortex-a7"; reg = <0xf03>; resets = <&cru SRST_CORE3>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1175000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1275000>; }; }; -- cgit v1.2.3 From 2b3f2f37ef4d7b9f233d7dc9529b789709b6c988 Mon Sep 17 00:00:00 2001 From: Rocky Hao Date: Wed, 17 May 2017 18:16:17 +0800 Subject: ARM: dts: rockchip: set a sane frequence for tsadc on rk322x Update freq of tsadc's working clock as 32768 hz, if not set, tsadc will work at a default frequence. Signed-off-by: Rocky Hao Signed-off-by: Frank Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index c09e17cc4ab0..df574135797a 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -434,6 +434,8 @@ interrupts = ; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <32768>; resets = <&cru SRST_TSADC>; reset-names = "tsadc-apb"; pinctrl-names = "init", "default", "sleep"; -- cgit v1.2.3 From 27d9fa06c122b135ad7552fa3138c3b47e5776c5 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Fri, 28 Apr 2017 16:11:29 -0400 Subject: ARM: BCM: Enable thermal support for NSP SoCs Change the Northstar Plus Kconfig to select THERMAL and THERMAL_OF, which allows the ns-thermal driver to be selected via menuconfig. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/mach-bcm/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index f9389c5910e7..abfce8f29ca1 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -44,6 +44,8 @@ config ARCH_BCM_NSP select ARM_ERRATA_775420 select ARM_ERRATA_764369 if SMP select HAVE_SMP + select THERMAL + select THERMAL_OF help Support for Broadcom Northstar Plus SoC. Broadcom Northstar Plus family of SoCs are used for switching control -- cgit v1.2.3 From 5c73cdf2bdf0570599d2fb849e9f54889be6df18 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 17 May 2017 13:44:19 -0300 Subject: ARM: dts: omap3: Remove 'enable-active-low' property Property 'enable-active-low' does not exist. Only 'enable-active-high' is valid, and when this property is absent the gpio regulator will act as active low by default. So remove the unexisting 'enable-active-low' property. Signed-off-by: Fabio Estevam Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-evm-common.dtsi | 1 - arch/arm/boot/dts/omap3-sb-t35.dtsi | 1 - arch/arm/boot/dts/omap3-tao3530.dtsi | 1 - 3 files changed, 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi index 090475083c2f..7780e2528697 100644 --- a/arch/arm/boot/dts/omap3-evm-common.dtsi +++ b/arch/arm/boot/dts/omap3-evm-common.dtsi @@ -76,7 +76,6 @@ &lcd_3v3 { gpio = <&gpio5 25 GPIO_ACTIVE_LOW>; /* gpio153 */ - enable-active-low; }; &lcd0 { diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/omap3-sb-t35.dtsi index 73643fabde5d..91e15af78949 100644 --- a/arch/arm/boot/dts/omap3-sb-t35.dtsi +++ b/arch/arm/boot/dts/omap3-sb-t35.dtsi @@ -50,7 +50,6 @@ pinctrl-names = "default"; pinctrl-0 = <&sb_t35_audio_amp>; gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; /* gpio_61 */ - enable-active-low; regulator-always-on; }; }; diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi index dc80886b5329..06ac0f80bcf0 100644 --- a/arch/arm/boot/dts/omap3-tao3530.dtsi +++ b/arch/arm/boot/dts/omap3-tao3530.dtsi @@ -63,7 +63,6 @@ regulator-min-microvolt = <3150000>; regulator-max-microvolt = <3150000>; gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; /* gpio_157 */ - enable-active-low; startup-delay-us = <10000>; }; }; -- cgit v1.2.3 From e3df026c594c77f0de1bdaa413d591b4345e4b6a Mon Sep 17 00:00:00 2001 From: Guillaume Tucker Date: Wed, 3 May 2017 10:56:26 +0100 Subject: ARM: dts: rockchip: add ARM Mali GPU node for rk3288 Add Mali GPU device tree node for the rk3288 SoC, with devfreq opp table. Signed-off-by: Guillaume Tucker Tested-by: Enric Balletbo i Serra Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index ad5d6022e95f..2484f11761ea 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -43,6 +43,7 @@ #include #include #include +#include #include #include #include @@ -1125,6 +1126,48 @@ }; }; + gpu: mali@ffa30000 { + compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard"; + reg = <0xffa30000 0x10000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&cru ACLK_GPU>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3288_PD_GPU>; + status = "disabled"; + }; + + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <950000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <950000>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1000000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1100000>; + }; + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1200000>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1250000>; + }; + }; + qos_gpu_r: qos@ffaa0000 { compatible = "syscon"; reg = <0xffaa0000 0x20>; -- cgit v1.2.3 From d6823b67288aad6810336b963140059721c83644 Mon Sep 17 00:00:00 2001 From: Guillaume Tucker Date: Wed, 3 May 2017 10:56:27 +0100 Subject: ARM: dts: rockchip: enable ARM Mali GPU on rk3288-rock2-som Add reference to the Mali GPU device tree node on the rk3288-rock2-som platform. Tested on a Radxa Rock2 Square board. Signed-off-by: Guillaume Tucker Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-rock2-som.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi index f0778a46bca9..749a9b86e6e2 100644 --- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi +++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi @@ -113,6 +113,11 @@ tx_delay = <0x30>; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &i2c0 { status = "okay"; -- cgit v1.2.3 From 93dedf52894e360731de17bdd9358873b36c3e0f Mon Sep 17 00:00:00 2001 From: Guillaume Tucker Date: Wed, 3 May 2017 10:56:28 +0100 Subject: ARM: dts: rockchip: enable ARM Mali GPU on rk3288-firefly Add reference to the Mali GPU device tree node on rk3288-firefly. Tested on Firefly board. Signed-off-by: Guillaume Tucker Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-firefly.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index 10793ac18599..864747342e3e 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -219,6 +219,11 @@ status = "ok"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &hdmi { ddc-i2c-bus = <&i2c5>; status = "okay"; -- cgit v1.2.3 From 08e779e59950affaec4f677b22fda6a1ab150a43 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Wed, 3 May 2017 10:56:29 +0100 Subject: ARM: dts: rockchip: enable ARM Mali GPU on rk3288-veyron Add reference to the Mali GPU device tree node on rk3288-veyron. Tested on Minnie and Jerry boards. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Guillaume Tucker Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 5d1eb0a25827..d709fa1847f9 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -161,6 +161,11 @@ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &hdmi { ddc-i2c-bus = <&i2c5>; status = "okay"; -- cgit v1.2.3 From 38281a4754809d830d9a4a56d1b2ab7902b9fd6d Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Mon, 15 May 2017 07:52:59 -0700 Subject: ARM: dts: imx: Reintroduce 'anatop-enable-bit' where appropriate Now that support for 'anatop-enable-bit' has been added to ANADIG driver, reintroduce 'anatop-enable-bit' for all applicable LDOs. Cc: yurovsky@gmail.com Cc: Dong Aisheng Cc: Sascha Hauer Cc: Fabio Estevam Cc: Rob Herring Cc: Mark Rutland Cc: Russell King Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 3 +++ arch/arm/boot/dts/imx6sl.dtsi | 3 +++ arch/arm/boot/dts/imx6sx.dtsi | 3 +++ arch/arm/boot/dts/imx6ul.dtsi | 1 + arch/arm/boot/dts/imx7s.dtsi | 1 + 5 files changed, 11 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 2c2af6737b0e..f325411f66aa 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -644,6 +644,7 @@ anatop-min-bit-val = <4>; anatop-min-voltage = <800000>; anatop-max-voltage = <1375000>; + anatop-enable-bit = <0>; }; regulator-3p0 { @@ -658,6 +659,7 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2625000>; anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; }; regulator-2p5 { @@ -672,6 +674,7 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2100000>; anatop-max-voltage = <2875000>; + anatop-enable-bit = <0>; }; reg_arm: regulator-vddcore { diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index cc9572ea2860..3243af4a9984 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -530,6 +530,7 @@ anatop-min-bit-val = <4>; anatop-min-voltage = <800000>; anatop-max-voltage = <1375000>; + anatop-enable-bit = <0>; }; regulator-3p0 { @@ -544,6 +545,7 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2625000>; anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; }; regulator-2p5 { @@ -558,6 +560,7 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2100000>; anatop-max-voltage = <2850000>; + anatop-enable-bit = <0>; }; reg_arm: regulator-vddcore { diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 3f1416be4c36..f16b9df9d0c6 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -587,6 +587,7 @@ anatop-min-bit-val = <4>; anatop-min-voltage = <800000>; anatop-max-voltage = <1375000>; + anatop-enable-bit = <0>; }; regulator-3p0 { @@ -601,6 +602,7 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2625000>; anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; }; regulator-2p5 { @@ -615,6 +617,7 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2100000>; anatop-max-voltage = <2875000>; + anatop-enable-bit = <0>; }; reg_arm: regulator-vddcore { diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index b9d7d2d09402..6da2b77edd46 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -542,6 +542,7 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2625000>; anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; }; reg_arm: regulator-vddcore { diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 843eb379e1ea..b4464adfbbde 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -516,6 +516,7 @@ anatop-min-bit-val = <8>; anatop-min-voltage = <800000>; anatop-max-voltage = <1200000>; + anatop-enable-bit = <0>; }; }; -- cgit v1.2.3 From 0f90b43ac71b484eebfc73e0f517110327071230 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Mon, 15 May 2017 07:53:01 -0700 Subject: ARM: dts: imx7s: Add node for GPC Add node for GPC and specify as a parent interrupt controller for SoC bus. Cc: yurovsky@gmail.com Cc: Dong Aisheng Cc: Sascha Hauer Cc: Fabio Estevam Cc: Rob Herring Cc: Mark Rutland Cc: Russell King Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index b4464adfbbde..b6ed1036f9e3 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -42,6 +42,7 @@ */ #include +#include #include #include #include @@ -119,7 +120,7 @@ #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; - interrupt-parent = <&intc>; + interrupt-parent = <&gpc>; ranges; funnel@30041000 { @@ -301,6 +302,7 @@ interrupts = ; #interrupt-cells = <3>; interrupt-controller; + interrupt-parent = <&intc>; reg = <0x31001000 0x1000>, <0x31002000 0x2000>, <0x31004000 0x2000>, @@ -309,6 +311,7 @@ timer { compatible = "arm,armv7-timer"; + interrupt-parent = <&intc>; interrupts = , , , @@ -564,6 +567,27 @@ interrupts = ; #reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx7d-gpc"; + reg = <0x303a0000 0x10000>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + #power-domain-cells = <1>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_pcie_phy: pgc-power-domain@IMX7_POWER_DOMAIN_PCIE_PHY { + #power-domain-cells = <0>; + reg = ; + power-supply = <®_1p0d>; + }; + }; + }; }; aips2: aips-bus@30400000 { -- cgit v1.2.3 From 9760c06bc20f82529aec4874b199a8e3437442a2 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Mon, 15 May 2017 07:53:02 -0700 Subject: ARM: dts: imx7s: Mark 'gpr' compatible with i.MX6 variant List GPR block as compatible "fsl,imx6q-iomuxc-gpr" to support drivers requesting it that way (PCIe driver is one example). Cc: yurovsky@gmail.com Cc: Dong Aisheng Cc: Sascha Hauer Cc: Fabio Estevam Cc: Rob Herring Cc: Mark Rutland Cc: Russell King Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index b6ed1036f9e3..aa1f4c3e915c 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -491,7 +491,8 @@ }; gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx7d-iomuxc-gpr", "syscon"; + compatible = "fsl,imx7d-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; }; -- cgit v1.2.3 From 184f39b57cab6fd00b045689d300070ca0ceac78 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Mon, 15 May 2017 07:53:03 -0700 Subject: ARM: dts: imx7d-sdb: Add GPIO expander node Add node for U38, a 74LV595PW serial-in shift register that acts as a GPIO expander on the board. Cc: yurovsky@gmail.com Cc: Dong Aisheng Cc: Sascha Hauer Cc: Fabio Estevam Cc: Rob Herring Cc: Mark Rutland Cc: Russell King Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-sdb.dts | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 5be01a1bf840..d6f2dda90710 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -52,6 +52,27 @@ reg = <0x80000000 0x80000000>; }; + spi4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + extended_io: gpio-expander@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + spi-max-frequency = <100000>; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -642,5 +663,13 @@ fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x110b0 >; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 + >; + }; }; }; -- cgit v1.2.3 From a816d5750edf7151e079c4929c60e2531fc98fa6 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Mon, 15 May 2017 07:53:04 -0700 Subject: ARM: dts: imx7d: Add node for PCIe controller Cc: yurovsky@gmail.com Cc: Dong Aisheng Cc: Sascha Hauer Cc: Fabio Estevam Cc: Rob Herring Cc: Mark Rutland Cc: Russell King Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d.dtsi | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index f6dee41a05d9..f46814a7ea44 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -42,6 +42,7 @@ */ #include "imx7s.dtsi" +#include / { cpus { @@ -127,6 +128,42 @@ fsl,num-rx-queues=<3>; status = "disabled"; }; + + pcie: pcie@0x33800000 { + compatible = "fsl,imx7d-pcie", "snps,dw-pcie"; + reg = <0x33800000 0x4000>, + <0x4ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, + <&clks IMX7D_PCIE_PHY_ROOT_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>, + <&clks IMX7D_PCIE_PHY_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + + fsl,max-link-speed = <2>; + power-domains = <&pgc_pcie_phy>; + resets = <&src IMX7_RESET_PCIEPHY>, + <&src IMX7_RESET_PCIE_CTRL_APPS_EN>; + reset-names = "pciephy", "apps"; + status = "disabled"; + }; }; &ca_funnel_ports { -- cgit v1.2.3 From 34adfaa3d404c0e763fa3614cfe01078e29c56c7 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Mon, 15 May 2017 07:53:05 -0700 Subject: ARM: dts: imx7d-sdb: Enable PCIe peripheral Enable PCIe peripheral on this board. Cc: yurovsky@gmail.com Cc: Dong Aisheng Cc: Sascha Hauer Cc: Fabio Estevam Cc: Rob Herring Cc: Mark Rutland Cc: Russell King Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-sdb.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index d6f2dda90710..77c400f0017a 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -349,6 +349,11 @@ }; }; +&pcie { + reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; -- cgit v1.2.3 From da6ee0c300b8a38cd79e64c9b1fd1a3ba94da7b2 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Mon, 15 May 2017 08:03:50 -0700 Subject: ARM: imx: Select GPCv2 for i.MX7 GPCv2 IP block is a part of i.MX7 SoC. Select it to make corresponding driver availible to support DT changes following this patch. Cc: yurovsky@gmail.com Cc: Dong Aisheng Cc: Sascha Hauer Cc: Fabio Estevam Cc: Rob Herring Cc: Mark Rutland Cc: Russell King Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Andrey Smirnov Signed-off-by: Shawn Guo --- arch/arm/mach-imx/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 936c59d0e18b..782699e67600 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -536,6 +536,7 @@ config SOC_IMX7D select HAVE_IMX_ANATOP select HAVE_IMX_MMDC select HAVE_IMX_SRC + select IMX_GPCV2 help This enables support for Freescale i.MX7 Dual processor. -- cgit v1.2.3 From 9be48d2d98810ae723c229c05b078ca5a07e9561 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 16 May 2017 00:40:13 -0700 Subject: ARM: dts: imx7: use 3 PWM cells The PWM driver has now capability to specify the PWM polarity which is e.g. for backlight control. Allow to make use of PWM polarity by specifying pwm-cells to be 3 in the base dt. Signed-off-by: Stefan Agner Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-colibri.dtsi | 2 +- arch/arm/boot/dts/imx7d-nitrogen7.dts | 2 +- arch/arm/boot/dts/imx7s.dtsi | 8 ++++---- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index 2d87489f9105..d7753f79937a 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -43,7 +43,7 @@ / { bl: backlight { compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; }; reg_module_3v3: regulator-module-3v3 { diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index a44f992051ac..dd40e49f6c42 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -67,7 +67,7 @@ backlight-j20 { compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; status = "okay"; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index aa1f4c3e915c..4cf6c458b583 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -635,7 +635,7 @@ clocks = <&clks IMX7D_PWM1_ROOT_CLK>, <&clks IMX7D_PWM1_ROOT_CLK>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -646,7 +646,7 @@ clocks = <&clks IMX7D_PWM2_ROOT_CLK>, <&clks IMX7D_PWM2_ROOT_CLK>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -657,7 +657,7 @@ clocks = <&clks IMX7D_PWM3_ROOT_CLK>, <&clks IMX7D_PWM3_ROOT_CLK>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -668,7 +668,7 @@ clocks = <&clks IMX7D_PWM4_ROOT_CLK>, <&clks IMX7D_PWM4_ROOT_CLK>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; -- cgit v1.2.3 From 23c787a99ff7b42f594722d60ea064534fe54a71 Mon Sep 17 00:00:00 2001 From: Vanessa Maegima Date: Wed, 17 May 2017 14:06:36 -0300 Subject: ARM: dts: imx7d-pico: Add initial support Add the initial support for imx7d-pico board. Add support for eMMC, USB host, USB device, PMIC, Ethernet and audio. For more information about this board, please visit: http://www.technexion.org/products/pico/pico-som/pico-imx7-emmc Signed-off-by: Vanessa Maegima Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx7d-pico.dts | 387 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 388 insertions(+) create mode 100644 arch/arm/boot/dts/imx7d-pico.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7881aaef2d58..cc1267098032 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -478,6 +478,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-cl-som-imx7.dtb \ imx7d-colibri-eval-v3.dtb \ imx7d-nitrogen7.dtb \ + imx7d-pico.dtb \ imx7d-sbc-imx7.dtb \ imx7d-sdb.dtb \ imx7d-sdb-sht11.dtb \ diff --git a/arch/arm/boot/dts/imx7d-pico.dts b/arch/arm/boot/dts/imx7d-pico.dts new file mode 100644 index 000000000000..ebda3dffc270 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-pico.dts @@ -0,0 +1,387 @@ +/* + * Copyright 2017 NXP + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx7d.dtsi" + +/ { + model = "Technexion Pico i.MX7D Board"; + compatible = "technexion,imx7d-pico", "fsl,imx7d"; + + memory { + reg = <0x80000000 0x80000000>; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 5 GPIO_ACTIVE_LOW>; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx7-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + status = "okay"; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@0a { + #sound-dai-cells = <0>; + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_vref_1v8>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + fsl,tuning-step = <2>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 + MX7D_PAD_SD2_WP__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f + MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f + MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 + MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79 + MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79 + >; + }; + + pinctrl_usbotg1_pwr: usbotg_pwr { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + >; + }; +}; -- cgit v1.2.3 From 60490d0a91ab97231d1cfea1f9327a03a596fa8f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 17 May 2017 15:55:25 -0300 Subject: ARM: dts: imx7s-warp: Pass 'no-1-8-v' property to the eMMC Currently the following eMMC error is seen: mmc1: mmc_select_hs200 failed, error -74 mmc1: new MMC card at address 0001 mmcblk1: mmc1:0001 V10008 7.05 GiB mmcblk1boot0: mmc1:0001 V10008 partition 1 4.00 MiB mmcblk1boot1: mmc1:0001 V10008 partition 2 4.00 MiB mmcblk1rpmb: mmc1:0001 V10008 partition 3 4.00 MiB On imx7s-warp the eMMC VCCQ is fixed at 3.15V, so pass the 'no-1-8-v' property to properly describe that 1.8V operation is not possible. With this change HS200 error is gone and another benefit is that the card can operate in DDR52 mode now: mmc1: new DDR MMC card at address 0001 mmcblk1: mmc1:0001 V10008 7.05 GiB mmcblk1boot0: mmc1:0001 V10008 partition 1 4.00 MiB mmcblk1boot1: mmc1:0001 V10008 partition 2 4.00 MiB mmcblk1rpmb: mmc1:0001 V10008 partition 3 4.00 MiB Suggested-by: Stefan Agner Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index d5237fd0fa65..8dfed85471e1 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -295,6 +295,7 @@ assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; assigned-clock-rates = <400000000>; bus-width = <8>; + no-1-8-v; fsl,tuning-step = <2>; non-removable; status = "okay"; -- cgit v1.2.3 From 2a8fbfa5823b80656a4302ea25990f630cccd463 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 21 May 2017 13:10:34 -0300 Subject: ARM: dts: imx6: Fix BCM43xx node name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit "bcrmf" is a typo and "wifi" is the preferred form to describe such node, so change it accordingly. Reported-by: Andreas Färber Signed-off-by: Fabio Estevam Reviewed-by: Andreas Färber Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx-nitrogen6sx.dts | 2 +- arch/arm/boot/dts/imx6ul-opos6ul.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts index 802da45aa551..ac1989e5d5ad 100644 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -374,7 +374,7 @@ cap-sdio-irq; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gpio7>; diff --git a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi b/arch/arm/boot/dts/imx6ul-opos6ul.dtsi index 51095df33a90..aec5ccce0321 100644 --- a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul-opos6ul.dtsi @@ -120,7 +120,7 @@ #address-cells = <1>; #size-cells = <0>; - brcmf: bcrmf@1 { + brcmf: wifi@1 { compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio2>; -- cgit v1.2.3 From f402573fc010fe05fb901ccb6057c4872c392a56 Mon Sep 17 00:00:00 2001 From: Franklin S Cooper Jr Date: Sun, 21 May 2017 22:46:56 -0700 Subject: ARM: dts: keystone-k2g: Remove skeleton.dtsi Adding the unit address to the memory node was causing the below error: Warning (reg_format): "reg" property in /memory has invalid length (8 bytes) (#address-cells == 2, #size-cells == 2) Further debugging showed that this was due to the memory node added by default to skeleton.dtsi which was being included in keystone-k2g.dtsi. Adding a missing node was all that was needed to remove this deprecated dtsi file from the SoC dtsi. With skeleton.dtsi removed the dtc compiler no longer complained about including the unit address for the memory node. Signed-off-by: Franklin S Cooper Jr Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index f59567fe7d91..a789f75a1ed5 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -15,7 +15,6 @@ #include #include -#include "skeleton.dtsi" / { compatible = "ti,k2g","ti,keystone"; @@ -24,6 +23,8 @@ #size-cells = <2>; interrupt-parent = <&gic>; + chosen { }; + aliases { serial0 = &uart0; }; -- cgit v1.2.3 From 99d20cf520731daac427e27bab71a6d98d3751c4 Mon Sep 17 00:00:00 2001 From: Franklin S Cooper Jr Date: Sun, 21 May 2017 22:46:56 -0700 Subject: ARM: dts: k2g-evm: Add unit address to memory node With the new Keystone 2 Industrial Communication EVM adding the unit address to the memory node it made sense to add it for this board also. Signed-off-by: Franklin S Cooper Jr Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g-evm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts index 692fcbb1434a..61883cb969d2 100644 --- a/arch/arm/boot/dts/keystone-k2g-evm.dts +++ b/arch/arm/boot/dts/keystone-k2g-evm.dts @@ -20,7 +20,7 @@ compatible = "ti,k2g-evm", "ti,k2g", "ti,keystone"; model = "Texas Instruments K2G General Purpose EVM"; - memory { + memory@800000000 { device_type = "memory"; reg = <0x00000008 0x00000000 0x00000000 0x80000000>; }; -- cgit v1.2.3 From 84e00e244176baec37c66b1cbee6b8a2f7dbd76f Mon Sep 17 00:00:00 2001 From: Franklin S Cooper Jr Date: Sun, 21 May 2017 22:46:56 -0700 Subject: ARM: dts: keystone: Add minimum support for K2G ICE evm Add barebones dts support for TI's K2G Industrial Communication Engine evm. This dts allows the board to boot using a ram based filesystem. Signed-off-by: Franklin S Cooper Jr Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/Makefile | 3 ++- arch/arm/boot/dts/keystone-k2g-ice.dts | 35 ++++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/keystone-k2g-ice.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9c5e1d944d1c..8db25d9e4399 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -204,7 +204,8 @@ dtb-$(CONFIG_ARCH_KEYSTONE) += \ keystone-k2hk-evm.dtb \ keystone-k2l-evm.dtb \ keystone-k2e-evm.dtb \ - keystone-k2g-evm.dtb + keystone-k2g-evm.dtb \ + keystone-k2g-ice.dtb dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-b3.dtb \ kirkwood-blackarmor-nas220.dtb \ diff --git a/arch/arm/boot/dts/keystone-k2g-ice.dts b/arch/arm/boot/dts/keystone-k2g-ice.dts new file mode 100644 index 000000000000..d820d37b5148 --- /dev/null +++ b/arch/arm/boot/dts/keystone-k2g-ice.dts @@ -0,0 +1,35 @@ +/* + * Device Tree Source for K2G Industrial Communication Engine EVM + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0 + */ +/dts-v1/; + +#include "keystone-k2g.dtsi" + +/ { + compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone"; + model = "Texas Instruments K2G Industrial Communication EVM"; + + memory@800000000 { + device_type = "memory"; + reg = <0x00000008 0x00000000 0x00000000 0x20000000>; + }; +}; + +&k2g_pinctrl { + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; -- cgit v1.2.3 From e5b558a5b2296009574f9237185f4e139f4b50f9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 21 May 2017 18:16:55 -0300 Subject: ARM: dts: sunxi: Fix BCM43xx node name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit "bcrmf" is a typo and "wifi" is the preferred form to describe such node, so change it accordingly. Reported-by: Andreas Färber Reviewed-by: Chen-Yu Tsai Signed-off-by: Fabio Estevam Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 2 +- arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts | 2 +- arch/arm/boot/dts/sun7i-a20-bananapro.dts | 2 +- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 2 +- arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 2 +- arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts | 2 +- arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts index bdfdce8ca6ba..51e6f1d21c32 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts +++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts @@ -138,7 +138,7 @@ non-removable; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&r_pio>; diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts index 08e776ae095a..4c03cc3fd7b3 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts @@ -172,7 +172,7 @@ wakeup-source; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; diff --git a/arch/arm/boot/dts/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/sun7i-a20-bananapro.dts index 83516bc81225..e7af1b7c33d5 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapro.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapro.dts @@ -172,7 +172,7 @@ non-removable; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 4ebeecf9c3d7..8dbf732c7aa9 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -195,7 +195,7 @@ non-removable; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts index e5cbcad3a556..55809973a568 100644 --- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts +++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts @@ -173,7 +173,7 @@ non-removable; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; diff --git a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts index 84462d7961f5..7f8405a0dd0f 100644 --- a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts +++ b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts @@ -137,7 +137,7 @@ non-removable; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts index 17c7c088cdea..883072b611fa 100644 --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts @@ -130,7 +130,7 @@ non-removable; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; -- cgit v1.2.3 From 749b7a9775a63bc8b87bbbe185d849df4c39158d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 22 May 2017 14:25:50 +0800 Subject: ARM: sun8i: a83t: Add device node for DMA controller The A83T SoC has a DMA controller that supports 8 DMA channels to and from various peripherals. Add a device node for it. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index e12dd7170b8f..47196feda26b 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -163,6 +163,15 @@ #size-cells = <1>; ranges; + dma: dma-controller@1c02000 { + compatible = "allwinner,sun8i-a83t-dma"; + reg = <0x01c02000 0x1000>; + interrupts = ; + clocks = <&ccu 21>; + resets = <&ccu 7>; + #dma-cells = <1>; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-a83t-ccu"; reg = <0x01c20000 0x400>; -- cgit v1.2.3 From 9ecf12302cd2baaba2dfedc0173978ab37416866 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 22 May 2017 14:25:51 +0800 Subject: ARM: sun8i: a83t: Add device node for SPDIF transmitter The A83T SoC has an SPDIF transmitter block. According to the vendor BSP kernel, it is compatible with the one found on the H3 SoC. Add a device node and pinmux setting for it. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 47196feda26b..1dc4cfe81534 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -202,6 +202,11 @@ bias-pull-up; }; + spdif_tx_pin: spdif-tx-pin { + pins = "PE18"; + function = "spdif"; + }; + uart0_pb_pins: uart0-pb-pins { pins = "PB9", "PB10"; function = "uart0"; @@ -228,6 +233,22 @@ clocks = <&osc24M>; }; + spdif: spdif@1c21000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-a83t-spdif", + "allwinner,sun8i-h3-spdif"; + reg = <0x01c21000 0x400>; + interrupts = ; + clocks = <&ccu 44>, <&ccu 76>; + resets = <&ccu 32>; + clock-names = "apb", "spdif"; + dmas = <&dma 2>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pin>; + status = "disabled"; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; -- cgit v1.2.3 From 54f3b7f051d6467b8eaccaf0abee4669785a1b31 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 22 May 2017 12:03:34 +0800 Subject: ARM: sun8i: a83t: cubietruck-plus: Add LED device nodes The Cubietruck Plus has 4 LEDs in different colors. Add device nodes for them. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts index d2614f101ecc..9e10cc6f39d4 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -45,6 +45,8 @@ /dts-v1/; #include "sun8i-a83t.dtsi" +#include + / { model = "Cubietech Cubietruck Plus"; compatible = "cubietech,cubietruck-plus", "allwinner,sun8i-a83t"; @@ -56,6 +58,30 @@ chosen { stdout-path = "serial0:115200n8"; }; + + leds { + compatible = "gpio-leds"; + + blue { + label = "cubietruck-plus:blue:usr"; + gpios = <&pio 3 25 GPIO_ACTIVE_HIGH>; /* PD25 */ + }; + + orange { + label = "cubietruck-plus:orange:usr"; + gpios = <&pio 3 26 GPIO_ACTIVE_HIGH>; /* PD26 */ + }; + + white { + label = "cubietruck-plus:white:usr"; + gpios = <&pio 3 27 GPIO_ACTIVE_HIGH>; /* PD27 */ + }; + + green { + label = "cubietruck-plus:green:usr"; + gpios = <&pio 4 4 GPIO_ACTIVE_HIGH>; /* PE4 */ + }; + }; }; &uart0 { -- cgit v1.2.3 From beea147ecdc3bcf3d6cf6006a65e00cc29c27f73 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 22 May 2017 14:25:52 +0800 Subject: ARM: sun8i: a83t: cubietruck-plus: Enable SPDIF output The Cubietruck Plus has an optical SPDIF out connector. Enable SPDIF audio output for this board. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts index 9e10cc6f39d4..cff33454fc24 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -82,6 +82,28 @@ gpios = <&pio 4 4 GPIO_ACTIVE_HIGH>; /* PE4 */ }; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; +}; + +&spdif { + status = "okay"; }; &uart0 { -- cgit v1.2.3 From f97f03578b997a8ec2b9bc4928f958a865137268 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 16 May 2017 17:13:45 -0500 Subject: ARM: davinci: da8xx: Create DSP device only when assigned memory The DSP device on Davinci platforms does not have an MMU and requires specific DDR memory to boot. This memory is reserved using the rproc_mem kernel boot parameter and is assigned to the device on non-DT boots. The remoteproc core uses the DMA API and so will fall back to assigning random memory if this memory is not assigned to the device, but the DSP remote processor boot will not be successful in such cases. So, check that memory has been reserved and assigned to the device specifically before even creating the DSP device. Signed-off-by: Suman Anna Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/devices-da8xx.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 7cf529ffbe5a..1ccf52e49886 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -814,6 +814,8 @@ static struct platform_device da8xx_dsp = { .resource = da8xx_rproc_resources, }; +static bool rproc_mem_inited __initdata; + #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC) static phys_addr_t rproc_base __initdata; @@ -852,6 +854,8 @@ void __init da8xx_rproc_reserve_cma(void) ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0); if (ret) pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret); + else + rproc_mem_inited = true; } #else @@ -866,6 +870,12 @@ int __init da8xx_register_rproc(void) { int ret; + if (!rproc_mem_inited) { + pr_warn("%s: memory not reserved for DSP, not registering DSP device\n", + __func__); + return -ENOMEM; + } + ret = platform_device_register(&da8xx_dsp); if (ret) pr_err("%s: can't register DSP device: %d\n", __func__, ret); -- cgit v1.2.3 From 6724a05ff35f95266c5746db0d7185269eec8282 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 16 May 2017 17:13:46 -0500 Subject: ARM: davinci: da8xx: Add names to DSP IOMEM resources Add names to the IOMEM resources for the DSP device present on DA8xx SoCs. This will facilitate the driver to use the names and be agnostic of the resource order, and facilitate scalable DT support in follow-up patches. Signed-off-by: Suman Anna Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/devices-da8xx.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 1ccf52e49886..74c76538cda3 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -789,11 +789,13 @@ int __init da850_register_mmcsd1(struct davinci_mmc_config *config) static struct resource da8xx_rproc_resources[] = { { /* DSP boot address */ + .name = "host1cfg", .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG, .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3, .flags = IORESOURCE_MEM, }, { /* DSP interrupt registers */ + .name = "chipsig", .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG, .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7, .flags = IORESOURCE_MEM, -- cgit v1.2.3 From 14ff86bc76be9b5c96f06ce141c8bdd612dafd64 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 16 May 2017 17:13:47 -0500 Subject: ARM: davinci: da8xx: Add DSP internal RAM memories as IOMEM resources The DSP subsystem on DA8xx has various internal RAM memories that can accessed from the ARM side. These memories can be configured to be used as either RAM or Cache. Add these memories as IOMEM resources to the DSP device so that the driver can support loading of images into internal memories. Signed-off-by: Suman Anna Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/devices-da8xx.c | 18 ++++++++++++++++++ arch/arm/mach-davinci/include/mach/da8xx.h | 5 +++++ 2 files changed, 23 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 74c76538cda3..22440c05d66a 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -800,6 +800,24 @@ static struct resource da8xx_rproc_resources[] = { .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7, .flags = IORESOURCE_MEM, }, + { /* DSP L2 RAM */ + .name = "l2sram", + .start = DA8XX_DSP_L2_RAM_BASE, + .end = DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1, + .flags = IORESOURCE_MEM, + }, + { /* DSP L1P RAM */ + .name = "l1pram", + .start = DA8XX_DSP_L1P_RAM_BASE, + .end = DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, + { /* DSP L1D RAM */ + .name = "l1dram", + .start = DA8XX_DSP_L1D_RAM_BASE, + .end = DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, { /* dsp irq */ .start = IRQ_DA8XX_CHIPINT0, .end = IRQ_DA8XX_CHIPINT0, diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 7e464228948b..93ff1569cee5 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -75,6 +75,11 @@ extern unsigned int da850_max_speed; #define DA8XX_VPIF_BASE 0x01e17000 #define DA8XX_GPIO_BASE 0x01e26000 #define DA8XX_PSC1_BASE 0x01e27000 + +#define DA8XX_DSP_L2_RAM_BASE 0x11800000 +#define DA8XX_DSP_L1P_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x600000) +#define DA8XX_DSP_L1D_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x700000) + #define DA8XX_AEMIF_CS2_BASE 0x60000000 #define DA8XX_AEMIF_CS3_BASE 0x62000000 #define DA8XX_AEMIF_CTL_BASE 0x68000000 -- cgit v1.2.3 From 7fc32564f57efc2b30871652aaef956805aebc95 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Thu, 18 May 2017 16:31:30 +0530 Subject: ARM: davinci_all_defconfig: cleanup with savedefconfig davinci_all_defconfig is out of sync with savedefconfig in some places. Regenerate the default settings by: $ make davinci_all_config $ make savedefconfig $ cp defconfig arch/arm/configs/davinci_all_defconfig Signed-off-by: Sekhar Nori --- arch/arm/configs/davinci_all_defconfig | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index 88575865c241..3d23356e2ebe 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig @@ -83,14 +83,13 @@ CONFIG_NETCONSOLE=y CONFIG_TUN=m CONFIG_DM9000=y CONFIG_TI_DAVINCI_EMAC=y +CONFIG_LSI_ET1011C_PHY=y CONFIG_LXT_PHY=y CONFIG_SMSC_PHY=y -CONFIG_LSI_ET1011C_PHY=y CONFIG_PPP=m CONFIG_PPP_DEFLATE=m CONFIG_PPP_ASYNC=m CONFIG_PPP_SYNC_TTY=m -# CONFIG_INPUT_MOUSEDEV is not set CONFIG_INPUT_EVDEV=m CONFIG_INPUT_EVBUG=m CONFIG_KEYBOARD_ATKBD=m @@ -237,7 +236,6 @@ CONFIG_NLS_ASCII=m CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=m CONFIG_DEBUG_FS=y -CONFIG_TIMER_STATS=y CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_MUTEXES=y # CONFIG_ARM_UNWIND is not set -- cgit v1.2.3 From 2ad060cf341ab54ed49f351b7bcdd8a585d792f3 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Thu, 18 May 2017 16:31:31 +0530 Subject: ARM: davinci_all_defconfig: enable USB audio/video device support Enable support for USB audio and video camera devices. Tested on OMAP-L138 LCDK using Logitech webcam and Plantronics headset. Signed-off-by: Sekhar Nori --- arch/arm/configs/davinci_all_defconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index 3d23356e2ebe..8b16482f27f1 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig @@ -131,6 +131,8 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_TPS6507X=y CONFIG_MEDIA_SUPPORT=m CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_VIDEO_DAVINCI_VPIF_DISPLAY=m CONFIG_VIDEO_DAVINCI_VPIF_CAPTURE=m @@ -147,6 +149,7 @@ CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y CONFIG_SOUND=m CONFIG_SND=m +CONFIG_SND_USB_AUDIO=m CONFIG_SND_SOC=m CONFIG_SND_EDMA_SOC=m CONFIG_SND_DA850_SOC_EVM=m -- cgit v1.2.3 From 64ac43e6fa283f556f0a8f69ad52d6e7d550307d Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Mon, 15 May 2017 11:24:25 +0200 Subject: gpio: mcp23s08: move to pinctrl This moves the mcp23s08 driver from gpio to pinctrl. Actual pinctrl support for configuration of the pull-up resistors follows in its own patch. Signed-off-by: Sebastian Reichel Acked-by: Sylvain Lemieux Signed-off-by: Linus Walleij --- arch/arm/configs/lpc32xx_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig index 6ba430d2b5b2..e15fa5f168bb 100644 --- a/arch/arm/configs/lpc32xx_defconfig +++ b/arch/arm/configs/lpc32xx_defconfig @@ -112,7 +112,7 @@ CONFIG_GPIO_SX150X=y CONFIG_GPIO_74X164=y CONFIG_GPIO_MAX7301=y CONFIG_GPIO_MC33880=y -CONFIG_GPIO_MCP23S08=y +CONFIG_PINCTRL_MCP23S08=y CONFIG_SENSORS_DS620=y CONFIG_SENSORS_MAX6639=y CONFIG_WATCHDOG=y -- cgit v1.2.3 From 5976a66913a8bf42465d96776fd37fb5631edc19 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 16 May 2017 20:42:33 +0200 Subject: arm: Adjust system_state check To enable smp_processor_id() and might_sleep() debug checks earlier, it's required to add system states between SYSTEM_BOOTING and SYSTEM_RUNNING. Adjust the system_state check in ipi_cpu_stop() to handle the extra states. Signed-off-by: Thomas Gleixner Signed-off-by: Peter Zijlstra (Intel) Cc: Greg Kroah-Hartman Cc: Linus Torvalds Cc: Mark Rutland Cc: Peter Zijlstra Cc: Russell King Cc: Steven Rostedt Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/20170516184735.020718977@linutronix.de Signed-off-by: Ingo Molnar --- arch/arm/kernel/smp.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 572a8df1b766..c9a0a5299827 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -555,8 +555,7 @@ static DEFINE_RAW_SPINLOCK(stop_lock); */ static void ipi_cpu_stop(unsigned int cpu) { - if (system_state == SYSTEM_BOOTING || - system_state == SYSTEM_RUNNING) { + if (system_state <= SYSTEM_RUNNING) { raw_spin_lock(&stop_lock); pr_crit("CPU%u: stopping\n", cpu); dump_stack(); -- cgit v1.2.3 From 0a848d638a25b4f2767b260ed83c271854e93cce Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Sun, 21 May 2017 23:57:25 +0200 Subject: gpio: max732x: move header file out of I2C realm include/linux/i2c is not for client devices. Move the header file to a more appropriate location. Signed-off-by: Wolfram Sang Signed-off-by: Linus Walleij --- arch/arm/mach-pxa/littleton.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index 051c554776a6..fae38fdc8d8e 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include -- cgit v1.2.3 From b6480faeee234829b315168aebcb281ecf95f178 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Sun, 21 May 2017 23:57:26 +0200 Subject: gpio: pcf857x: move header file out of I2C realm include/linux/i2c is not for client devices. Move the header file to a more appropriate location. Signed-off-by: Wolfram Sang Signed-off-by: Linus Walleij --- arch/arm/mach-davinci/board-da830-evm.c | 2 +- arch/arm/mach-davinci/board-dm644x-evm.c | 2 +- arch/arm/mach-davinci/board-dm646x-evm.c | 2 +- arch/arm/mach-pxa/balloon3.c | 2 +- arch/arm/mach-pxa/stargate2.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index 58075627c6df..f673cd7a6766 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index 20f1874a5657..70e00dbeec96 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index cb176826d1cb..ca69d0b96a4f 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index d452a49c0396..1467c1d1e541 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c index 7b6610e9dae4..2d45d18b1a5e 100644 --- a/arch/arm/mach-pxa/stargate2.c +++ b/arch/arm/mach-pxa/stargate2.c @@ -26,7 +26,7 @@ #include #include -#include +#include #include #include #include -- cgit v1.2.3 From abd7229626b9339e378a8cfcdebe0c0943b06a7f Mon Sep 17 00:00:00 2001 From: Christoffer Dall Date: Sat, 6 May 2017 20:01:24 +0200 Subject: KVM: arm/arm64: Simplify active_change_prepare and plug race We don't need to stop a specific VCPU when changing the active state, because private IRQs can only be modified by a running VCPU for the VCPU itself and it is therefore already stopped. However, it is also possible for two VCPUs to be modifying the active state of SPIs at the same time, which can cause the thread being stuck in the loop that checks other VCPU threads for a potentially very long time, or to modify the active state of a running VCPU. Fix this by serializing all accesses to setting and clearing the active state of interrupts using the KVM mutex. Reported-by: Andrew Jones Signed-off-by: Christoffer Dall Reviewed-by: Marc Zyngier --- arch/arm/include/asm/kvm_host.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h index f0e66577ce05..12274d46df70 100644 --- a/arch/arm/include/asm/kvm_host.h +++ b/arch/arm/include/asm/kvm_host.h @@ -233,8 +233,6 @@ struct kvm_vcpu *kvm_arm_get_running_vcpu(void); struct kvm_vcpu __percpu **kvm_get_running_vcpus(void); void kvm_arm_halt_guest(struct kvm *kvm); void kvm_arm_resume_guest(struct kvm *kvm); -void kvm_arm_halt_vcpu(struct kvm_vcpu *vcpu); -void kvm_arm_resume_vcpu(struct kvm_vcpu *vcpu); int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices); unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu); -- cgit v1.2.3 From 801f19b9515fb61e8b2400f5555460f55f22571c Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Thu, 4 May 2017 09:17:55 +0100 Subject: ARM: 8673/1: Fix __show_regs output timestamps Multiple line formats are not preferred as the second and subsequent lines may not have timestamps. Lacking timestamps makes reading the output a bit difficult. This also makes arm/arm64 output more similar. Previous: [ 1514.093231] pc : [] lr : [] psr: a00f0013 sp : ecdd7e20 ip : 00000000 fp : ffffffff New: [ 1514.093231] pc : [] lr : [] psr: a00f0013 [ 1514.105316] sp : ecdd7e20 ip : 00000000 fp : ffffffff Signed-off-by: Joe Perches Signed-off-by: Russell King --- arch/arm/kernel/process.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 939e8b58c59d..151cece4a293 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -123,10 +123,10 @@ void __show_regs(struct pt_regs *regs) print_symbol("PC is at %s\n", instruction_pointer(regs)); print_symbol("LR is at %s\n", regs->ARM_lr); - printk("pc : [<%08lx>] lr : [<%08lx>] psr: %08lx\n" - "sp : %08lx ip : %08lx fp : %08lx\n", - regs->ARM_pc, regs->ARM_lr, regs->ARM_cpsr, - regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printk("pc : [<%08lx>] lr : [<%08lx>] psr: %08lx\n", + regs->ARM_pc, regs->ARM_lr, regs->ARM_cpsr); + printk("sp : %08lx ip : %08lx fp : %08lx\n", + regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); printk("r10: %08lx r9 : %08lx r8 : %08lx\n", regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); -- cgit v1.2.3 From 4166a56aa8d5babe979d8e0834a741c9f015ad14 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 20 May 2017 23:42:50 +0200 Subject: ARM/dmaengine: pl08x: pass reasonable memcpy settings We cannot use bits from configuration registers as API between platforms and driver like this, abstract it out to two enums and mimic the stuff passed as device tree data. This is done to make it possible for the driver to generate the ccfg word on-the-fly so we can support more PL08x derivatives. Acked-by: Olof Johansson Acked-by: Arnd Bergmann Signed-off-by: Linus Walleij Signed-off-by: Vinod Koul --- arch/arm/mach-lpc32xx/phy3250.c | 3 +++ arch/arm/mach-s3c64xx/pl080.c | 28 ++++++++-------------------- arch/arm/mach-spear/spear3xx.c | 14 ++++---------- arch/arm/mach-spear/spear6xx.c | 14 ++++---------- 4 files changed, 19 insertions(+), 40 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index 6c52bd32610e..e48cc06c2aec 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -137,6 +137,9 @@ static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch) } static struct pl08x_platform_data pl08x_pd = { + /* Some reasonable memcpy defaults */ + .memcpy_burst_size = PL08X_BURST_SZ_256, + .memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS, .slave_channels = &pl08x_slave_channels[0], .num_slave_channels = ARRAY_SIZE(pl08x_slave_channels), .get_xfer_signal = pl08x_get_signal, diff --git a/arch/arm/mach-s3c64xx/pl080.c b/arch/arm/mach-s3c64xx/pl080.c index 261820a855ec..66fc774b70ec 100644 --- a/arch/arm/mach-s3c64xx/pl080.c +++ b/arch/arm/mach-s3c64xx/pl080.c @@ -137,16 +137,10 @@ static const struct dma_slave_map s3c64xx_dma0_slave_map[] = { }; struct pl08x_platform_data s3c64xx_dma0_plat_data = { - .memcpy_channel = { - .bus_id = "memcpy", - .cctl_memcpy = - (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT | - PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT | - PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | - PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | - PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | - PL080_CONTROL_PROT_SYS), - }, + .memcpy_burst_size = PL08X_BURST_SZ_4, + .memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS, + .memcpy_prot_buff = true, + .memcpy_prot_cache = true, .lli_buses = PL08X_AHB1, .mem_buses = PL08X_AHB1, .get_xfer_signal = pl08x_get_xfer_signal, @@ -238,16 +232,10 @@ static const struct dma_slave_map s3c64xx_dma1_slave_map[] = { }; struct pl08x_platform_data s3c64xx_dma1_plat_data = { - .memcpy_channel = { - .bus_id = "memcpy", - .cctl_memcpy = - (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT | - PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT | - PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | - PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | - PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | - PL080_CONTROL_PROT_SYS), - }, + .memcpy_burst_size = PL08X_BURST_SZ_4, + .memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS, + .memcpy_prot_buff = true, + .memcpy_prot_cache = true, .lli_buses = PL08X_AHB1, .mem_buses = PL08X_AHB1, .get_xfer_signal = pl08x_get_xfer_signal, diff --git a/arch/arm/mach-spear/spear3xx.c b/arch/arm/mach-spear/spear3xx.c index 23394ac76cf2..8537fcffe5a8 100644 --- a/arch/arm/mach-spear/spear3xx.c +++ b/arch/arm/mach-spear/spear3xx.c @@ -44,16 +44,10 @@ struct pl022_ssp_controller pl022_plat_data = { /* dmac device registration */ struct pl08x_platform_data pl080_plat_data = { - .memcpy_channel = { - .bus_id = "memcpy", - .cctl_memcpy = - (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \ - PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \ - PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \ - PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \ - PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \ - PL080_CONTROL_PROT_SYS), - }, + .memcpy_burst_size = PL08X_BURST_SZ_16, + .memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS, + .memcpy_prot_buff = true, + .memcpy_prot_cache = true, .lli_buses = PL08X_AHB1, .mem_buses = PL08X_AHB1, .get_xfer_signal = pl080_get_signal, diff --git a/arch/arm/mach-spear/spear6xx.c b/arch/arm/mach-spear/spear6xx.c index ccf3573b831c..c5fc110134ba 100644 --- a/arch/arm/mach-spear/spear6xx.c +++ b/arch/arm/mach-spear/spear6xx.c @@ -322,16 +322,10 @@ static struct pl08x_channel_data spear600_dma_info[] = { }; static struct pl08x_platform_data spear6xx_pl080_plat_data = { - .memcpy_channel = { - .bus_id = "memcpy", - .cctl_memcpy = - (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \ - PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \ - PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \ - PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \ - PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \ - PL080_CONTROL_PROT_SYS), - }, + .memcpy_burst_size = PL08X_BURST_SZ_16, + .memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS, + .memcpy_prot_buff = true, + .memcpy_prot_cache = true, .lli_buses = PL08X_AHB1, .mem_buses = PL08X_AHB1, .get_xfer_signal = pl080_get_signal, -- cgit v1.2.3 From 3863c5289920c7ac0df56830aeee0c1b7566f35d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 13 Apr 2017 16:09:53 +0200 Subject: ARM: dts: Add the Gemini reset controller This adds the Gemini reset controller to the Gemini SoC DTSI file and also adds the reset references to all existing blocks already in the device tree. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini.dtsi | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index b8d011bdcc76..dadc8412243e 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -25,8 +25,10 @@ }; syscon: syscon@40000000 { - compatible = "cortina,gemini-syscon", "syscon", "simple-mfd"; + compatible = "cortina,gemini-syscon", + "syscon", "simple-mfd"; reg = <0x40000000 0x1000>; + #reset-cells = <1>; syscon-reboot { compatible = "syscon-reboot"; @@ -42,11 +44,13 @@ compatible = "cortina,gemini-watchdog"; reg = <0x41000000 0x1000>; interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + resets = <&syscon 23>; }; uart0: serial@42000000 { compatible = "ns16550a"; reg = <0x42000000 0x100>; + resets = <&syscon 18>; clock-frequency = <48000000>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; @@ -59,6 +63,7 @@ interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */ <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */ <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */ + resets = <&syscon 17>; syscon = <&syscon>; }; @@ -66,11 +71,13 @@ compatible = "cortina,gemini-rtc"; reg = <0x45000000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + resets = <&syscon 16>; }; intcon: interrupt-controller@48000000 { compatible = "faraday,ftintc010"; reg = <0x48000000 0x1000>; + resets = <&syscon 14>; interrupt-controller; #interrupt-cells = <2>; }; @@ -85,6 +92,7 @@ compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; reg = <0x4d000000 0x100>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; + resets = <&syscon 20>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -95,6 +103,7 @@ compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; reg = <0x4e000000 0x100>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + resets = <&syscon 21>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -105,6 +114,7 @@ compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; reg = <0x4f000000 0x100>; interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; + resets = <&syscon 22>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -118,6 +128,7 @@ * to configure the host bridge. */ reg = <0x50000000 0x100>; + resets = <&syscon 7>; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; -- cgit v1.2.3 From 664ed4e283926d753e876a1347b7729135a3f6b8 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 20 Apr 2017 21:43:38 +0200 Subject: ARM: dts: Add clocks to the Gemini SoC We have a clock controller for the Gemini SoC, so make use of the driver and add clocks to the peripherals. Remove the hard-coded frequency from the UART and add switch the timer compatible to the generic that uses the clock framework for clock speed look-up. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index dadc8412243e..80abf84f8a80 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -28,6 +28,7 @@ compatible = "cortina,gemini-syscon", "syscon", "simple-mfd"; reg = <0x40000000 0x1000>; + #clock-cells = <1>; #reset-cells = <1>; syscon-reboot { @@ -45,25 +46,29 @@ reg = <0x41000000 0x1000>; interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; resets = <&syscon 23>; + clocks = <&syscon 2>; }; uart0: serial@42000000 { compatible = "ns16550a"; reg = <0x42000000 0x100>; resets = <&syscon 18>; - clock-frequency = <48000000>; + clocks = <&syscon 6>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; }; timer@43000000 { - compatible = "cortina,gemini-timer"; + compatible = "faraday,fttmr010"; reg = <0x43000000 0x1000>; interrupt-parent = <&intcon>; interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */ <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */ <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */ resets = <&syscon 17>; + /* APB clock or RTC clock */ + clocks = <&syscon 2>, <&syscon 0>; + clock-names = "PCLK", "EXTCLK"; syscon = <&syscon>; }; @@ -72,6 +77,8 @@ reg = <0x45000000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; resets = <&syscon 16>; + clocks = <&syscon 2>, <&syscon 0>; + clock-names = "PCLK", "EXTCLK"; }; intcon: interrupt-controller@48000000 { @@ -93,6 +100,7 @@ reg = <0x4d000000 0x100>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; resets = <&syscon 20>; + clocks = <&syscon 2>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -104,6 +112,7 @@ reg = <0x4e000000 0x100>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; resets = <&syscon 21>; + clocks = <&syscon 2>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -115,6 +124,7 @@ reg = <0x4f000000 0x100>; interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; resets = <&syscon 22>; + clocks = <&syscon 2>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -129,6 +139,8 @@ */ reg = <0x50000000 0x100>; resets = <&syscon 7>; + clocks = <&syscon 15>, <&syscon 4>; + clock-names = "PCLK", "PCICLK"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; -- cgit v1.2.3 From bed8c926d17529c7c0ae14a509db1957d7710c8b Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 24 May 2017 14:02:42 +0900 Subject: ARM: dts: imx6: use #include "..." to include local DT Most of DT files in ARM use #include "..." to make pre-processor include DT in the same directory, but we have some exceptional files that use #include <...> for that. Fix them to remove -I$(srctree)/arch/$(SRCARCH)/boot/dts path from dtc_cpp_flags. Signed-off-by: Masahiro Yamada Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-zii-rdu2.dts | 4 ++-- arch/arm/boot/dts/imx6qp-zii-rdu2.dts | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6q-zii-rdu2.dts b/arch/arm/boot/dts/imx6q-zii-rdu2.dts index b2d346640fd7..6be8a1eea895 100644 --- a/arch/arm/boot/dts/imx6q-zii-rdu2.dts +++ b/arch/arm/boot/dts/imx6q-zii-rdu2.dts @@ -41,8 +41,8 @@ /dts-v1/; -#include -#include +#include "imx6q.dtsi" +#include "imx6qdl-zii-rdu2.dtsi" / { model = "ZII RDU2 Board"; diff --git a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts b/arch/arm/boot/dts/imx6qp-zii-rdu2.dts index 882b3bd97e07..547a76677ab3 100644 --- a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts +++ b/arch/arm/boot/dts/imx6qp-zii-rdu2.dts @@ -41,8 +41,8 @@ /dts-v1/; -#include -#include +#include "imx6qp.dtsi" +#include "imx6qdl-zii-rdu2.dtsi" / { model = "ZII RDU2+ Board"; -- cgit v1.2.3 From 30dd9fb924efccfa080e5cba9cd6c2e1ebbd1822 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Tue, 23 May 2017 15:34:34 +0200 Subject: ARM: dts: imx: Add generic compatible string for I2C EEPROM The at24 driver allows to register I2C EEPROM chips using different vendor and devices, but the I2C subsystem does not take the vendor into account when matching using the I2C table since it only has device entries. But when matching using an OF table, both the vendor and device has to be taken into account so the driver defines only a set of compatible strings using the "atmel" vendor as a generic fallback for compatible I2C devices. So add this generic fallback to the device node compatible string to make the device to match the driver using the OF device ID table. Signed-off-by: Javier Martinez Canillas Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi | 2 +- arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 2 +- arch/arm/boot/dts/imx28-evk.dts | 2 +- arch/arm/boot/dts/imx53-tqma53.dtsi | 2 +- arch/arm/boot/dts/imx6q-cm-fx6.dts | 2 +- arch/arm/boot/dts/imx6q-utilite-pro.dts | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi index 4f3e0f473581..0b8490b21a38 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi @@ -40,7 +40,7 @@ status = "okay"; at24@52 { - compatible = "at,24c32"; + compatible = "atmel,24c32"; pagesize = <32>; reg = <0x52>; }; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi index 82fec935ce83..c973c5d91875 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi @@ -193,7 +193,7 @@ status = "okay"; at24@52 { - compatible = "at,24c32"; + compatible = "atmel,24c32"; pagesize = <32>; reg = <0x52>; }; diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index a5ba669b4eaa..b88c087f1fea 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -203,7 +203,7 @@ }; at24@51 { - compatible = "at24,24c32"; + compatible = "atmel,24c32"; pagesize = <32>; reg = <0x51>; }; diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi index 85972f2201c2..eecdc1c55eef 100644 --- a/arch/arm/boot/dts/imx53-tqma53.dtsi +++ b/arch/arm/boot/dts/imx53-tqma53.dtsi @@ -272,7 +272,7 @@ }; eeprom: 24c64@50 { - compatible = "at,24c64"; + compatible = "atmel,24c64"; pagesize = <32>; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index 66cac5328b86..a8af3822d9df 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -215,7 +215,7 @@ clock-frequency = <100000>; eeprom@50 { - compatible = "at24,24c02"; + compatible = "atmel,24c02"; reg = <0x50>; pagesize = <16>; }; diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/imx6q-utilite-pro.dts index d900ad6ec5f8..16d5be1aeb3c 100644 --- a/arch/arm/boot/dts/imx6q-utilite-pro.dts +++ b/arch/arm/boot/dts/imx6q-utilite-pro.dts @@ -130,7 +130,7 @@ #size-cells = <0>; eeprom@50 { - compatible = "at24,24c02"; + compatible = "atmel,24c02"; reg = <0x50>; pagesize = <16>; }; -- cgit v1.2.3 From d1ceec2a8f6ab1b35c296c3339127adca1ace30b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 23 May 2017 12:16:08 -0300 Subject: ARM: dts: imx7d-pico: Add watchdog support imx7d-pico has the WDOG1_B pin connected to the PMIC, so add the wdog1 node and use the 'fsl,ext-reset-output' property to properly describe it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-pico.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7d-pico.dts b/arch/arm/boot/dts/imx7d-pico.dts index ebda3dffc270..f874352bb496 100644 --- a/arch/arm/boot/dts/imx7d-pico.dts +++ b/arch/arm/boot/dts/imx7d-pico.dts @@ -284,6 +284,13 @@ status = "okay"; }; +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + &iomuxc { pinctrl_enet1: enet1grp { fsl,pins = < @@ -385,3 +392,11 @@ >; }; }; + +&iomuxc_lpsr { + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x74 + >; + }; +}; -- cgit v1.2.3 From bdc111bd50cc1378e113647dc251689636986d84 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 23 May 2017 12:16:09 -0300 Subject: ARM: dts: imx7d-pico: Pass 'no-1-8-v' property to the eMMC Currently the following eMMC error is seen: mmc1: mmc_select_hs200 failed, error -74 On imx7d-pico the eMMC VCCQ is fixed at 3.15V, so pass the 'no-1-8-v' property to properly describe that 1.8V operation is not possible. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-pico.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7d-pico.dts b/arch/arm/boot/dts/imx7d-pico.dts index f874352bb496..79b5d83aaace 100644 --- a/arch/arm/boot/dts/imx7d-pico.dts +++ b/arch/arm/boot/dts/imx7d-pico.dts @@ -279,6 +279,7 @@ assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; assigned-clock-rates = <400000000>; bus-width = <8>; + no-1-8-v; fsl,tuning-step = <2>; non-removable; status = "okay"; -- cgit v1.2.3 From 71ba49902d35d025b3810d6f19028eff624c67a7 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 23 May 2017 12:32:43 -0300 Subject: ARM: dts: imx23-sansa: Remove 'enable-active-low' property Property 'enable-active-low' does not exist. Only 'enable-active-high' is valid, and when this property is absent the gpio regulator will act as active low by default. So remove the unexisting 'enable-active-low' property. Currently the GPIO flag is 0, which means active-high. In order to make the dts description accurate, pass the GPIO_ACTIVE_LOW flag instead. This change is safe because the gpio regulator driver does not take the GPIO flag polarity into account. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx23-sansa.dts | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx23-sansa.dts b/arch/arm/boot/dts/imx23-sansa.dts index 4ec32f4c7885..221fd55e967e 100644 --- a/arch/arm/boot/dts/imx23-sansa.dts +++ b/arch/arm/boot/dts/imx23-sansa.dts @@ -42,6 +42,7 @@ */ /dts-v1/; +#include #include "imx23.dtsi" / { @@ -149,9 +150,8 @@ regulator-name = "vdd-touchpad0"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio0 26 0>; + gpio = <&gpio0 26 GPIO_ACTIVE_LOW>; regulator-always-on; - enable-active-low; }; reg_vdd_tuner: regulator-vdd-tuner0 { @@ -159,9 +159,8 @@ regulator-name = "vdd-tuner0"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio0 29 0>; + gpio = <&gpio0 29 GPIO_ACTIVE_LOW>; regulator-always-on; - enable-active-low; }; backlight { -- cgit v1.2.3 From 8b7be72b1fe93fe78f325312a9ece12b9531efeb Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 23 May 2017 12:32:44 -0300 Subject: ARM: dts: tx6: Remove 'enable-active-low' property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Property 'enable-active-low' does not exist. Only 'enable-active-high' is valid, and when this property is absent the gpio regulator will act as active low by default. So remove the unexisting 'enable-active-low' property. Currently the GPIO flag is GPIO_ACTIVE_HIGH. In order to make the dts description accurate, pass the GPIO_ACTIVE_LOW flag instead. This change is safe because the gpio regulator driver does not take the GPIO flag polarity into account. Signed-off-by: Fabio Estevam Acked-by: Lothar Waßmann Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-tx6.dtsi | 3 +-- arch/arm/boot/dts/imx6ul-tx6ul.dtsi | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index 1691714f13a2..a146fe7fdc5a 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -133,8 +133,7 @@ regulator-max-microvolt = <3300000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan_xcvr>; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - enable-active-low; + gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; }; reg_lcd0_pwr: regulator-lcd0-pwr { diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi index c784a0b75ca0..4ccc9e9d2c29 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi @@ -173,8 +173,7 @@ regulator-max-microvolt = <3300000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan_xcvr>; - gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; - enable-active-low; + gpio = <&gpio3 5 GPIO_ACTIVE_LOW>; }; reg_lcd_pwr: regulator-lcdpwr { -- cgit v1.2.3 From 939fa844a0ee02058ee743981c9e2d350f699dd1 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 26 Jan 2017 16:47:24 -0800 Subject: ARM: dts: qcom: Remove s4/5vs1,2 from RPM pm8941 control These regulators are controlled by the SPMI regulator driver instead of the RPM regulator driver in the downstream android kernel sources. Let's remove them from the DTS here because they'll never be used by the RPM regulator driver. Cc: Bjorn Andersson Signed-off-by: Stephen Boyd Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts | 1 - arch/arm/boot/dts/qcom-msm8974.dtsi | 4 ---- 2 files changed, 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts index e7c1577d56f4..50966378f9e4 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts @@ -92,7 +92,6 @@ vdd_l9_l10_l17_l22-supply = <&vreg_boost>; vdd_l13_l20_l23_l24-supply = <&vreg_boost>; vdd_l21-supply = <&vreg_boost>; - vin_5vs-supply = <&pm8941_5v>; s1 { regulator-min-microvolt = <1300000>; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 307bf6a647b3..0b2014fab4ea 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1021,7 +1021,6 @@ pm8941_s1: s1 {}; pm8941_s2: s2 {}; pm8941_s3: s3 {}; - pm8941_5v: s4 {}; pm8941_l1: l1 {}; pm8941_l2: l2 {}; @@ -1051,9 +1050,6 @@ pm8941_lvs1: lvs1 {}; pm8941_lvs2: lvs2 {}; pm8941_lvs3: lvs3 {}; - - pm8941_5vs1: 5vs1 {}; - pm8941_5vs2: 5vs2 {}; }; }; }; -- cgit v1.2.3 From ffb35d431b7666544994ecef0ef8b2227c20b6da Mon Sep 17 00:00:00 2001 From: "Bird, Tim" Date: Thu, 26 Jan 2017 16:47:25 -0800 Subject: ARM: dts: qcom: add charger otg regulator Add the otg regulator provided by the charger block. Signed-off-by: Tim Bird Reviewed-by: Bjorn Andersson [stephen.boyd@linaro.org: Fix otg supply property name] Signed-off-by: Stephen Boyd Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-pm8941.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi index f8eb5e31c920..6b16b296f0fa 100644 --- a/arch/arm/boot/dts/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom-pm8941.dtsi @@ -45,6 +45,10 @@ "chg-gone", "usb-valid", "dc-valid"; + + usb-otg-in-supply = <&pm8941_5vs1>; + + chg_otg: otg-vbus { }; }; pm8941_gpios: gpios@c000 { -- cgit v1.2.3 From 4ac5a200b06f1522f8bcc7df1e45ee17221d166a Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 26 Jan 2017 16:47:26 -0800 Subject: ARM: dts: qcom-msm8974: Add HS usb node and OTG detection mechanisms This USB controller has two phys, so add them both underneath the ULPI bus, but only enable one of them based on the board configuration. To get OTG to work, we need to add the id and vbus detection info and also populate the regulators for the vbus supply. Signed-off-by: Stephen Boyd Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 20 +++++++++++ arch/arm/boot/dts/qcom-msm8974.dtsi | 50 ++++++++++++++++++++++++++ arch/arm/boot/dts/qcom-pm8941.dtsi | 32 ++++++++++++++++- 3 files changed, 101 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index ad51df27dfb7..32f3b81f609c 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -44,6 +44,26 @@ vqmmc-supply = <&pm8941_l13>; }; + usb@f9a55000 { + status = "ok"; + phys = <&usb_hs2_phy>; + phy-select = <&tcsr 0xb000 1>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; + hnp-disable; + srp-disable; + adp-disable; + ulpi { + phy@b { + status = "ok"; + v3p3-supply = <&pm8941_l24>; + v1p8-supply = <&pm8941_l6>; + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x63>; + }; + }; + }; + pinctrl@fd510000 { i2c11_pins: i2c11 { diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 0b2014fab4ea..c5ee68a3f7f5 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include #include #include "skeleton.dtsi" @@ -551,6 +552,11 @@ reg = <0xfc400000 0x4000>; }; + tcsr: syscon@fd4a0000 { + compatible = "syscon"; + reg = <0xfd4a0000 0x10000>; + }; + tcsr_mutex_block: syscon@fd484000 { compatible = "syscon"; reg = <0xfd484000 0x2000>; @@ -620,6 +626,50 @@ status = "disabled"; }; + otg: usb@f9a55000 { + compatible = "qcom,ci-hdrc"; + reg = <0xf9a55000 0x200>, + <0xf9a55200 0x200>; + interrupts = ; + clocks = <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names = "iface", "core"; + assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <75000000>; + resets = <&gcc GCC_USB_HS_BCR>; + reset-names = "core"; + phy_type = "ulpi"; + dr_mode = "otg"; + ahb-burst-config = <0>; + phy-names = "usb-phy"; + status = "disabled"; + #reset-cells = <1>; + + ulpi { + usb_hs1_phy: phy@a { + compatible = "qcom,usb-hs-phy-msm8974", + "qcom,usb-hs-phy"; + #phy-cells = <0>; + clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "sleep"; + resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>; + reset-names = "phy", "por"; + status = "disabled"; + }; + + usb_hs2_phy: phy@b { + compatible = "qcom,usb-hs-phy-msm8974", + "qcom,usb-hs-phy"; + #phy-cells = <0>; + clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>; + clock-names = "ref", "sleep"; + resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>; + reset-names = "phy", "por"; + status = "disabled"; + }; + }; + }; + rng@f9bff000 { compatible = "qcom,prng"; reg = <0xf9bff000 0x200>; diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi index 6b16b296f0fa..3fc9f34f45bb 100644 --- a/arch/arm/boot/dts/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom-pm8941.dtsi @@ -26,7 +26,14 @@ bias-pull-up; }; - charger@1000 { + usb_id: misc@900 { + compatible = "qcom,pm8941-misc"; + reg = <0x900>; + interrupts = <0x0 0x9 0 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "usb_id"; + }; + + smbb: charger@1000 { compatible = "qcom,pm8941-charger"; reg = <0x1000>; interrupts = <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>, @@ -175,5 +182,28 @@ status = "disabled"; }; + + regulators { + compatible = "qcom,pm8941-regulators"; + interrupts = <0x1 0x83 0x2 0>, <0x1 0x84 0x2 0>; + interrupt-names = "ocp-5vs1", "ocp-5vs2"; + vin_5vs-supply = <&pm8941_5v>; + + pm8941_5v: s4 { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-enable-ramp-delay = <500>; + }; + + pm8941_5vs1: 5vs1 { + regulator-enable-ramp-delay = <1000>; + regulator-pull-down; + regulator-over-current-protection; + qcom,ocp-max-retries = <10>; + qcom,ocp-retry-delay = <30>; + qcom,vs-soft-start-strength = <0>; + regulator-initial-mode = <1>; + }; + }; }; }; -- cgit v1.2.3 From b993292f73dcffd113bd5196bd5898432ddd463d Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 26 Jan 2017 16:47:27 -0800 Subject: ARM: dts: qcom-apq8064: Collapse usb support into one node We currently have three device nodes for the same USB hardware block, as evident by the reuse of the same reg address multiple times. Now that the chipidea driver fully supports OTG with the MSM wrapper we can collapse the three nodes into one USB device node, reflecting the true nature of the hardware. Since we're here, we also mark the irq trigger flags correctly, as IRQ_TYPE_LEVEL_HIGH instead of IRQ_TYPE_NONE. Cc: Bjorn Andersson Cc: Srinivas Kandagatla Cc: Nicolas Dechesne Cc: John Stultz Signed-off-by: Stephen Boyd Signed-off-by: Andy Gross --- .../arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts | 48 +++---- arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 20 +-- arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 53 ++++--- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 53 ++++--- .../arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts | 16 +-- arch/arm/boot/dts/qcom-apq8064.dtsi | 154 ++++++++++++--------- 6 files changed, 169 insertions(+), 175 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts index 8f5de029bca9..f245064f320e 100644 --- a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts +++ b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts @@ -319,44 +319,38 @@ target-supply = <&pm8921_lvs7>; }; - /* OTG */ - phy@12500000 { - status = "okay"; - dr_mode = "peripheral"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; - }; - - phy@12520000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - - phy@12530000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - - gadget@12500000 { - status = "okay"; - }; - /* OTG */ usb@12500000 { status = "okay"; + dr_mode = "peripheral"; + ulpi { + phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l4>; + }; + }; }; usb@12520000 { status = "okay"; + dr_mode = "otg"; + ulpi { + phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + }; + }; }; usb@12530000 { status = "okay"; + dr_mode = "otg"; + ulpi { + phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + }; + }; }; amba { diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts index e39440a86739..3483a66e44c1 100644 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts @@ -320,22 +320,16 @@ }; }; - /* OTG */ - phy@12500000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; - dr_mode = "otg"; - }; - - gadget@12500000 { - status = "okay"; - }; - /* OTG */ usb@12500000 { status = "okay"; + dr_mode = "otg"; + ulpi { + phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l4>; + }; + }; }; amba { diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts index 35f1d46edded..5b151e425530 100644 --- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts +++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts @@ -150,42 +150,37 @@ }; /* OTG */ - usb1_phy: phy@12500000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; - }; - - usb3_phy: phy@12520000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - - usb4_phy: phy@12530000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - - gadget1: gadget@12500000 { - status = "ok"; - }; - - /* OTG */ - usb1: usb@12500000 { + usb@12500000 { status = "ok"; + dr_mode = "otg"; + ulpi { + phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l4>; + }; + }; }; - usb3: usb@12520000 { + usb@12520000 { status = "okay"; + dr_mode = "host"; + ulpi { + phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + }; + }; }; - usb4: usb@12530000 { + usb@12530000 { status = "okay"; + dr_mode = "host"; + ulpi { + phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + }; + }; }; /* on board fixed 3.3v supply */ diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 881ce707311a..053b5bdd7808 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -244,42 +244,37 @@ }; /* OTG */ - usb1_phy: phy@12500000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; - }; - - usb3_phy: phy@12520000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - - usb4_phy: phy@12530000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - - gadget1: gadget@12500000 { - status = "okay"; - }; - - /* OTG */ - usb1: usb@12500000 { + usb@12500000 { status = "okay"; + dr_mode = "otg"; + ulpi { + phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l4>; + }; + }; }; - usb3: usb@12520000 { + usb@12520000 { status = "okay"; + dr_mode = "host"; + ulpi { + phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + }; + }; }; - usb4: usb@12530000 { + usb@12530000 { status = "okay"; + dr_mode = "host"; + ulpi { + phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + }; + }; }; pci@1b500000 { diff --git a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts index a34ba3555454..88a9aff41e2f 100644 --- a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts +++ b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts @@ -349,15 +349,15 @@ }; }; - phy@12500000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; - }; - - gadget@12500000 { + usb@12500000 { status = "okay"; + dr_mode = "otg"; + ulpi { + phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l4>; + }; + }; }; gsbi@1a200000 { diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 14a6f5ed02de..f3db185a6809 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -197,7 +197,7 @@ clock-frequency = <27000000>; }; - sleep_clk { + sleep_clk: sleep_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; @@ -884,81 +884,97 @@ }; }; - usb1_phy: phy@12500000 { - compatible = "qcom,usb-otg-ci"; - reg = <0x12500000 0x400>; - interrupts = ; - status = "disabled"; - - clocks = <&gcc USB_HS1_XCVR_CLK>, - <&gcc USB_HS1_H_CLK>; - clock-names = "core", "iface"; - - resets = <&gcc USB_HS1_RESET>; - reset-names = "link"; - }; - - usb3_phy: phy@12520000 { - compatible = "qcom,usb-otg-ci"; - reg = <0x12520000 0x400>; - interrupts = ; - status = "disabled"; - dr_mode = "host"; - - clocks = <&gcc USB_HS3_XCVR_CLK>, - <&gcc USB_HS3_H_CLK>; - clock-names = "core", "iface"; - - resets = <&gcc USB_HS3_RESET>; - reset-names = "link"; - }; - - usb4_phy: phy@12530000 { - compatible = "qcom,usb-otg-ci"; - reg = <0x12530000 0x400>; - interrupts = ; - status = "disabled"; - dr_mode = "host"; - - clocks = <&gcc USB_HS4_XCVR_CLK>, - <&gcc USB_HS4_H_CLK>; - clock-names = "core", "iface"; - - resets = <&gcc USB_HS4_RESET>; - reset-names = "link"; - }; - - gadget1: gadget@12500000 { - compatible = "qcom,ci-hdrc"; - reg = <0x12500000 0x400>; - status = "disabled"; - dr_mode = "peripheral"; - interrupts = ; - usb-phy = <&usb1_phy>; - }; - usb1: usb@12500000 { - compatible = "qcom,ehci-host"; - reg = <0x12500000 0x400>; - interrupts = ; - status = "disabled"; - usb-phy = <&usb1_phy>; + compatible = "qcom,ci-hdrc"; + reg = <0x12500000 0x200>, + <0x12500200 0x200>; + interrupts = ; + clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; + clock-names = "core", "iface"; + assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; + assigned-clock-rates = <60000000>; + resets = <&gcc USB_HS1_RESET>; + reset-names = "core"; + phy_type = "ulpi"; + ahb-burst-config = <0>; + phys = <&usb_hs1_phy>; + phy-names = "usb-phy"; + status = "disabled"; + #reset-cells = <1>; + + ulpi { + usb_hs1_phy: phy { + compatible = "qcom,usb-hs-phy-apq8064", + "qcom,usb-hs-phy"; + #phy-cells = <0>; + clocks = <&sleep_clk>, <&cxo_board>; + clock-names = "sleep", "ref"; + resets = <&usb1 0>; + reset-names = "por"; + }; + }; }; usb3: usb@12520000 { - compatible = "qcom,ehci-host"; - reg = <0x12520000 0x400>; - interrupts = ; - status = "disabled"; - usb-phy = <&usb3_phy>; + compatible = "qcom,ci-hdrc"; + reg = <0x12520000 0x200>, + <0x12520200 0x200>; + interrupts = ; + clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>; + clock-names = "core", "iface"; + assigned-clocks = <&gcc USB_HS3_XCVR_CLK>; + assigned-clock-rates = <60000000>; + resets = <&gcc USB_HS3_RESET>; + reset-names = "core"; + phy_type = "ulpi"; + ahb-burst-config = <0>; + phys = <&usb_hs3_phy>; + phy-names = "usb-phy"; + status = "disabled"; + #reset-cells = <1>; + + ulpi { + usb_hs3_phy: phy { + compatible = "qcom,usb-hs-phy-apq8064", + "qcom,usb-hs-phy"; + #phy-cells = <0>; + clocks = <&sleep_clk>, <&cxo_board>; + clock-names = "sleep", "ref"; + resets = <&usb3 0>; + reset-names = "por"; + }; + }; }; usb4: usb@12530000 { - compatible = "qcom,ehci-host"; - reg = <0x12530000 0x400>; - interrupts = ; - status = "disabled"; - usb-phy = <&usb4_phy>; + compatible = "qcom,ci-hdrc"; + reg = <0x12530000 0x200>, + <0x12530200 0x200>; + interrupts = ; + clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>; + clock-names = "core", "iface"; + assigned-clocks = <&gcc USB_HS4_XCVR_CLK>; + assigned-clock-rates = <60000000>; + resets = <&gcc USB_HS4_RESET>; + reset-names = "core"; + phy_type = "ulpi"; + ahb-burst-config = <0>; + phys = <&usb_hs4_phy>; + phy-names = "usb-phy"; + status = "disabled"; + #reset-cells = <1>; + + ulpi { + usb_hs4_phy: phy { + compatible = "qcom,usb-hs-phy-apq8064", + "qcom,usb-hs-phy"; + #phy-cells = <0>; + clocks = <&sleep_clk>, <&cxo_board>; + clock-names = "sleep", "ref"; + resets = <&usb4 0>; + reset-names = "por"; + }; + }; }; sata_phy0: phy@1b400000 { -- cgit v1.2.3 From bc63cd87f3ce924f02e575ffb12f8c10cd7d3780 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Fri, 19 May 2017 15:07:01 +0200 Subject: ARM: dts: gose: add HDMI input Identical to the setup on Koelsch. Signed-off-by: Ulrich Hecht Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7793-gose.dts | 68 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 66 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index 95e51b79c1d7..30f083528468 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -253,12 +253,23 @@ }; }; + hdmi-in { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&adv7612_in>; + }; + }; + }; + hdmi-out { compatible = "hdmi-connector"; type = "a"; port { - hdmi_con: endpoint { + hdmi_con_out: endpoint { remote-endpoint = <&adv7511_out>; }; }; @@ -395,6 +406,11 @@ groups = "audio_clk_a"; function = "audio_clk"; }; + + vin0_pins: vin0 { + groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; + function = "vin0"; + }; }; ðer { @@ -552,7 +568,34 @@ port@1 { reg = <1>; adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; + + hdmi-in@4c { + compatible = "adi,adv7612"; + reg = <0x4c>; + interrupt-parent = <&gpio4>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + default-input = <0>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7612_in: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + + port@2 { + reg = <2>; + adv7612_out: endpoint { + remote-endpoint = <&vin0ep2>; }; }; }; @@ -606,3 +649,24 @@ &ssi1 { shared-pin; }; + +/* HDMI video input */ +&vin0 { + status = "okay"; + pinctrl-0 = <&vin0_pins>; + pinctrl-names = "default"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + vin0ep2: endpoint { + remote-endpoint = <&adv7612_out>; + bus-width = <24>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + data-active = <1>; + }; + }; +}; -- cgit v1.2.3 From fe2a5cd8aa038e2b02fda983afc2083e94c04b4f Mon Sep 17 00:00:00 2001 From: Sebastian Andrzej Siewior Date: Wed, 24 May 2017 10:15:25 +0200 Subject: ARM/hw_breakpoint: Use cpuhp_setup_state_cpuslocked() arch_hw_breakpoint_init() holds get_online_cpus() while registerring the hotplug callbacks. cpuhp_setup_state() invokes get_online_cpus() as well. This is correct, but prevents the conversion of the hotplug locking to a percpu rwsem. Use cpuhp_setup_state_cpuslocked() to avoid the nested call. Convert *_online_cpus() to the new interfaces while at it. Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Thomas Gleixner Acked-by: Ingo Molnar Acked-by: Mark Rutland Cc: Paul E. McKenney Cc: Peter Zijlstra Cc: Will Deacon Cc: Steven Rostedt Cc: Russell King Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/20170524081548.170940729@linutronix.de --- arch/arm/kernel/hw_breakpoint.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index be3b3fbd382f..63cb4c7c6593 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -1090,7 +1090,7 @@ static int __init arch_hw_breakpoint_init(void) * driven low on this core and there isn't an architected way to * determine that. */ - get_online_cpus(); + cpus_read_lock(); register_undef_hook(&debug_reg_hook); /* @@ -1098,15 +1098,16 @@ static int __init arch_hw_breakpoint_init(void) * assume that a halting debugger will leave the world in a nice state * for us. */ - ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm/hw_breakpoint:online", - dbg_reset_online, NULL); + ret = cpuhp_setup_state_cpuslocked(CPUHP_AP_ONLINE_DYN, + "arm/hw_breakpoint:online", + dbg_reset_online, NULL); unregister_undef_hook(&debug_reg_hook); if (WARN_ON(ret < 0) || !cpumask_empty(&debug_err_mask)) { core_num_brps = 0; core_num_wrps = 0; if (ret > 0) cpuhp_remove_state_nocalls(ret); - put_online_cpus(); + cpus_read_unlock(); return 0; } @@ -1124,7 +1125,7 @@ static int __init arch_hw_breakpoint_init(void) TRAP_HWBKPT, "watchpoint debug exception"); hook_ifault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT, "breakpoint debug exception"); - put_online_cpus(); + cpus_read_unlock(); /* Register PM notifiers. */ pm_init(); -- cgit v1.2.3 From 9489cc8f370be811f7e741a772bcce88b712272d Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 24 May 2017 10:15:38 +0200 Subject: arm: Prevent hotplug rwsem recursion The text patching functions which are invoked from jump_label and kprobes code are protected against cpu hotplug at the call sites. Use stop_machine_cpuslocked() to avoid recursion on the cpu hotplug rwsem. stop_machine_cpuslocked() contains a lockdep assertion to catch any unprotected callers. Signed-off-by: Thomas Gleixner Acked-by: Ingo Molnar Cc: Paul E. McKenney Cc: Peter Zijlstra Cc: Sebastian Siewior Cc: Steven Rostedt Cc: Russell King Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/20170524081549.275871311@linutronix.de --- arch/arm/kernel/patch.c | 2 +- arch/arm/probes/kprobes/core.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/patch.c b/arch/arm/kernel/patch.c index 020560b2dcb7..a1a34722c655 100644 --- a/arch/arm/kernel/patch.c +++ b/arch/arm/kernel/patch.c @@ -124,5 +124,5 @@ void __kprobes patch_text(void *addr, unsigned int insn) .insn = insn, }; - stop_machine(patch_text_stop_machine, &patch, NULL); + stop_machine_cpuslocked(patch_text_stop_machine, &patch, NULL); } diff --git a/arch/arm/probes/kprobes/core.c b/arch/arm/probes/kprobes/core.c index ad1f4e6a9e33..52d1cd14fda4 100644 --- a/arch/arm/probes/kprobes/core.c +++ b/arch/arm/probes/kprobes/core.c @@ -182,7 +182,8 @@ void __kprobes kprobes_remove_breakpoint(void *addr, unsigned int insn) .addr = addr, .insn = insn, }; - stop_machine(__kprobes_remove_breakpoint, &p, cpu_online_mask); + stop_machine_cpuslocked(__kprobes_remove_breakpoint, &p, + cpu_online_mask); } void __kprobes arch_disarm_kprobe(struct kprobe *p) -- cgit v1.2.3 From bd71af3c71b51b02f83e3987a3a44ca51894ae8a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 18 May 2017 15:00:09 +0200 Subject: ARM: dts: omap4-devkit8000: fix gpmc ranges property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With two separate &gpmc nodes the second ranges property overwrites the first. So put nand and ethernet in a single node and merge the ranges. While at it also fix the ethernet suffix. Signed-off-by: Uwe Kleine-König Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-devkit8000-common.dtsi | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi index f330c69cc683..82aa9c4a0f1c 100644 --- a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi +++ b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi @@ -201,7 +201,8 @@ }; &gpmc { - ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ + ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ + 6 0 0x2c000000 0x1000000>; /* CS6: 16MB for DM9000 */ nand@0,0 { compatible = "ti,omap2-nand"; @@ -256,12 +257,8 @@ reg = <0x680000 0xf980000>; }; }; -}; - -&gpmc { - ranges = <6 0 0x2c000000 0x1000000>; /* CS6: 16MB for DM9000 */ - ethernet@0,0 { + ethernet@6,0 { compatible = "davicom,dm9000"; reg = <6 0x000 2 6 0x400 2>; /* CS6, offset 0 and 0x400, IO size 2 */ -- cgit v1.2.3 From 3264ce2079f379b006ae951c14ebac81058d87d5 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 19 May 2017 15:47:41 -0500 Subject: ARM: dts: am572x-idk: Enable the system mailboxes 5 and 6 Enable the System Mailboxes 5 and 6 and the corresponding child sub-mailbox (IPC 3.x) nodes for the AM572x IDK board. This is needed to enable communication with the respective remote processors IPU1, IPU2, DSP1 and DSP2 from the MPU. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am572x-idk.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts index 8350b4b34b08..9da6d83ca185 100644 --- a/arch/arm/boot/dts/am572x-idk.dts +++ b/arch/arm/boot/dts/am572x-idk.dts @@ -91,3 +91,23 @@ &pcie1 { gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; }; + +&mailbox5 { + status = "okay"; + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + status = "okay"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + status = "okay"; + }; +}; + +&mailbox6 { + status = "okay"; + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + status = "okay"; + }; + mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + status = "okay"; + }; +}; -- cgit v1.2.3 From 2303587b9b1d7867c6d2ec4ea3bc341a1c8be486 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 19 May 2017 15:47:42 -0500 Subject: ARM: dts: am571x-idk: Enable the system mailboxes 5 and 6 Enable the System Mailboxes 5 and 6 and the corresponding child sub-mailbox (IPC 3.x) nodes for the AM571x IDK board. This is needed to enable communication with the respective remote processors IPU1, IPU2, and DSP1 from the MPU. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am571x-idk.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts index ad68d1eb3bc3..7b207835b2d1 100644 --- a/arch/arm/boot/dts/am571x-idk.dts +++ b/arch/arm/boot/dts/am571x-idk.dts @@ -79,3 +79,20 @@ id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>; }; + +&mailbox5 { + status = "okay"; + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + status = "okay"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + status = "okay"; + }; +}; + +&mailbox6 { + status = "okay"; + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + status = "okay"; + }; +}; -- cgit v1.2.3 From c2498af5c036ee72e0a0f4247770cab7fd1f34b5 Mon Sep 17 00:00:00 2001 From: Ricardo Salveti Date: Mon, 22 May 2017 11:51:38 -0300 Subject: arm: dts: boneblack-wireless: add WL1835 Bluetooth device node This adds the serial slave device for the WL1835 Bluetooth interface. Signed-off-by: Ricardo Salveti Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-boneblack-wireless.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/am335x-boneblack-wireless.dts index 105bd10655f7..83f49f616b19 100644 --- a/arch/arm/boot/dts/am335x-boneblack-wireless.dts +++ b/arch/arm/boot/dts/am335x-boneblack-wireless.dts @@ -97,6 +97,11 @@ pinctrl-names = "default"; pinctrl-0 = <&uart3_pins &bt_pins>; status = "okay"; + + bluetooth { + compatible = "ti,wl1835-st"; + enable-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; }; &gpio3 { -- cgit v1.2.3 From bfaa10635f2e911f8edc7de4fd40a15322bb91e2 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 22 May 2017 09:13:46 -0700 Subject: ARM: dts: Enable earlycon stdout path for duovero As long as the kernel cmdline has "earlycon" in it, this allows seeing debug messages earlier and does not require DEBUG_LL to be enabled. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-duovero.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi index ec0bd9779e1a..6e6810c258eb 100644 --- a/arch/arm/boot/dts/omap4-duovero.dtsi +++ b/arch/arm/boot/dts/omap4-duovero.dtsi @@ -12,6 +12,10 @@ model = "Gumstix Duovero"; compatible = "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; + chosen { + stdout-path = &uart3; + }; + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ -- cgit v1.2.3 From cb11a8baa504a85973def5a848502bbdb944c450 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 22 May 2017 09:13:45 -0700 Subject: ARM: dts: Enable earlycon stdout path for LogicPD torpedo As long as the kernel cmdline has "earlycon" in it, this allows seeing debug messages earlier and does not require DEBUG_LL to be enabled. Acked-by: Adam Ford Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/logicpd-torpedo-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi index efe53998c961..6d89736c7b44 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi +++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi @@ -7,6 +7,10 @@ #include / { + chosen { + stdout-path = &uart1; + }; + cpus { cpu@0 { cpu0-supply = <&vcc>; -- cgit v1.2.3 From 05e7d622f1536266e6be352fa344e4cce51c95b0 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Tue, 23 May 2017 15:34:31 +0200 Subject: ARM: dts: omap: Add generic compatible string for I2C EEPROM The at24 driver allows to register I2C EEPROM chips using different vendor and devices, but the I2C subsystem does not take the vendor into account when matching using the I2C table since it only has device entries. But when matching using an OF table, both the vendor and device has to be taken into account so the driver defines only a set of compatible strings using the "atmel" vendor as a generic fallback for compatible I2C devices. So add this generic fallback to the device node compatible string to make the device to match the driver using the OF device ID table. Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-baltos.dtsi | 2 +- arch/arm/boot/dts/am335x-base0033.dts | 2 +- arch/arm/boot/dts/am335x-bone-common.dtsi | 10 +++++----- arch/arm/boot/dts/am335x-nano.dts | 2 +- arch/arm/boot/dts/am335x-pepper.dts | 2 +- arch/arm/boot/dts/am335x-shc.dts | 2 +- arch/arm/boot/dts/am335x-sl50.dts | 2 +- arch/arm/boot/dts/am437x-idk-evm.dts | 2 +- arch/arm/boot/dts/am437x-sk-evm.dts | 2 +- arch/arm/boot/dts/am43x-epos-evm.dts | 2 +- arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 2 +- arch/arm/boot/dts/omap3-cm-t3x.dtsi | 2 +- arch/arm/boot/dts/omap3-gta04.dtsi | 2 +- arch/arm/boot/dts/omap3-sb-t35.dtsi | 2 +- arch/arm/boot/dts/omap4-var-som-om44.dtsi | 2 +- arch/arm/boot/dts/omap5-cm-t54.dts | 2 +- arch/arm/boot/dts/omap5-sbc-t54.dts | 2 +- 17 files changed, 21 insertions(+), 21 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi index d42b98f15e8b..ec6052c521ef 100644 --- a/arch/arm/boot/dts/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/am335x-baltos.dtsi @@ -255,7 +255,7 @@ }; at24@50 { - compatible = "at24,24c02"; + compatible = "atmel,24c02"; pagesize = <8>; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/am335x-base0033.dts b/arch/arm/boot/dts/am335x-base0033.dts index c2bee452dab8..29782be07605 100644 --- a/arch/arm/boot/dts/am335x-base0033.dts +++ b/arch/arm/boot/dts/am335x-base0033.dts @@ -89,7 +89,7 @@ &i2c0 { eeprom: eeprom@50 { - compatible = "at,24c256"; + compatible = "atmel,24c256"; reg = <0x50>; }; }; diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index bf6b26abe35b..1d154444dfef 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -232,7 +232,7 @@ }; baseboard_eeprom: baseboard_eeprom@50 { - compatible = "at,24c256"; + compatible = "atmel,24c256"; reg = <0x50>; #address-cells = <1>; @@ -251,7 +251,7 @@ clock-frequency = <100000>; cape_eeprom0: cape_eeprom0@54 { - compatible = "at,24c256"; + compatible = "atmel,24c256"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; @@ -261,7 +261,7 @@ }; cape_eeprom1: cape_eeprom1@55 { - compatible = "at,24c256"; + compatible = "atmel,24c256"; reg = <0x55>; #address-cells = <1>; #size-cells = <1>; @@ -271,7 +271,7 @@ }; cape_eeprom2: cape_eeprom2@56 { - compatible = "at,24c256"; + compatible = "atmel,24c256"; reg = <0x56>; #address-cells = <1>; #size-cells = <1>; @@ -281,7 +281,7 @@ }; cape_eeprom3: cape_eeprom3@57 { - compatible = "at,24c256"; + compatible = "atmel,24c256"; reg = <0x57>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts index 807494bc722b..946d7069f417 100644 --- a/arch/arm/boot/dts/am335x-nano.dts +++ b/arch/arm/boot/dts/am335x-nano.dts @@ -224,7 +224,7 @@ }; eeprom@53 { - compatible = "microchip,24c02"; + compatible = "microchip,24c02", "atmel,24c02"; reg = <0x53>; pagesize = <8>; }; diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts index 30e2f8770aaf..03c7d77023c6 100644 --- a/arch/arm/boot/dts/am335x-pepper.dts +++ b/arch/arm/boot/dts/am335x-pepper.dts @@ -67,7 +67,7 @@ }; eeprom: eeprom@50 { - compatible = "at,24c256"; + compatible = "atmel,24c256"; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts index bf8727a19ece..4f6a286ea293 100644 --- a/arch/arm/boot/dts/am335x-shc.dts +++ b/arch/arm/boot/dts/am335x-shc.dts @@ -188,7 +188,7 @@ }; at24@50 { - compatible = "at24,24c32"; + compatible = "atmel,24c32"; pagesize = <32>; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts index c5d2589c55fc..a82a4042eb9d 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/am335x-sl50.dts @@ -309,7 +309,7 @@ }; eeprom: eeprom@50 { - compatible = "at,24c256"; + compatible = "atmel,24c256"; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts index c1f7f9336e64..5e364473067f 100644 --- a/arch/arm/boot/dts/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/am437x-idk-evm.dts @@ -339,7 +339,7 @@ clock-frequency = <400000>; at24@50 { - compatible = "at24,24c256"; + compatible = "atmel,24c256"; pagesize = <64>; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 4dc54bee2f36..a62e1583da04 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -511,7 +511,7 @@ }; at24@50 { - compatible = "at24,24c256"; + compatible = "atmel,24c256"; pagesize = <64>; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 9acd4ccdec4e..f6648ab10d29 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -477,7 +477,7 @@ }; at24@50 { - compatible = "at24,24c256"; + compatible = "atmel,24c256"; pagesize = <64>; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi index 585d792a8fdd..fdfe5b16b806 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi +++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi @@ -388,7 +388,7 @@ }; eeprom: eeprom@50 { - compatible = "at,24c32"; + compatible = "atmel,24c32"; reg = <0x50>; }; }; diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi index 57b9a028a49a..fccd5383243c 100644 --- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi +++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi @@ -188,7 +188,7 @@ clock-frequency = <400000>; at24@50 { - compatible = "at24,24c02"; + compatible = "atmel,24c02"; pagesize = <16>; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index b3a8b1f24499..43a0456e3dcc 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -418,7 +418,7 @@ /* RFID EEPROM */ m24lr64@50 { - compatible = "at,24c64"; + compatible = "atmel,24c64"; reg = <0x50>; }; }; diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/omap3-sb-t35.dtsi index 91e15af78949..4476fb685a1b 100644 --- a/arch/arm/boot/dts/omap3-sb-t35.dtsi +++ b/arch/arm/boot/dts/omap3-sb-t35.dtsi @@ -89,7 +89,7 @@ clock-frequency = <400000>; at24@50 { - compatible = "at24,24c02"; + compatible = "atmel,24c02"; pagesize = <16>; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/omap4-var-som-om44.dtsi index 758b6eb7ae43..6500bfc8d130 100644 --- a/arch/arm/boot/dts/omap4-var-som-om44.dtsi +++ b/arch/arm/boot/dts/omap4-var-som-om44.dtsi @@ -241,7 +241,7 @@ }; eeprom@50 { - compatible = "microchip,24c32"; + compatible = "microchip,24c32", "atmel,24c32"; reg = <0x50>; }; }; diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts index b153f604932a..78397f66d0b2 100644 --- a/arch/arm/boot/dts/omap5-cm-t54.dts +++ b/arch/arm/boot/dts/omap5-cm-t54.dts @@ -404,7 +404,7 @@ clock-frequency = <400000>; at24@50 { - compatible = "at24,24c02"; + compatible = "atmel,24c02"; pagesize = <16>; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/omap5-sbc-t54.dts b/arch/arm/boot/dts/omap5-sbc-t54.dts index 337bbbc01a35..7b8810d13257 100644 --- a/arch/arm/boot/dts/omap5-sbc-t54.dts +++ b/arch/arm/boot/dts/omap5-sbc-t54.dts @@ -44,7 +44,7 @@ clock-frequency = <400000>; at24@50 { - compatible = "at24,24c02"; + compatible = "atmel,24c02"; pagesize = <16>; reg = <0x50>; }; -- cgit v1.2.3 From 05306b848b367e326dc76e7552192056338ac6ad Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 25 May 2017 09:15:58 -0700 Subject: ARM: dts: Configure USB host for 37xx-evm Looks like nobody bothered to configure USB host for 37xx-evm when we converted things to device tree, so let's add it. This is similar to beagleboard configuration with few extra quirks to configure the port. And as with beagleboard, OHCI won't work because there is no USB LS/FS PHY. A HS USB hub is needed to use devices like keyboard and mice. Acked-by: Roger Quadros Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-evm-37xx.dts | 102 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/omap3-evm-common.dtsi | 33 +++++++++++ 2 files changed, 135 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts index 4f9a76544602..c963b31ec3b3 100644 --- a/arch/arm/boot/dts/omap3-evm-37xx.dts +++ b/arch/arm/boot/dts/omap3-evm-37xx.dts @@ -34,7 +34,15 @@ >; }; +&hsusb2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&ehci_phy_pins>; +}; + &omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>; + dss_dpi_pins1: pinmux_dss_dpi_pins2 { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ @@ -98,6 +106,37 @@ >; }; + /* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */ + on_board_gpio_61: pinmux_ehci_port_select_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) + >; + }; + + /* Used by OHCI and EHCI. OHCI won't work without external phy */ + hsusb2_pins: pinmux_hsusb2_pins { + pinctrl-single,pins = < + + /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* mcspi2_cs1.hsusb2_data3 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) + >; + }; + wl12xx_gpio: pinmux_wl12xx_gpio { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ @@ -112,6 +151,46 @@ }; }; +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_2_pins>; + + ehci_phy_pins: pinmux_ehci_phy_pins { + pinctrl-single,pins = < + + /* EHCI PHY reset GPIO etk_d7.gpio_21 */ + OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) + + /* EHCI VBUS etk_d8.gpio_22 */ + OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) + >; + }; + + /* Used by OHCI and EHCI. OHCI won't work without external phy */ + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + + /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) + + /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) + + /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* etk_d15.hsusb2_data1 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) + >; + }; +}; + &omap3_pmx_wkup { dss_dpi_pins2: pinmux_dss_dpi_pins1 { pinctrl-single,pins = < @@ -153,6 +232,29 @@ pinctrl-0 = <&uart3_pins>; }; +/* + * GPIO_61 (nUSB2_EN_1V8) must be low to enable on-board EHCI USB2 interface + * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V. + */ +&gpio2 { + en_usb2_port { + gpio-hog; + gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */ + output-low; + line-name = "enable usb2 port"; + }; +}; + +/* T2_GPIO_2 low to route GPIO_61 to on-board devices */ +&twl_gpio { + en_on_board_gpio_61 { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "en_hsusb2_clk"; + }; +}; + &gpmc { ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */ <5 0 0x2c000000 0x01000000>; diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi index 7780e2528697..2b1d6977a535 100644 --- a/arch/arm/boot/dts/omap3-evm-common.dtsi +++ b/arch/arm/boot/dts/omap3-evm-common.dtsi @@ -12,6 +12,24 @@ }; }; + /* HS USB Port 2 Power */ + hsusb2_power: hsusb2_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb2_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; /* gpio_22 */ + startup-delay-us = <70000>; + enable-active-high; + }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ + vcc-supply = <&hsusb2_power>; + }; + leds { compatible = "gpio-leds"; ledb { @@ -142,6 +160,14 @@ >; }; +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy>; +}; + &usb_otg_hs { interface-type = <0>; usb-phy = <&usb2_phy>; @@ -158,3 +184,10 @@ reg = <5 0 0xff>; }; }; + +&vaux2 { + regulator-name = "usb_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; -- cgit v1.2.3 From 200a575b68d25c5ad4d3379e6d43e9b3f6083e1b Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 17 Apr 2017 23:39:37 +0200 Subject: ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson.dtsi | 178 ++++++++++++++++++++++-------------------- arch/arm/boot/dts/meson6.dtsi | 2 - arch/arm/boot/dts/meson8.dtsi | 116 ++++++++++++++++++--------- 3 files changed, 170 insertions(+), 126 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index 8c77c87660cd..8d9c36970dfd 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -65,100 +65,108 @@ #interrupt-cells = <3>; }; - timer@c1109940 { - compatible = "amlogic,meson6-timer"; - reg = <0xc1109940 0x18>; - interrupts = <0 10 1>; - }; - soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - wdt: watchdog@c1109900 { - compatible = "amlogic,meson6-wdt"; - reg = <0xc1109900 0x8>; - interrupts = <0 0 1>; - }; - - uart_AO: serial@c81004c0 { - compatible = "amlogic,meson-uart"; - reg = <0xc81004c0 0x18>; - interrupts = <0 90 1>; - clocks = <&clk81>; - status = "disabled"; - }; - - uart_A: serial@c11084c0 { - compatible = "amlogic,meson-uart"; - reg = <0xc11084c0 0x18>; - interrupts = <0 26 1>; - clocks = <&clk81>; - status = "disabled"; - }; - - uart_B: serial@c11084dc { - compatible = "amlogic,meson-uart"; - reg = <0xc11084dc 0x18>; - interrupts = <0 75 1>; - clocks = <&clk81>; - status = "disabled"; - }; - - uart_C: serial@c1108700 { - compatible = "amlogic,meson-uart"; - reg = <0xc1108700 0x18>; - interrupts = <0 93 1>; - clocks = <&clk81>; - status = "disabled"; - }; - - i2c_AO: i2c@c8100500 { - compatible = "amlogic,meson6-i2c"; - reg = <0xc8100500 0x20>; - interrupts = <0 92 1>; - clocks = <&clk81>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c_A: i2c@c1108500 { - compatible = "amlogic,meson6-i2c"; - reg = <0xc1108500 0x20>; - interrupts = <0 21 1>; - clocks = <&clk81>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c_B: i2c@c11087c0 { - compatible = "amlogic,meson6-i2c"; - reg = <0xc11087c0 0x20>; - interrupts = <0 128 1>; - clocks = <&clk81>; + cbus: cbus@c1100000 { + compatible = "simple-bus"; + reg = <0xc1100000 0x200000>; #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + #size-cells = <1>; + ranges = <0x0 0xc1100000 0x200000>; + + uart_A: serial@84c0 { + compatible = "amlogic,meson-uart"; + reg = <0x84c0 0x18>; + interrupts = <0 26 1>; + status = "disabled"; + }; + + uart_B: serial@84dc { + compatible = "amlogic,meson-uart"; + reg = <0x84dc 0x18>; + interrupts = <0 75 1>; + status = "disabled"; + }; + + i2c_A: i2c@8500 { + compatible = "amlogic,meson6-i2c"; + reg = <0x8500 0x20>; + interrupts = <0 21 1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart_C: serial@8700 { + compatible = "amlogic,meson-uart"; + reg = <0x8700 0x18>; + interrupts = <0 93 1>; + status = "disabled"; + }; + + i2c_B: i2c@87c0 { + compatible = "amlogic,meson6-i2c"; + reg = <0x87c0 0x20>; + interrupts = <0 128 1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spifc: spi@8c80 { + compatible = "amlogic,meson6-spifc"; + reg = <0x8c80 0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + wdt: watchdog@9900 { + compatible = "amlogic,meson6-wdt"; + reg = <0x9900 0x8>; + interrupts = <0 0 1>; + }; + + timer@9940 { + compatible = "amlogic,meson6-timer"; + reg = <0x9940 0x18>; + interrupts = <0 10 1>; + }; }; - ir_receiver: ir-receiver@c8100480 { - compatible= "amlogic,meson6-ir"; - reg = <0xc8100480 0x20>; - interrupts = <0 15 1>; - status = "disabled"; - }; - - spifc: spi@c1108c80 { - compatible = "amlogic,meson6-spifc"; - reg = <0xc1108c80 0x80>; + aobus: aobus@c8100000 { + compatible = "simple-bus"; + reg = <0xc8100000 0x100000>; #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk81>; - status = "disabled"; + #size-cells = <1>; + ranges = <0x0 0xc8100000 0x100000>; + + ir_receiver: ir-receiver@480 { + compatible= "amlogic,meson6-ir"; + reg = <0x480 0x20>; + interrupts = <0 15 1>; + status = "disabled"; + }; + + uart_AO: serial@4c0 { + compatible = "amlogic,meson-uart"; + reg = <0x4c0 0x18>; + interrupts = <0 90 1>; + status = "disabled"; + }; + + i2c_AO: i2c@500 { + compatible = "amlogic,meson6-i2c"; + reg = <0x500 0x20>; + interrupts = <0 92 1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; ethmac: ethernet@c9410000 { @@ -167,8 +175,6 @@ 0xc1108108 0x4>; interrupts = <0 8 1>; interrupt-names = "macirq"; - clocks = <&clk81>; - clock-names = "stmmaceth"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi index 8b33be15af94..b0fc91ffd6a1 100644 --- a/arch/arm/boot/dts/meson6.dtsi +++ b/arch/arm/boot/dts/meson6.dtsi @@ -51,8 +51,6 @@ model = "Amlogic Meson6 SoC"; compatible = "amlogic,meson6"; - interrupt-parent = <&gic>; - cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index ebc763eab195..5eaaf067c76a 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -50,8 +50,6 @@ model = "Amlogic Meson8 SoC"; compatible = "amlogic,meson8"; - interrupt-parent = <&gic>; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -91,18 +89,55 @@ clock-frequency = <141666666>; }; - pinctrl_cbus: pinctrl@c1109880 { +}; /* end of / */ + +&aobus { + pinctrl_aobus: pinctrl@84 { + compatible = "amlogic,meson8-aobus-pinctrl"; + reg = <0x84 0xc>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio_ao: ao-bank@14 { + reg = <0x14 0x4>, + <0x2c 0x4>, + <0x24 0x8>; + reg-names = "mux", "pull", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aobus 0 120 16>; + }; + + uart_ao_a_pins: uart_ao_a { + mux { + groups = "uart_tx_ao_a", "uart_rx_ao_a"; + function = "uart_ao"; + }; + }; + + i2c_ao_pins: i2c_mst_ao { + mux { + groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; + function = "i2c_mst_ao"; + }; + }; + }; +}; + +&cbus { + pinctrl_cbus: pinctrl@9880 { compatible = "amlogic,meson8-cbus-pinctrl"; - reg = <0xc1109880 0x10>; + reg = <0x9880 0x10>; #address-cells = <1>; #size-cells = <1>; ranges; - gpio: banks@c11080b0 { - reg = <0xc11080b0 0x28>, - <0xc11080e8 0x18>, - <0xc1108120 0x18>, - <0xc1108030 0x30>; + gpio: banks@80b0 { + reg = <0x80b0 0x28>, + <0x80e8 0x18>, + <0x8120 0x18>, + <0x8030 0x30>; reg-names = "mux", "pull", "pull-enable", "gpio"; gpio-controller; #gpio-cells = <2>; @@ -134,36 +169,41 @@ }; }; }; +}; - pinctrl_aobus: pinctrl@c8100084 { - compatible = "amlogic,meson8-aobus-pinctrl"; - reg = <0xc8100084 0xc>; - #address-cells = <1>; - #size-cells = <1>; - ranges; +ðmac { + clocks = <&clk81>; + clock-names = "stmmaceth"; +}; - gpio_ao: ao-bank@c1108030 { - reg = <0xc8100014 0x4>, - <0xc810002c 0x4>, - <0xc8100024 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 120 16>; - }; +&i2c_AO { + clocks = <&clk81>; +}; - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a"; - function = "uart_ao"; - }; - }; +&i2c_A { + clocks = <&clk81>; +}; - i2c_ao_pins: i2c_mst_ao { - mux { - groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; - function = "i2c_mst_ao"; - }; - }; - }; -}; /* end of / */ +&i2c_B { + clocks = <&clk81>; +}; + +&spifc { + clocks = <&clk81>; +}; + +&uart_AO { + clocks = <&clk81>; +}; + +&uart_A { + clocks = <&clk81>; +}; + +&uart_B { + clocks = <&clk81>; +}; + +&uart_C { + clocks = <&clk81>; +}; -- cgit v1.2.3 From f44135e1f961d5bed1e737ff8e67564cdfa5eb85 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 17 Apr 2017 23:39:38 +0200 Subject: ARM: dts: meson8b: inherit meson.dtsi from meson8b.dtsi Currently only meson6.dtsi and meson8.dtsi inherit the generic meson.dtsi. However, since the Meson8b platform is basically a slightly updated version of Meson8 we can safely inherit meson.dtsi. An indicator for this are the nodes which are identical in meson.dtsi and meson8b.dtsi (L2, gic, timer, uart_AO, uart_A, uart_B, uart_C). Additionally this makes the following devices available on Meson8b which were not avaialble before (however, since all affected drivers support Meson6, Meson8 and the whole GX series there's no reason to assume that they are not working): - i2c_a and i2c_B - the IR receiver - SPFIC (SPI flash controller) - the dwmac ethernet controller Differences between Meson8 and Meson8b seem to be: - ARM Cortex-A5 core instead of Cortex-A9 on Meson8 - dwmac on Meson8b supports RGMII - small pinctrl updates Inheriting meson.dtsi makes it easier to maintain by removing duplicate definitions. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 210 +++++++++++++++++------------------------ 1 file changed, 84 insertions(+), 126 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 828aa49c678c..ef9ac974111c 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -47,11 +47,9 @@ #include #include #include -#include "skeleton.dtsi" +#include "meson.dtsi" / { - interrupt-parent = <&gic>; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -84,147 +82,107 @@ reg = <0x203>; }; }; +}; /* end of / */ - soc { - compatible = "simple-bus"; +&aobus { + pinctrl_aobus: pinctrl@84 { + compatible = "amlogic,meson8b-aobus-pinctrl"; + reg = <0x84 0xc>; #address-cells = <1>; #size-cells = <1>; ranges; - L2: l2-cache-controller@c4200000 { - compatible = "arm,pl310-cache"; - reg = <0xc4200000 0x1000>; - cache-unified; - cache-level = <2>; + gpio_ao: ao-bank@14 { + reg = <0x14 0x4>, + <0x2c 0x4>, + <0x24 0x8>; + reg-names = "mux", "pull", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aobus 0 130 16>; }; - gic: interrupt-controller@c4301000 { - compatible = "arm,cortex-a9-gic"; - reg = <0xc4301000 0x1000>, - <0xc4300100 0x0100>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - reset: reset-controller@c1104404 { - compatible = "amlogic,meson8b-reset"; - reg = <0xc1104404 0x20>; - #reset-cells = <1>; - }; - - wdt: watchdog@c1109900 { - compatible = "amlogic,meson8b-wdt"; - reg = <0xc1109900 0x8>; - interrupts = <0 0 1>; + uart_ao_a_pins: uart_ao_a { + mux { + groups = "uart_tx_ao_a", "uart_rx_ao_a"; + function = "uart_ao"; + }; }; + }; +}; - timer@c1109940 { - compatible = "amlogic,meson6-timer"; - reg = <0xc1109940 0x18>; - interrupts = <0 10 1>; - }; +&cbus { + clkc: clock-controller@4000 { + #clock-cells = <1>; + compatible = "amlogic,meson8b-clkc"; + reg = <0x8000 0x4>, <0x4000 0x460>; + }; - uart_AO: serial@c81004c0 { - compatible = "amlogic,meson-uart"; - reg = <0xc81004c0 0x18>; - interrupts = <0 90 1>; - clocks = <&clkc CLKID_CLK81>; - status = "disabled"; - }; + reset: reset-controller@4404 { + compatible = "amlogic,meson8b-reset"; + reg = <0x4404 0x20>; + #reset-cells = <1>; + }; - uart_A: serial@c11084c0 { - compatible = "amlogic,meson-uart"; - reg = <0xc11084c0 0x18>; - interrupts = <0 26 1>; - clocks = <&clkc CLKID_CLK81>; - status = "disabled"; - }; + pwm_ab: pwm@8550 { + compatible = "amlogic,meson8b-pwm"; + reg = <0x8550 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; - uart_B: serial@c11084dc { - compatible = "amlogic,meson-uart"; - reg = <0xc11084dc 0x18>; - interrupts = <0 75 1>; - clocks = <&clkc CLKID_CLK81>; - status = "disabled"; - }; + pwm_cd: pwm@8650 { + compatible = "amlogic,meson8b-pwm"; + reg = <0x8650 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; - uart_C: serial@c1108700 { - compatible = "amlogic,meson-uart"; - reg = <0xc1108700 0x18>; - interrupts = <0 93 1>; - clocks = <&clkc CLKID_CLK81>; - status = "disabled"; - }; + pwm_ef: pwm@86c0 { + compatible = "amlogic,meson8b-pwm"; + reg = <0x86c0 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; - clkc: clock-controller@c1104000 { - #clock-cells = <1>; - compatible = "amlogic,meson8b-clkc"; - reg = <0xc1108000 0x4>, <0xc1104000 0x460>; - }; + wdt: watchdog@9900 { + compatible = "amlogic,meson8b-wdt"; + reg = <0x9900 0x8>; + interrupts = <0 0 1>; + }; - pwm_ab: pwm@8550 { - compatible = "amlogic,meson8b-pwm"; - reg = <0xc1108550 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; + pinctrl_cbus: pinctrl@9880 { + compatible = "amlogic,meson8b-cbus-pinctrl"; + reg = <0x9880 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; - pwm_cd: pwm@8650 { - compatible = "amlogic,meson8b-pwm"; - reg = <0xc1108650 0x10>; - #pwm-cells = <3>; - status = "disabled"; + gpio: banks@80b0 { + reg = <0x80b0 0x28>, + <0x80e8 0x18>, + <0x8120 0x18>, + <0x8030 0x38>; + reg-names = "mux", "pull", "pull-enable", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_cbus 0 0 130>; }; + }; +}; - pwm_ef: pwm@86c0 { - compatible = "amlogic,meson8b-pwm"; - reg = <0xc11086c0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; +&uart_AO { + clocks = <&clkc CLKID_CLK81>; +}; - pinctrl_cbus: pinctrl@c1109880 { - compatible = "amlogic,meson8b-cbus-pinctrl"; - reg = <0xc1109880 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio: banks@c11080b0 { - reg = <0xc11080b0 0x28>, - <0xc11080e8 0x18>, - <0xc1108120 0x18>, - <0xc1108030 0x38>; - reg-names = "mux", "pull", "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_cbus 0 0 130>; - }; - }; +&uart_A { + clocks = <&clkc CLKID_CLK81>; +}; - pinctrl_aobus: pinctrl@c8100084 { - compatible = "amlogic,meson8b-aobus-pinctrl"; - reg = <0xc8100084 0xc>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio_ao: ao-bank@c1108030 { - reg = <0xc8100014 0x4>, - <0xc810002c 0x4>, - <0xc8100024 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 130 16>; - }; +&uart_B { + clocks = <&clkc CLKID_CLK81>; +}; - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a"; - function = "uart_ao"; - }; - }; - }; - }; -}; /* end of / */ +&uart_C { + clocks = <&clkc CLKID_CLK81>; +}; -- cgit v1.2.3 From bbe5b23dfdd346e782f8c56ab01bb3f5eaddd438 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Mon, 17 Apr 2017 23:42:44 +0200 Subject: ARM: dts: meson: Extend L2 cache controller node for Meson8 and Meson8b This patch extends the L2 cache controller node for the Amlogic Meson8 and Meson8b SoCs with some missing parameters. These are taken from the Amlogic GPL kernel source. Signed-off-by: Carlo Caione [apply the change to Meson8 and Meson8b and updated description] Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 6 ++++++ arch/arm/boot/dts/meson8b.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 5eaaf067c76a..6993077331c7 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -188,6 +188,12 @@ clocks = <&clk81>; }; +&L2 { + arm,data-latency = <3 3 3>; + arm,tag-latency = <2 2 2>; + arm,filter-ranges = <0x100000 0xc0000000>; +}; + &spifc { clocks = <&clk81>; }; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index ef9ac974111c..d9f116a418b2 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -171,6 +171,12 @@ }; }; +&L2 { + arm,data-latency = <3 3 3>; + arm,tag-latency = <2 2 2>; + arm,filter-ranges = <0x100000 0xc0000000>; +}; + &uart_AO { clocks = <&clkc CLKID_CLK81>; }; -- cgit v1.2.3 From 925b865f88182e47891cb9b9eb27db4e5a86fc6f Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Fri, 26 May 2017 01:44:44 +0200 Subject: ARM: dts: vf610-zii: Add switch eeprom-length properties Two of the Ethernet switches on this board have EEPROMs connected. Add the eeprom-length property to the device tree, making it possible to access the EEPROM using ethtool -e. Signed-off-by: Andrew Lunn Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts index 37f95427616f..acdf12ad0622 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -78,6 +78,7 @@ interrupts = <27 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <2>; + eeprom-length = <512>; ports { #address-cells = <1>; @@ -163,6 +164,7 @@ interrupts = <26 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <2>; + eeprom-length = <512>; ports { #address-cells = <1>; -- cgit v1.2.3 From 0ac409a6cac35a8190f7c6fdbfc274603ee43e7f Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 25 May 2017 15:31:33 +0800 Subject: ARM: sun7i: a20: cubieboard2: Move usb_otg node for alphabetical ordering We want to keep node references in alphabetical order, except for instances where node must be #included first. Move the usb_otg node reference so that all references to non-AXP209 device nodes are in alphabetical order. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index 7ac5bcc9f972..c21edd75d0b3 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -174,11 +174,6 @@ status = "okay"; }; -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - #include "axp209.dtsi" ®_dcdc2 { @@ -220,6 +215,11 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; -- cgit v1.2.3 From 6df31af7d827ab8dbcf0baec0411813d7a709150 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 25 May 2017 15:31:34 +0800 Subject: ARM: sun7i: a20: cubieboard2: Enable AXP209's ACIN power supply The ACIN pins of the AXP209 PMIC on the Cubieboard 2 are tied to the DC jack on the board. Enable the ACIN power supply. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index c21edd75d0b3..2a50207618cb 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -176,6 +176,10 @@ #include "axp209.dtsi" +&ac_power_supply { + status = "okay"; +}; + ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; -- cgit v1.2.3 From 17aafb5b336b5cb78973c290b12aa0bd239be7fe Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 25 May 2017 15:31:35 +0800 Subject: ARM: sun7i: a20: bananapi-m1-plus: Enable AXP209's ACIN power supply The ACIN pins of the AXP209 PMIC on the Bananapi M1 Plus are tied to the "power input" micro USB connector next to the SATA connector on the board. Enable the ACIN power supply. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts index 4c03cc3fd7b3..eb55e74232c9 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts @@ -144,6 +144,10 @@ #include "axp209.dtsi" +&ac_power_supply { + status = "okay"; +}; + &ir0 { pinctrl-names = "default"; pinctrl-0 = <&ir0_rx_pins_a>; -- cgit v1.2.3 From 2fb90080db2c76e2ffcce1b8b3867250091b4d65 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 25 May 2017 15:31:36 +0800 Subject: ARM: sun4i: a10: cubieboard: Enable AXP209's ACIN power supply The ACIN pins of the AXP209 PMIC on the Cubieboard are tied to the DC jack on the board. Enable the ACIN power supply. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index a698a994e5ff..404ce7694899 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -182,6 +182,10 @@ #include "axp209.dtsi" +&ac_power_supply { + status = "okay"; +}; + ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; -- cgit v1.2.3 From c7b7158f397b6e2fc5cd13925b185502ca026158 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 25 May 2017 15:31:37 +0800 Subject: ARM: sun6i: a31: hummingbird: Enable AXP221's ACIN power supply The ACIN pins of the AXP221 PMIC on the A31 Hummingbird are tied to the DC jack on the board through a 12V to 5V buck converter. Enable the ACIN power supply. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index 55607208468b..9ecb5f0b3f83 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -253,6 +253,10 @@ #include "axp22x.dtsi" +&ac_power_supply { + status = "okay"; +}; + ®_aldo1 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; -- cgit v1.2.3 From 3c0492811ef83b3dfed88a7c3fe759ac7ad0197f Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 25 May 2017 15:31:38 +0800 Subject: ARM: sun7i: a20: cubietruck: Tie AXP209's USB power supply to USB PHY The USB PHY can use either a GPIO pin or the PMIC's USB power supply to sense VBUS. Since both options are available on the Cubietruck, add the missing property for the USB power supply to the USB PHY node. The device tree provides all usable options. Ultimately, which method is used is up to the driver implementation. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 8dbf732c7aa9..bb510187602c 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -336,6 +336,7 @@ pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */ usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ + usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; -- cgit v1.2.3 From 45857ae954783bcbab6f67c2300b7d98d214c393 Mon Sep 17 00:00:00 2001 From: Sergey Matyukevich Date: Sun, 28 May 2017 13:30:26 +0300 Subject: ARM: dts: orange-pi-zero: add node for SPI NOR Add node for SPI NOR flash on orange-pi-zero board. Disable this node by default and leave it to users to enable it if their board has SPI NOR flash chip populated. SPI NOR flash was optional in the first production batch in Dec 2016. In later batches flash chip was pre-populated. However there should be quite a few boards around which do not have flash chip. Signed-off-by: Sergey Matyukevich Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts index 9e8b082c134f..0b8b969f7c64 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts @@ -143,6 +143,19 @@ status = "okay"; }; +&spi0 { + /* Disable SPI NOR by default: it optional on Orange Pi Zero boards */ + status = "disabled"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mxicy,mx25l1606e", "winbond,w25q128"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; -- cgit v1.2.3 From 775448ce274a58bb8b5fa49795dc808446434dae Mon Sep 17 00:00:00 2001 From: Alexandre Bailon Date: Fri, 19 May 2017 15:33:36 +0200 Subject: ARM: dts: da850: Add CPPI 4.1 DMA to USB OTG controller This adds CPPI 4.1 DMA controller to USB OTG controller. Changes since v2: - Fixed the the property reg-names (had glue register defined) - Removed few useless property Signed-off-by: Alexandre Bailon Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850.dtsi | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 941d455000a7..0bd048e0049f 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -446,13 +446,38 @@ }; usb0: usb@200000 { compatible = "ti,da830-musb"; - reg = <0x200000 0x10000>; + reg = <0x200000 0x1000>; + ranges; interrupts = <58>; interrupt-names = "mc"; dr_mode = "otg"; phys = <&usb_phy 0>; phy-names = "usb-phy"; status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + + dmas = <&cppi41dma 0 0 &cppi41dma 1 0 + &cppi41dma 2 0 &cppi41dma 3 0 + &cppi41dma 0 1 &cppi41dma 1 1 + &cppi41dma 2 1 &cppi41dma 3 1>; + dma-names = + "rx1", "rx2", "rx3", "rx4", + "tx1", "tx2", "tx3", "tx4"; + + cppi41dma: dma-controller@201000 { + compatible = "ti,da830-cppi41"; + reg = <0x201000 0x1000 + 0x202000 0x1000 + 0x204000 0x4000>; + reg-names = "controller", + "scheduler", "queuemgr"; + interrupts = <58>; + #dma-cells = <2>; + #dma-channels = <4>; + status = "okay"; + }; }; sata: sata@218000 { compatible = "ti,da850-ahci"; -- cgit v1.2.3 From 0b997c8c9562dd61733dfeb9e1a5962730338e6e Mon Sep 17 00:00:00 2001 From: Alexandre Bailon Date: Tue, 23 May 2017 17:46:57 +0200 Subject: ARM: davinci_all_defconfig: Enable CPPI 4.1 USB OTG DMA CPPI 4.1 DMA is now supported on AM18xx. Update the config to use it instead of PIO mode. Signed-off-by: Alexandre Bailon Signed-off-by: Sekhar Nori --- arch/arm/configs/davinci_all_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index 8b16482f27f1..7f726277dd1b 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig @@ -177,7 +177,7 @@ CONFIG_USB_OHCI_HCD=m CONFIG_USB_STORAGE=m CONFIG_USB_MUSB_HDRC=m CONFIG_USB_MUSB_DA8XX=m -CONFIG_MUSB_PIO_ONLY=y +CONFIG_USB_TI_CPPI41_DMA=y CONFIG_USB_TEST=m CONFIG_NOP_USB_XCEIV=m CONFIG_USB_GADGET=m -- cgit v1.2.3 From 3c4ec0f9b3a1cd0365c33e53936274f81d536b94 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 24 May 2017 19:31:41 +0530 Subject: ARM: dts: da850: Add interrupt-controller property to gpio node The gpio node has 144 gpios. Each gpio is capable of generating an interrupt. Hence add interrupt-controller property to the gpio node. With this in place one can use interrupts property in device tree to request for the gpio interrupts. Signed-off-by: Keerthy Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 0bd048e0049f..af68ef7b0caa 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -528,6 +528,8 @@ ti,ngpio = <144>; ti,davinci-gpio-unbanked = <0>; status = "disabled"; + interrupt-controller; + #interrupt-cells = <2>; }; pinconf: pin-controller@22c00c { compatible = "ti,da850-pupd"; -- cgit v1.2.3 From 1515b186c2359996b50241c1c6f79ff933d5112a Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 19 May 2017 16:35:56 +0100 Subject: ARM: make configuration of userspace Thumb support an expert option David Mosberger reports random segfaults and other problems when running his buildroot userspace. It turns out that his kernel did not have support for Thumb userspace, nor did his application, but glibc made use of Thumb instructions in glibc. The kernel Thumb support option already recommends being enabled, and is also so biased, but clearly this is not enough of a recommendation. So, hide this behind CONFIG_EXPERT as well, and include a note to indicate the potential issues if it's turned off and userspace Thumb mode is made use of. Reported-by: David Mosberger Signed-off-by: Russell King --- arch/arm/mm/Kconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index c6c4c9c8824b..4f68659abe6c 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -679,7 +679,7 @@ config ARCH_DMA_ADDR_T_64BIT bool config ARM_THUMB - bool "Support Thumb user binaries" if !CPU_THUMBONLY + bool "Support Thumb user binaries" if !CPU_THUMBONLY && EXPERT depends on CPU_THUMB_CAPABLE default y help @@ -690,6 +690,10 @@ config ARM_THUMB instruction set resulting in smaller binaries at the expense of slightly less efficient code. + If this option is disabled, and you run userspace that switches to + Thumb mode, signal handling will not work correctly, resulting in + segmentation faults or illegal instruction aborts. + If you don't know what this all is, saying Y is a safe choice. config ARM_THUMBEE -- cgit v1.2.3 From 46992a17a853c537c77a99e67912c4f6317a71cb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 26 May 2017 20:06:07 +0200 Subject: ARM: dts: at91-sama5d4: use IRQ_TYPE_* to specify irq flags MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the binding documentation and the source code the atmel-gpio controller takes IRQ_TYPE_* as its flags values, not GPIO_ACTIVE_*. This patch uses the right variable type which yields the same result when compiled. Note that this might be wrong and actually IRQ_TYPE_LEVEL_LOW is intended by the dt author. Signed-off-by: Uwe Kleine-König Acked-by: Marek Vasut Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi index b5a5a91bc2ef..b813fdfa2842 100644 --- a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi +++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi @@ -75,7 +75,7 @@ reg = <0>; clocks = <&clk20m>; interrupt-parent = <&pioE>; - interrupts = <6 GPIO_ACTIVE_LOW>; + interrupts = <6 IRQ_TYPE_EDGE_RISING>; spi-max-frequency = <10000000>; }; @@ -84,7 +84,7 @@ reg = <1>; clocks = <&clk20m>; interrupt-parent = <&pioE>; - interrupts = <7 GPIO_ACTIVE_LOW>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; spi-max-frequency = <10000000>; }; }; -- cgit v1.2.3 From d9c41bf30cf8cea379f5947624e76c893791fec0 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Tue, 30 May 2017 11:20:52 +0200 Subject: ARM: dts: at91: Declare EBI/NAND controllers Declare new nodes for the EBI and NAND controllers embedded in various at91/sama5 SoCs. Signed-off-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9260.dtsi | 37 +++++++++ arch/arm/boot/dts/at91sam9261.dtsi | 32 ++++++++ arch/arm/boot/dts/at91sam9263.dtsi | 61 ++++++++++++++ arch/arm/boot/dts/at91sam9g45.dtsi | 35 ++++++++ arch/arm/boot/dts/at91sam9n12.dtsi | 42 ++++++++++ arch/arm/boot/dts/at91sam9rl.dtsi | 35 ++++++++ arch/arm/boot/dts/at91sam9x5.dtsi | 42 ++++++++++ arch/arm/boot/dts/sama5d2.dtsi | 53 ++++++++++++ arch/arm/boot/dts/sama5d3.dtsi | 113 ++++++++++++++++++++++++++ arch/arm/boot/dts/sama5d4.dtsi | 160 +++++++++++++++++++++++++++++++++++++ 10 files changed, 610 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 9e035b21e1b6..ab0e73374567 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -99,6 +99,16 @@ reg = <0xffffea00 0x200>; }; + smc: smc@ffffec00 { + compatible = "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffec00 0x200>; + }; + + matrix: matrix@ffffee00 { + compatible = "atmel,at91sam9260-matrix", "syscon"; + reg = <0xffffee00 0x200>; + }; + pmc: pmc@fffffc00 { compatible = "atmel,at91sam9260-pmc", "syscon"; reg = <0xfffffc00 0x100>; @@ -1011,6 +1021,33 @@ clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; + + ebi: ebi@10000000 { + compatible = "atmel,at91sam9260-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&smc>; + atmel,matrix = <&matrix>; + reg = <0x10000000 0x80000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x20000000 0x10000000 + 0x2 0x0 0x30000000 0x10000000 + 0x3 0x0 0x40000000 0x10000000 + 0x4 0x0 0x50000000 0x10000000 + 0x5 0x0 0x60000000 0x10000000 + 0x6 0x0 0x70000000 0x10000000 + 0x7 0x0 0x80000000 0x10000000>; + clocks = <&mck>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,at91sam9260-nand-controller"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; }; i2c-gpio-0 { diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index 7e80acda8f69..3ab0c21134f1 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -91,6 +91,33 @@ status = "disabled"; }; + ebi: ebi@10000000 { + compatible = "atmel,at91sam9261-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&smc>; + atmel,matrix = <&matrix>; + reg = <0x10000000 0x80000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x20000000 0x10000000 + 0x2 0x0 0x30000000 0x10000000 + 0x3 0x0 0x40000000 0x10000000 + 0x4 0x0 0x50000000 0x10000000 + 0x5 0x0 0x60000000 0x10000000 + 0x6 0x0 0x70000000 0x10000000 + 0x7 0x0 0x80000000 0x10000000>; + clocks = <&mck>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,at91sam9261-nand-controller"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + nand0: nand@40000000 { compatible = "atmel,at91rm9200-nand"; #address-cells = <1>; @@ -262,6 +289,11 @@ reg = <0xffffea00 0x200>; }; + smc: smc@ffffec00 { + compatible = "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffec00 0x200>; + }; + matrix: matrix@ffffee00 { compatible = "atmel,at91sam9261-matrix", "syscon"; reg = <0xffffee00 0x200>; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index a1888f6d892b..db9f3a02f2fa 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -361,11 +361,26 @@ reg = <0xffffe200 0x200>; }; + smc0: smc@ffffe400 { + compatible = "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffe400 0x200>; + }; + ramc1: ramc@ffffe800 { compatible = "atmel,at91sam9260-sdramc"; reg = <0xffffe800 0x200>; }; + smc1: smc@ffffea00 { + compatible = "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffea00 0x200>; + }; + + matrix: matrix@ffffec00 { + compatible = "atmel,at91sam9263-matrix", "syscon"; + reg = <0xffffec00 0x200>; + }; + pit: timer@fffffd30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>; @@ -1017,6 +1032,52 @@ clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; + + ebi0: ebi@10000000 { + compatible = "atmel,at91sam9263-ebi0"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&smc0>; + atmel,matrix = <&matrix>; + reg = <0x10000000 0x80000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x20000000 0x10000000 + 0x2 0x0 0x30000000 0x10000000 + 0x3 0x0 0x40000000 0x10000000 + 0x4 0x0 0x50000000 0x10000000 + 0x5 0x0 0x60000000 0x10000000>; + clocks = <&mck>; + status = "disabled"; + + nand_controller0: nand-controller { + compatible = "atmel,at91sam9260-nand-controller"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + + ebi1: ebi@70000000 { + compatible = "atmel,at91sam9263-ebi1"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&smc1>; + atmel,matrix = <&matrix>; + reg = <0x80000000 0x20000000>; + ranges = <0x0 0x0 0x80000000 0x10000000 + 0x1 0x0 0x90000000 0x10000000>; + clocks = <&mck>; + status = "disabled"; + + nand_controller1: nand-controller { + compatible = "atmel,at91sam9260-nand-controller"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; }; i2c-gpio-0 { diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index e567d5fd3f9d..392dcfb79b57 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -113,6 +113,16 @@ clock-names = "ddrck"; }; + smc: smc@ffffe800 { + compatible = "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffe800 0x200>; + }; + + matrix: matrix@ffffea00 { + compatible = "atmel,at91sam9g45-matrix", "syscon"; + reg = <0xffffea00 0x200>; + }; + pmc: pmc@fffffc00 { compatible = "atmel,at91sam9g45-pmc", "syscon"; reg = <0xfffffc00 0x100>; @@ -1314,6 +1324,31 @@ clock-names = "usb_clk", "ehci_clk"; status = "disabled"; }; + + ebi: ebi@10000000 { + compatible = "atmel,at91sam9g45-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&smc>; + atmel,matrix = <&matrix>; + reg = <0x10000000 0x80000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x20000000 0x10000000 + 0x2 0x0 0x30000000 0x10000000 + 0x3 0x0 0x40000000 0x10000000 + 0x4 0x0 0x50000000 0x10000000 + 0x5 0x0 0x60000000 0x10000000>; + clocks = <&mck>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,at91sam9g45-nand-controller"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; }; i2c-gpio-0 { diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index f43d7695352d..df06a66ace07 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -89,6 +89,17 @@ atmel,external-irqs = <31>; }; + matrix: matrix@ffffde00 { + compatible = "atmel,at91sam9n12-matrix", "syscon"; + reg = <0xffffde00 0x100>; + }; + + pmecc: ecc-engine@ffffe000 { + compatible = "atmel,at91sam9g45-pmecc"; + reg = <0xffffe000 0x600>, + <0xffffe600 0x200>; + }; + ramc0: ramc@ffffe800 { compatible = "atmel,at91sam9g45-ddramc"; reg = <0xffffe800 0x200>; @@ -96,6 +107,11 @@ clock-names = "ddrck"; }; + smc: smc@ffffea00 { + compatible = "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffea00 0x200>; + }; + pmc: pmc@fffffc00 { compatible = "atmel,at91sam9n12-pmc", "syscon"; reg = <0xfffffc00 0x200>; @@ -1028,6 +1044,32 @@ clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; + + ebi: ebi@10000000 { + compatible = "atmel,at91sam9x5-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&smc>; + atmel,matrix = <&matrix>; + reg = <0x10000000 0x60000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x20000000 0x10000000 + 0x2 0x0 0x30000000 0x10000000 + 0x3 0x0 0x40000000 0x10000000 + 0x4 0x0 0x50000000 0x10000000 + 0x5 0x0 0x60000000 0x10000000>; + clocks = <&mck>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,at91sam9g45-nand-controller"; + ecc-engine = <&pmecc>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; }; i2c-gpio-0 { diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index f4c129a98f17..d373400cddcd 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -92,6 +92,31 @@ status = "disabled"; }; + ebi: ebi@10000000 { + compatible = "atmel,at91sam9rl-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&smc>; + atmel,matrix = <&matrix>; + reg = <0x10000000 0x80000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x20000000 0x10000000 + 0x2 0x0 0x30000000 0x10000000 + 0x3 0x0 0x40000000 0x10000000 + 0x4 0x0 0x50000000 0x10000000 + 0x5 0x0 0x60000000 0x10000000>; + clocks = <&mck>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,at91sam9g45-nand-controller"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + nand0: nand@40000000 { compatible = "atmel,at91rm9200-nand"; #address-cells = <1>; @@ -364,6 +389,16 @@ reg = <0xffffea00 0x200>; }; + smc: smc@ffffec00 { + compatible = "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffec00 0x200>; + }; + + matrix: matrix@ffffee00 { + compatible = "atmel,at91sam9rl-matrix", "syscon"; + reg = <0xffffee00 0x200>; + }; + aic: interrupt-controller@fffff000 { #interrupt-cells = <3>; compatible = "atmel,at91rm9200-aic"; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index f66bae925705..7723e8b02880 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -97,6 +97,17 @@ atmel,external-irqs = <31>; }; + matrix: matrix@ffffde00 { + compatible = "atmel,at91sam9x5-matrix", "syscon"; + reg = <0xffffde00 0x100>; + }; + + pmecc: ecc-engine@ffffe000 { + compatible = "atmel,at91sam9g45-pmecc"; + reg = <0xffffe000 0x600>, + <0xffffe600 0x200>; + }; + ramc0: ramc@ffffe800 { compatible = "atmel,at91sam9g45-ddramc"; reg = <0xffffe800 0x200>; @@ -104,6 +115,11 @@ clock-names = "ddrck"; }; + smc: smc@ffffea00 { + compatible = "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffea00 0x200>; + }; + pmc: pmc@fffffc00 { compatible = "atmel,at91sam9x5-pmc", "syscon"; reg = <0xfffffc00 0x200>; @@ -1236,6 +1252,32 @@ clock-names = "usb_clk", "ehci_clk"; status = "disabled"; }; + + ebi: ebi@10000000 { + compatible = "atmel,at91sam9x5-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&smc>; + atmel,matrix = <&matrix>; + reg = <0x10000000 0x60000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x20000000 0x10000000 + 0x2 0x0 0x30000000 0x10000000 + 0x3 0x0 0x40000000 0x10000000 + 0x4 0x0 0x50000000 0x10000000 + 0x5 0x0 0x60000000 0x10000000>; + clocks = <&mck>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,at91sam9g45-nand-controller"; + ecc-engine = <&pmecc>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; }; i2c-gpio-0 { diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index ce95dcb8bdf9..e77fa36cb6f1 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -135,6 +135,12 @@ #size-cells = <1>; ranges; + nfc_sram: sram@00100000 { + compatible = "mmio-sram"; + no-memory-wc; + reg = <0x00100000 0x2400>; + }; + usb0: gadget@00300000 { #address-cells = <1>; #size-cells = <0>; @@ -291,6 +297,32 @@ cache-level = <2>; }; + ebi: ebi@10000000 { + compatible = "atmel,sama5d3-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&hsmc>; + reg = <0x10000000 0x10000000 + 0x40000000 0x30000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x60000000 0x10000000 + 0x2 0x0 0x70000000 0x10000000 + 0x3 0x0 0x80000000 0x10000000>; + clocks = <&mck>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,sama5d3-nand-controller"; + atmel,nfc-sram = <&nfc_sram>; + atmel,nfc-io = <&nfc_io>; + ecc-engine = <&pmecc>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + nand0: nand@80000000 { compatible = "atmel,sama5d2-nand"; #address-cells = <1>; @@ -347,6 +379,11 @@ status = "disabled"; }; + nfc_io: nfc-io@c0000000 { + compatible = "atmel,sama5d3-nfc-io", "syscon"; + reg = <0xc0000000 0x8000000>; + }; + apb { compatible = "simple-bus"; #address-cells = <1>; @@ -1010,6 +1047,22 @@ clock-names = "t0_clk", "slow_clk"; }; + hsmc: hsmc@f8014000 { + compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd"; + reg = <0xf8014000 0x1000>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; + clocks = <&hsmc_clk>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pmecc: ecc-engine@ffffc070 { + compatible = "atmel,sama5d2-pmecc"; + reg = <0xffffc070 0x490>, + <0xffffc500 0x100>; + }; + }; + pdmic: pdmic@f8018000 { compatible = "atmel,sama5d2-pdmic"; reg = <0xf8018000 0x124>; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index b06448ba6649..3925f83f58a6 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -429,6 +429,22 @@ clocks = <&trng_clk>; }; + hsmc: hsmc@ffffc000 { + compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd"; + reg = <0xffffc000 0x1000>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; + clocks = <&hsmc_clk>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pmecc: ecc-engine@ffffc070 { + compatible = "atmel,at91sam9g45-pmecc"; + reg = <0xffffc070 0x490>, + <0xffffc500 0x100>; + }; + }; + dma0: dma-controller@ffffe600 { compatible = "atmel,at91sam9g45-dma"; reg = <0xffffe600 0x200>; @@ -554,6 +570,66 @@ }; }; + ebi { + pinctrl_ebi_addr: ebi-addr-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_nand_addr: ebi-addr-1 { + atmel,pins = + ; + }; + + pinctrl_ebi_cs0: ebi-cs0-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_cs1: ebi-cs1-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_cs2: ebi-cs2-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_nwait: ebi-nwait-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 { + atmel,pins = + ; + }; + }; + i2c0 { pinctrl_i2c0: i2c0-0 { atmel,pins = @@ -1326,6 +1402,12 @@ }; }; + nfc_sram: sram@200000 { + compatible = "mmio-sram"; + no-memory-wc; + reg = <0x200000 0x2400>; + }; + usb0: gadget@00500000 { #address-cells = <1>; #size-cells = <0>; @@ -1461,6 +1543,32 @@ status = "disabled"; }; + ebi: ebi@10000000 { + compatible = "atmel,sama5d3-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&hsmc>; + reg = <0x10000000 0x10000000 + 0x40000000 0x30000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x40000000 0x10000000 + 0x2 0x0 0x50000000 0x10000000 + 0x3 0x0 0x60000000 0x10000000>; + clocks = <&mck>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,sama5d3-nand-controller"; + atmel,nfc-sram = <&nfc_sram>; + atmel,nfc-io = <&nfc_io>; + ecc-engine = <&pmecc>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + nand0: nand@60000000 { compatible = "atmel,at91rm9200-nand"; #address-cells = <1>; @@ -1492,5 +1600,10 @@ clocks = <&hsmc_clk>; }; }; + + nfc_io: nfc-io@70000000 { + compatible = "atmel,sama5d3-nfc-io", "syscon"; + reg = <0x70000000 0x8000000>; + }; }; }; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index d3889c9d25a9..de6bcff87745 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -124,6 +124,12 @@ #size-cells = <1>; ranges; + nfc_sram: sram@100000 { + compatible = "mmio-sram"; + no-memory-wc; + reg = <0x100000 0x2400>; + }; + usb0: gadget@00400000 { #address-cells = <1>; #size-cells = <0>; @@ -280,6 +286,32 @@ cache-level = <2>; }; + ebi: ebi@10000000 { + compatible = "atmel,sama5d3-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&hsmc>; + reg = <0x10000000 0x10000000 + 0x60000000 0x28000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x60000000 0x10000000 + 0x2 0x0 0x70000000 0x10000000 + 0x3 0x0 0x80000000 0x8000000>; + clocks = <&mck>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,sama5d3-nand-controller"; + atmel,nfc-sram = <&nfc_sram>; + atmel,nfc-io = <&nfc_io>; + ecc-engine = <&pmecc>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + nand0: nand@80000000 { compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand"; #address-cells = <1>; @@ -311,6 +343,11 @@ }; }; + nfc_io: nfc-io@90000000 { + compatible = "atmel,sama5d3-nfc-io", "syscon"; + reg = <0x90000000 0x8000000>; + }; + apb { compatible = "simple-bus"; #address-cells = <1>; @@ -1287,6 +1324,22 @@ status = "okay"; }; + hsmc: smc@fc05c000 { + compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd"; + reg = <0xfc05c000 0x1000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>; + clocks = <&hsmc_clk>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pmecc: ecc-engine@ffffc070 { + compatible = "atmel,sama5d4-pmecc"; + reg = <0xfc05c070 0x490>, + <0xfc05c500 0x100>; + }; + }; + rstc@fc068600 { compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; reg = <0xfc068600 0x10>; @@ -1447,6 +1500,113 @@ }; }; + ebi { + pinctrl_ebi_addr: ebi-addr-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_nand_addr: ebi-addr-1 { + atmel,pins = + ; + }; + + pinctrl_ebi_cs0: ebi-cs0-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_cs1: ebi-cs1-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_cs2: ebi-cs2-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_cs3: ebi-cs3-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_data_0_7: ebi-data-lsb-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_data_8_15: ebi-data-msb-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_nandrdy: ebi-nandrdy-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_nrd_nandoe: ebi-nrd-nandoe-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_nwait: ebi-nwait-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_nwe_nandwe: ebi-nwe-nandwe-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 { + atmel,pins = + ; + }; + }; + i2c0 { pinctrl_i2c0: i2c0-0 { atmel,pins = -- cgit v1.2.3 From 1004a2977bdc7566bca87c565541c3232ed467c4 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Tue, 30 May 2017 11:20:53 +0200 Subject: ARM: dts: at91: Switch to the new NAND bindings Use the new EBI/NAND bindings to declare NAND chips and remove old NAND nodes along the way. Note that we keep using old bindings in at91rm9200.dtsi because this SoC is not supported by the EBI driver. Signed-off-by: Boris Brezillon Tested-by: Peter Rosin Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/aks-cdu.dts | 56 ++++++++------- arch/arm/boot/dts/animeo_ip.dts | 53 +++++++++----- arch/arm/boot/dts/at91-cosino.dtsi | 83 ++++++++++++++-------- arch/arm/boot/dts/at91-kizbox.dts | 42 +++++++++--- arch/arm/boot/dts/at91-kizbox2.dts | 45 ++++++++---- arch/arm/boot/dts/at91-kizboxmini.dts | 52 +++++++++++--- arch/arm/boot/dts/at91-linea.dtsi | 25 +++++-- arch/arm/boot/dts/at91-qil_a9260.dts | 103 ++++++++++++++++------------ arch/arm/boot/dts/at91-sama5d3_xplained.dts | 97 +++++++++++++++----------- arch/arm/boot/dts/at91-sama5d4_xplained.dts | 83 +++++++++++++--------- arch/arm/boot/dts/at91-sama5d4ek.dts | 83 +++++++++++++--------- arch/arm/boot/dts/at91-tse850-3.dts | 70 ++++++++++--------- arch/arm/boot/dts/at91sam9260.dtsi | 28 ++------ arch/arm/boot/dts/at91sam9261.dtsi | 24 ++----- arch/arm/boot/dts/at91sam9261ek.dts | 83 +++++++++++++--------- arch/arm/boot/dts/at91sam9263.dtsi | 28 ++------ arch/arm/boot/dts/at91sam9263ek.dts | 103 ++++++++++++++++------------ arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 103 ++++++++++++++++------------ arch/arm/boot/dts/at91sam9g45.dtsi | 29 ++------ arch/arm/boot/dts/at91sam9m10g45ek.dts | 49 +++++++++---- arch/arm/boot/dts/at91sam9n12.dtsi | 32 ++------- arch/arm/boot/dts/at91sam9n12ek.dts | 26 +++++-- arch/arm/boot/dts/at91sam9rl.dtsi | 42 ++++-------- arch/arm/boot/dts/at91sam9rlek.dts | 85 ++++++++++++++--------- arch/arm/boot/dts/at91sam9x5.dtsi | 92 ++++++++++++------------- arch/arm/boot/dts/at91sam9x5cm.dtsi | 83 ++++++++++++++-------- arch/arm/boot/dts/ethernut5.dts | 47 ++++++++----- arch/arm/boot/dts/ge863-pro3.dtsi | 41 ++++++++--- arch/arm/boot/dts/pm9g45.dts | 99 ++++++++++++++------------ arch/arm/boot/dts/sama5d3.dtsi | 32 --------- arch/arm/boot/dts/sama5d3xcm.dtsi | 76 ++++++++++++-------- arch/arm/boot/dts/sama5d3xcm_cmp.dtsi | 77 +++++++++++++-------- arch/arm/boot/dts/sama5d4.dtsi | 31 --------- arch/arm/boot/dts/tny_a9260_common.dtsi | 89 ++++++++++++++---------- arch/arm/boot/dts/tny_a9263.dts | 103 ++++++++++++++++------------ arch/arm/boot/dts/usb_a9260_common.dtsi | 103 ++++++++++++++++------------ arch/arm/boot/dts/usb_a9263.dts | 103 ++++++++++++++++------------ 37 files changed, 1368 insertions(+), 1032 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/aks-cdu.dts index 5b1bf92d927c..888bfcd4a402 100644 --- a/arch/arm/boot/dts/aks-cdu.dts +++ b/arch/arm/boot/dts/aks-cdu.dts @@ -62,32 +62,36 @@ status = "okay"; }; - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - status = "okay"; - - bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x40000>; - }; - - uboot@40000 { - label = "uboot"; - reg = <0x40000 0x80000>; - }; - ubootenv@c0000 { - label = "ubootenv"; - reg = <0xc0000 0x40000>; - }; - kernel@100000 { - label = "kernel"; - reg = <0x100000 0x400000>; - }; - rootfs@500000 { - label = "rootfs"; - reg = <0x500000 0x7b00000>; + ebi: ebi@10000000 { + nand_controller: nand-controller { + nand: nand@3 { + partitions { + bootstrap@0 { + label = "bootstrap"; + reg = <0x0 0x40000>; + }; + + uboot@40000 { + label = "uboot"; + reg = <0x40000 0x80000>; + }; + + ubootenv@c0000 { + label = "ubootenv"; + reg = <0xc0000 0x40000>; + }; + + kernel@100000 { + label = "kernel"; + reg = <0x100000 0x400000>; + }; + + rootfs@500000 { + label = "rootfs"; + reg = <0x500000 0x7b00000>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts index 9cc372b9fb9b..26ade8c0a960 100644 --- a/arch/arm/boot/dts/animeo_ip.dts +++ b/arch/arm/boot/dts/animeo_ip.dts @@ -83,25 +83,44 @@ }; }; - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; + ebi: ebi@10000000 { status = "okay"; - barebox@0 { - label = "barebox"; - reg = <0x0 0x58000>; - }; - - u_boot_env@58000 { - label = "u_boot_env"; - reg = <0x58000 0x8000>; - }; - - ubi@60000 { - label = "ubi"; - reg = <0x60000 0x1FA0000>; + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + barebox@0 { + label = "barebox"; + reg = <0x0 0x58000>; + }; + + u_boot_env@58000 { + label = "u_boot_env"; + reg = <0x58000 0x8000>; + }; + + ubi@60000 { + label = "ubi"; + reg = <0x60000 0x1FA0000>; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi index 02d8ef43de3a..89cde175154e 100644 --- a/arch/arm/boot/dts/at91-cosino.dtsi +++ b/arch/arm/boot/dts/at91-cosino.dtsi @@ -82,38 +82,61 @@ }; }; - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - atmel,has-pmecc; /* Enable PMECC */ - atmel,pmecc-cap = <4>; - atmel,pmecc-sector-size = <512>; - nand-on-flash-bbt; + ebi: ebi@10000000 { + pinctrl-0 = <&pinctrl_ebi_addr_nand + &pinctrl_ebi_data_0_7>; + pinctrl-names = "default"; status = "okay"; - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - uboot@40000 { - label = "u-boot"; - reg = <0x40000 0x80000>; - }; - - ubootenv@c0000 { - label = "U-Boot Env"; - reg = <0xc0000 0x140000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_oe_we + &pinctrl_nand_cs + &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + uboot@40000 { + label = "u-boot"; + reg = <0x40000 0x80000>; + }; + + ubootenv@c0000 { + label = "U-Boot Env"; + reg = <0xc0000 0x140000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/at91-kizbox.dts b/arch/arm/boot/dts/at91-kizbox.dts index b4f147c193fd..1f31df846d61 100644 --- a/arch/arm/boot/dts/at91-kizbox.dts +++ b/arch/arm/boot/dts/at91-kizbox.dts @@ -59,19 +59,39 @@ status = "okay"; }; - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; + ebi: ebi@10000000 { status = "okay"; - bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x20000>; - }; - - ubi@20000 { - label = "ubi"; - reg = <0x20000 0x7fe0000>; + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootstrap@0 { + label = "bootstrap"; + reg = <0x0 0x20000>; + }; + + ubi@20000 { + label = "ubi"; + reg = <0x20000 0x7fe0000>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/at91-kizbox2.dts b/arch/arm/boot/dts/at91-kizbox2.dts index 50a14568f094..4372c0287c1c 100644 --- a/arch/arm/boot/dts/at91-kizbox2.dts +++ b/arch/arm/boot/dts/at91-kizbox2.dts @@ -141,23 +141,40 @@ status = "okay"; }; - nand0: nand@60000000 { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - atmel,has-pmecc; - atmel,pmecc-cap = <4>; - atmel,pmecc-sector-size = <512>; - nand-on-flash-bbt; + ebi: ebi@10000000 { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; status = "okay"; - bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x20000>; - }; + nand_controller: nand-controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootstrap@0 { + label = "bootstrap"; + reg = <0x0 0x20000>; + }; - ubi@20000 { - label = "ubi"; - reg = <0x20000 0x7fe0000>; + ubi@20000 { + label = "ubi"; + reg = <0x20000 0x7fe0000>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/at91-kizboxmini.dts b/arch/arm/boot/dts/at91-kizboxmini.dts index 9682d105d4d8..33238fcb6d0b 100644 --- a/arch/arm/boot/dts/at91-kizboxmini.dts +++ b/arch/arm/boot/dts/at91-kizboxmini.dts @@ -68,6 +68,49 @@ status = "okay"; }; + ebi: ebi@10000000 { + pinctrl-0 = <&pinctrl_ebi_addr_nand + &pinctrl_ebi_data_0_7>; + pinctrl-names = "default"; + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_oe_we + &pinctrl_nand_cs + &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootstrap@0 { + label = "bootstrap"; + reg = <0x0 0x20000>; + }; + + ubi@20000 { + label = "ubi"; + reg = <0x20000 0x7fe0000>; + }; + }; + }; + }; + }; + nand0: nand@40000000 { nand-bus-width = <8>; nand-ecc-mode = "hw"; @@ -77,15 +120,6 @@ nand-on-flash-bbt; status = "okay"; - bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x20000>; - }; - - ubi@20000 { - label = "ubi"; - reg = <0x20000 0x7fe0000>; - }; }; }; diff --git a/arch/arm/boot/dts/at91-linea.dtsi b/arch/arm/boot/dts/at91-linea.dtsi index 9bf9aaeff3e8..87e5090fb4c4 100644 --- a/arch/arm/boot/dts/at91-linea.dtsi +++ b/arch/arm/boot/dts/at91-linea.dtsi @@ -37,13 +37,24 @@ }; }; -&nand0 { +&ebi { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; status = "okay"; +}; + - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - atmel,has-pmecc; - atmel,pmecc-cap = <4>; - atmel,pmecc-sector-size = <512>; - nand-on-flash-bbt; +&nand_controller { + status = "okay"; + + nand: nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + }; }; diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/at91-qil_a9260.dts index 8f019184fccf..f46352790a41 100644 --- a/arch/arm/boot/dts/at91-qil_a9260.dts +++ b/arch/arm/boot/dts/at91-qil_a9260.dts @@ -107,50 +107,69 @@ status = "okay"; }; - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; + ebi: ebi@10000000 { status = "okay"; - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@a0000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@c0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4c0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7cc0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; + + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + oftree@a0000 { + label = "oftree"; + reg = <0xa0000 0x20000>; + }; + + kernel@c0000 { + label = "kernel"; + reg = <0xc0000 0x400000>; + }; + + rootfs@4c0000 { + label = "rootfs"; + reg = <0x4c0000 0x7800000>; + }; + + data@7cc0000 { + label = "data"; + reg = <0x7cc0000 0x8340000>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts index 5a53fcf542ab..3af088d2cba7 100644 --- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts @@ -235,46 +235,6 @@ }; }; - nand0: nand@60000000 { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - atmel,has-pmecc; - atmel,pmecc-cap = <4>; - atmel,pmecc-sector-size = <512>; - nand-on-flash-bbt; - status = "okay"; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; - - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - usb0: gadget@00500000 { atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; /* PE9, conflicts with A9 */ pinctrl-names = "default"; @@ -294,6 +254,63 @@ usb2: ehci@00700000 { status = "okay"; }; + + ebi: ebi@10000000 { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + }; + }; }; vcc_mmc0_reg: fixedregulator_mmc0 { diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts index 5ab14cedb1db..cf712444b2c2 100644 --- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts @@ -190,41 +190,60 @@ status = "okay"; }; - nand0: nand@80000000 { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - atmel,has-pmecc; + ebi: ebi@10000000 { + pinctrl-0 = <&pinctrl_ebi_cs3 &pinctrl_ebi_nrd_nandoe + &pinctrl_ebi_nwe_nandwe &pinctrl_ebi_nandrdy + &pinctrl_ebi_data_0_7 &pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; status = "okay"; - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; - - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; + nand_controller: nand-controller { + status = "okay"; - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts index f8b96cef5e1a..bae5248f126e 100644 --- a/arch/arm/boot/dts/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts @@ -236,41 +236,60 @@ status = "okay"; }; - nand0: nand@80000000 { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - atmel,has-pmecc; + ebi: ebi@10000000 { + pinctrl-0 = <&pinctrl_ebi_cs3 &pinctrl_ebi_nrd_nandoe + &pinctrl_ebi_nwe_nandwe &pinctrl_ebi_nandrdy + &pinctrl_ebi_data_0_7 &pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; status = "okay"; - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; - - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; + nand_controller: nand-controller { + status = "okay"; - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/at91-tse850-3.dts b/arch/arm/boot/dts/at91-tse850-3.dts index a5c0dd630253..5f29010cdbd8 100644 --- a/arch/arm/boot/dts/at91-tse850-3.dts +++ b/arch/arm/boot/dts/at91-tse850-3.dts @@ -161,45 +161,51 @@ }; }; -&nand0 { - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; +&nand { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; - barebox@40000 { - label = "bootloader"; - reg = <0x40000 0x60000>; - }; + barebox@40000 { + label = "bootloader"; + reg = <0x40000 0x60000>; + }; - bareboxenv@c0000 { - label = "bareboxenv"; - reg = <0xc0000 0x40000>; - }; + bareboxenv@c0000 { + label = "bareboxenv"; + reg = <0xc0000 0x40000>; + }; - bareboxenv2@100000 { - label = "bareboxenv2"; - reg = <0x100000 0x40000>; - }; + bareboxenv2@100000 { + label = "bareboxenv2"; + reg = <0x100000 0x40000>; + }; - oftree@180000 { - label = "oftree"; - reg = <0x180000 0x20000>; - }; + oftree@180000 { + label = "oftree"; + reg = <0x180000 0x20000>; + }; - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x500000>; - }; + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x500000>; + }; - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; - ovlfs@10000000 { - label = "ovlfs"; - reg = <0x10000000 0x10000000>; + ovlfs@10000000 { + label = "ovlfs"; + reg = <0x10000000 0x10000000>; + }; }; }; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index ab0e73374567..6582f3cca929 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -532,10 +532,14 @@ }; nand { - pinctrl_nand: nand-0 { + pinctrl_nand_rb: nand-rb-0 { atmel,pins = - ; /* PC14 gpio enable pin pull_up */ + ; + }; + + pinctrl_nand_cs: nand-cs-0 { + atmel,pins = + ; }; }; @@ -995,24 +999,6 @@ }; }; - nand0: nand@40000000 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x10000000 - 0xffffe800 0x200 - >; - atmel,nand-addr-offset = <21>; - atmel,nand-cmd-offset = <22>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioC 13 GPIO_ACTIVE_HIGH - &pioC 14 GPIO_ACTIVE_HIGH - 0 - >; - status = "disabled"; - }; - usb0: ohci@500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index 3ab0c21134f1..a05353f96151 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -118,22 +118,6 @@ }; }; - nand0: nand@40000000 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x10000000>; - atmel,nand-addr-offset = <22>; - atmel,nand-cmd-offset = <21>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - - gpios = <&pioC 15 GPIO_ACTIVE_HIGH>, - <&pioC 14 GPIO_ACTIVE_HIGH>, - <0>; - status = "disabled"; - }; - apb { compatible = "simple-bus"; #address-cells = <1>; @@ -394,9 +378,13 @@ }; nand { - pinctrl_nand: nand-0 { + pinctrl_nand_rb: nand-rb-0 { + atmel,pins = + ; + }; + + pinctrl_nand_cs: nand-cs-0 { atmel,pins = - , ; }; }; diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts index 55bd51f07fa6..157e1493e6eb 100644 --- a/arch/arm/boot/dts/at91sam9261ek.dts +++ b/arch/arm/boot/dts/at91sam9261ek.dts @@ -68,40 +68,59 @@ }; }; - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; + ebi: ebi@10000000 { status = "okay"; - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; - - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioC 15 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index db9f3a02f2fa..ed4b564f8de5 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -487,10 +487,14 @@ }; nand { - pinctrl_nand: nand-0 { + pinctrl_nand_rb: nand-rb-0 { atmel,pins = - ; /* PD15 gpio enable pin pull_up */ + ; + }; + + pinctrl_nand_cs: nand-cs-0 { + atmel,pins = + ; }; }; @@ -1006,24 +1010,6 @@ status = "disabled"; }; - nand0: nand@40000000 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x10000000 - 0xffffe000 0x200 - >; - atmel,nand-addr-offset = <21>; - atmel,nand-cmd-offset = <22>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioA 22 GPIO_ACTIVE_HIGH - &pioD 15 GPIO_ACTIVE_HIGH - 0 - >; - status = "disabled"; - }; - usb0: ohci@00a00000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00a00000 0x100000>; diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts index 127cc42e9e29..10a0925da10e 100644 --- a/arch/arm/boot/dts/at91sam9263ek.dts +++ b/arch/arm/boot/dts/at91sam9263ek.dts @@ -125,50 +125,69 @@ }; }; - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt = <1>; + ebi0: ebi@10000000 { status = "okay"; - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; + + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + oftree@80000 { + label = "oftree"; + reg = <0xa0000 0x20000>; + }; + + kernel@a0000 { + label = "kernel"; + reg = <0xc0000 0x400000>; + }; + + rootfs@4a0000 { + label = "rootfs"; + reg = <0x4c0000 0x7800000>; + }; + + data@7ca0000 { + label = "data"; + reg = <0x7cc0000 0x8340000>; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index 27847a47c108..ac9a1511e239 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi @@ -123,50 +123,69 @@ }; }; - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; + ebi: ebi@10000000 { status = "okay"; - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; + + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + oftree@80000 { + label = "oftree"; + reg = <0xa0000 0x20000>; + }; + + kernel@a0000 { + label = "kernel"; + reg = <0xc0000 0x400000>; + }; + + rootfs@4a0000 { + label = "rootfs"; + reg = <0x4c0000 0x7800000>; + }; + + data@7ca0000 { + label = "data"; + reg = <0x7cc0000 0x8340000>; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 392dcfb79b57..a4808c4fbc05 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -611,10 +611,14 @@ }; nand { - pinctrl_nand: nand-0 { + pinctrl_nand_rb: nand-rb-0 { atmel,pins = - ; /* PC14 gpio enable pin pull_up */ + ; + }; + + pinctrl_nand_cs: nand-cs-0 { + atmel,pins = + ; }; }; @@ -1288,25 +1292,6 @@ status = "disabled"; }; - nand0: nand@40000000 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x10000000 - 0xffffe200 0x200 - >; - atmel,nand-addr-offset = <21>; - atmel,nand-cmd-offset = <22>; - atmel,nand-has-dma; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioC 8 GPIO_ACTIVE_HIGH - &pioC 14 GPIO_ACTIVE_HIGH - 0 - >; - status = "disabled"; - }; - usb0: ohci@00700000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00700000 0x100000>; diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 2400c99134f7..2522c3308305 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -245,25 +245,44 @@ }; }; - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; + ebi: ebi@10000000 { status = "okay"; - boot@0 { - label = "bootstrap/uboot/kernel"; - reg = <0x0 0x400000>; - }; + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; - rootfs@400000 { - label = "rootfs"; - reg = <0x400000 0x3C00000>; - }; + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioC 8 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + label = "bootstrap/uboot/kernel"; + reg = <0x0 0x400000>; + }; - data@4000000 { - label = "data"; - reg = <0x4000000 0xC000000>; + rootfs@400000 { + label = "rootfs"; + reg = <0x400000 0x3C00000>; + }; + + data@4000000 { + label = "data"; + reg = <0x4000000 0xC000000>; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index df06a66ace07..06516d02d351 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -643,10 +643,14 @@ }; nand { - pinctrl_nand: nand-0 { + pinctrl_nand_rb: nand-rb-0 { atmel,pins = - ; /* PD4 gpio enable pin pull_up */ + ; + }; + + pinctrl_nand_cs: nand-cs-0 { + atmel,pins = + ; }; }; @@ -1014,28 +1018,6 @@ }; }; - nand0: nand@40000000 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = < 0x40000000 0x10000000 - 0xffffe000 0x00000600 - 0xffffe600 0x00000200 - 0x00108000 0x00018000 - >; - atmel,pmecc-lookup-table-offset = <0x0 0x8000>; - atmel,nand-addr-offset = <21>; - atmel,nand-cmd-offset = <22>; - atmel,nand-has-dma; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioD 5 GPIO_ACTIVE_HIGH - &pioD 4 GPIO_ACTIVE_HIGH - 0 - >; - status = "disabled"; - }; - usb0: ohci@00500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x00100000>; diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index 626c67d66626..5bea8c59b115 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -147,14 +147,26 @@ }; }; - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - atmel,has-pmecc; - atmel,pmecc-cap = <2>; - atmel,pmecc-sector-size = <512>; - nand-on-flash-bbt; + ebi: ebi@10000000 { status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-ecc-strength = <2>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + }; + }; }; usb0: ohci@00500000 { diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index d373400cddcd..7768342a6638 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -117,23 +117,6 @@ }; }; - nand0: nand@40000000 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x10000000>, - <0xffffe800 0x200>; - atmel,nand-addr-offset = <21>; - atmel,nand-cmd-offset = <22>; - atmel,nand-has-dma; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioD 17 GPIO_ACTIVE_HIGH>, - <&pioB 6 GPIO_ACTIVE_HIGH>, - <0>; - status = "disabled"; - }; - apb { compatible = "simple-bus"; #address-cells = <1>; @@ -478,6 +461,14 @@ }; }; + ebi { + pinctrl_ebi_addr_nand: ebi-addr-0 { + atmel,pins = + , + ; + }; + }; + fb { pinctrl_fb: fb-0 { atmel,pins = @@ -542,28 +533,21 @@ }; nand { - pinctrl_nand: nand-0 { + pinctrl_nand_rb: nand-rb-0 { atmel,pins = - , - ; + ; }; - pinctrl_nand0_ale_cle: nand_ale_cle-0 { + pinctrl_nand_cs: nand-cs-0 { atmel,pins = - , - ; + ; }; - pinctrl_nand0_oe_we: nand_oe_we-0 { + pinctrl_nand_oe_we: nand-oe-we-0 { atmel,pins = , ; }; - - pinctrl_nand0_cs: nand_cs-0 { - atmel,pins = - ; - }; }; pwm0 { diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts index 2e567d90fba8..9047c168298a 100644 --- a/arch/arm/boot/dts/at91sam9rlek.dts +++ b/arch/arm/boot/dts/at91sam9rlek.dts @@ -63,40 +63,63 @@ }; }; - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt = <1>; + ebi: ebi@10000000 { + pinctrl-0 = <&pinctrl_ebi_addr_nand>; + pinctrl-names = "default"; status = "okay"; - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; - - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_oe_we + &pinctrl_nand_cs + &pinctrl_nand_rb>; + pinctrl-names = "default"; - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioB 6 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 7723e8b02880..57f307541d2e 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -481,6 +481,38 @@ }; }; + ebi { + pinctrl_ebi_data_0_7: ebi-data-lsb-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_data_8_15: ebi-data-msb-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_addr_nand: ebi-addr-0 { + atmel,pins = + ; + }; + }; + usart0 { pinctrl_usart0: usart0-0 { atmel,pins = @@ -567,34 +599,20 @@ }; nand { - pinctrl_nand: nand-0 { + pinctrl_nand_oe_we: nand-oe-we-0 { atmel,pins = - ; /* PD13 periph A Data bit 7 */ - }; - - pinctrl_nand_16bits: nand_16bits-0 { + ; + }; + + pinctrl_nand_rb: nand-rb-0 { + atmel,pins = + ; + }; + + pinctrl_nand_cs: nand-cs-0 { atmel,pins = - ; /* PD21 periph A Data bit 15 */ + ; }; }; @@ -1213,28 +1231,6 @@ }; }; - nand0: nand@40000000 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x10000000 - 0xffffe000 0x600 /* PMECC Registers */ - 0xffffe600 0x200 /* PMECC Error Location Registers */ - 0x00108000 0x18000 /* PMECC looup table in ROM code */ - >; - atmel,pmecc-lookup-table-offset = <0x0 0x8000>; - atmel,nand-addr-offset = <21>; - atmel,nand-cmd-offset = <22>; - atmel,nand-has-dma; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioD 5 GPIO_ACTIVE_HIGH - &pioD 4 GPIO_ACTIVE_HIGH - 0 - >; - status = "disabled"; - }; - usb0: ohci@00600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi index b098ad8cd93a..bdeaa0b64a5b 100644 --- a/arch/arm/boot/dts/at91sam9x5cm.dtsi +++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi @@ -37,38 +37,61 @@ }; }; - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - atmel,has-pmecc; /* Enable PMECC */ - atmel,pmecc-cap = <2>; - atmel,pmecc-sector-size = <512>; - nand-on-flash-bbt; + ebi: ebi@10000000 { + pinctrl-0 = <&pinctrl_ebi_addr_nand + &pinctrl_ebi_data_0_7>; + pinctrl-names = "default"; status = "okay"; - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - uboot@40000 { - label = "u-boot"; - reg = <0x40000 0x80000>; - }; - - ubootenv@c0000 { - label = "U-Boot Env"; - reg = <0xc0000 0x140000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x1f800000>; + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_oe_we + &pinctrl_nand_cs + &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <2>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + uboot@40000 { + label = "u-boot"; + reg = <0x40000 0x80000>; + }; + + ubootenv@c0000 { + label = "U-Boot Env"; + reg = <0xc0000 0x140000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x1f800000>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts index 4687229a3ab9..123b203be06c 100644 --- a/arch/arm/boot/dts/ethernut5.dts +++ b/arch/arm/boot/dts/ethernut5.dts @@ -55,25 +55,38 @@ }; }; - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; + ebi: ebi@10000000 { status = "okay"; - gpios = <0 - &pioC 14 GPIO_ACTIVE_HIGH - 0 - >; - - root@0 { - label = "root"; - reg = <0x0 0x08000000>; - }; - - data@20000 { - label = "data"; - reg = <0x08000000 0x38000000>; + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs>; + pinctrl-names = "default"; + + nand: nand@3 { + reg = <0x3 0x0 0x800000>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + root@0 { + label = "root"; + reg = <0x0 0x08000000>; + }; + + data@20000 { + label = "data"; + reg = <0x08000000 0x38000000>; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi index 4aee5cc75fa4..8613944ea5c5 100644 --- a/arch/arm/boot/dts/ge863-pro3.dtsi +++ b/arch/arm/boot/dts/ge863-pro3.dtsi @@ -23,20 +23,39 @@ }; }; - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; + ebi: ebi@10000000 { status = "okay"; - boot@0 { - label = "boot"; - reg = <0x0 0x7c0000>; - }; + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + label = "boot"; + reg = <0x0 0x7c0000>; + }; - root@07c0000 { - label = "root"; - reg = <0x7c0000 0x7840000>; + root@07c0000 { + label = "root"; + reg = <0x7c0000 0x7840000>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts index 0abd7bf17568..3139221737ee 100644 --- a/arch/arm/boot/dts/pm9g45.dts +++ b/arch/arm/boot/dts/pm9g45.dts @@ -37,12 +37,10 @@ }; pinctrl@fffff200 { - - board { - pinctrl_board_nand: nand0-board { + nand { + pinctrl_nand_rb: nand-rb-0 { atmel,pins = - ; /* PC14 gpio enable pin pull_up */ + ; }; }; @@ -71,50 +69,61 @@ phy-mode = "rmii"; status = "okay"; }; - }; - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - pinctrl-0 = <&pinctrl_board_nand>; - - gpios = <&pioD 3 GPIO_ACTIVE_HIGH - &pioC 14 GPIO_ACTIVE_HIGH - 0 - >; - + ebi: ebi@10000000 { status = "okay"; - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x1A0000>; - }; - - kernel@200000 { - label = "bareboxenv2"; - reg = <0x200000 0x300000>; - }; - - kernel@500000 { - label = "root"; - reg = <0x500000 0x400000>; - }; - - data@900000 { - label = "data"; - reg = <0x900000 0x8340000>; + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioD 3 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x1A0000>; + }; + + kernel@200000 { + label = "bareboxenv2"; + reg = <0x200000 0x300000>; + }; + + kernel@500000 { + label = "root"; + reg = <0x500000 0x400000>; + }; + + data@900000 { + label = "data"; + reg = <0x900000 0x8340000>; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 3925f83f58a6..554d0bdedc7a 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -1569,38 +1569,6 @@ }; }; - nand0: nand@60000000 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = < 0x60000000 0x01000000 /* EBI CS3 */ - 0xffffc070 0x00000490 /* SMC PMECC regs */ - 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ - 0x00110000 0x00018000 /* ROM code */ - >; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; - atmel,nand-addr-offset = <21>; - atmel,nand-cmd-offset = <22>; - atmel,nand-has-dma; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand0_ale_cle>; - atmel,pmecc-lookup-table-offset = <0x0 0x8000>; - status = "disabled"; - - nfc@70000000 { - compatible = "atmel,sama5d3-nfc"; - #address-cells = <1>; - #size-cells = <1>; - reg = < - 0x70000000 0x08000000 /* NFC Command Registers */ - 0xffffc000 0x00000070 /* NFC HSMC regs */ - 0x00200000 0x00100000 /* NFC SRAM banks */ - >; - clocks = <&hsmc_clk>; - }; - }; - nfc_io: nfc-io@70000000 { compatible = "atmel,sama5d3-nfc-io", "syscon"; reg = <0x70000000 0x8000000>; diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index b5e111b29da1..4606e1d7e6f2 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -36,43 +36,59 @@ }; }; - nand0: nand@60000000 { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - atmel,has-pmecc; - atmel,pmecc-cap = <4>; - atmel,pmecc-sector-size = <512>; - nand-on-flash-bbt; + ebi@10000000 { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; status = "okay"; - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; + nand_controller: nand-controller { + status = "okay"; - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi b/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi index dc7572bc7ff0..75cbf4d4ab1a 100644 --- a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi @@ -148,43 +148,60 @@ }; }; - nand0: nand@60000000 { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - atmel,has-pmecc; - atmel,pmecc-cap = <4>; - atmel,pmecc-sector-size = <512>; - nand-on-flash-bbt; + ebi: ebi@10000000 { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; status = "okay"; - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; + nand_controller: nand-controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index de6bcff87745..2fa36c525957 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -312,37 +312,6 @@ }; }; - nand0: nand@80000000 { - compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = < 0x80000000 0x08000000 /* EBI CS3 */ - 0xfc05c070 0x00000490 /* SMC PMECC regs */ - 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */ - >; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>; - atmel,nand-addr-offset = <21>; - atmel,nand-cmd-offset = <22>; - atmel,nand-has-dma; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - status = "disabled"; - - nfc@90000000 { - compatible = "atmel,sama5d3-nfc"; - #address-cells = <1>; - #size-cells = <1>; - reg = < - 0x90000000 0x08000000 /* NFC Command Registers */ - 0xfc05c000 0x00000070 /* NFC HSMC regs */ - 0x00100000 0x00100000 /* NFC SRAM banks */ - >; - clocks = <&hsmc_clk>; - atmel,write-by-sram; - }; - }; - nfc_io: nfc-io@90000000 { compatible = "atmel,sama5d3-nfc-io", "syscon"; reg = <0x90000000 0x8000000>; diff --git a/arch/arm/boot/dts/tny_a9260_common.dtsi b/arch/arm/boot/dts/tny_a9260_common.dtsi index f9dc463b9e48..5d83df4675a1 100644 --- a/arch/arm/boot/dts/tny_a9260_common.dtsi +++ b/arch/arm/boot/dts/tny_a9260_common.dtsi @@ -32,50 +32,69 @@ }; }; - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; + ebi: ebi@10000000 { status = "okay"; - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + oftree@80000 { + label = "oftree"; + reg = <0xa0000 0x20000>; + }; + + kernel@a0000 { + label = "kernel"; + reg = <0xc0000 0x400000>; + }; + + rootfs@4a0000 { + label = "rootfs"; + reg = <0x4c0000 0x7800000>; + }; - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; + data@7ca0000 { + label = "data"; + reg = <0x7cc0000 0x8340000>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts index 9161cd9889b4..8cf0a9e08571 100644 --- a/arch/arm/boot/dts/tny_a9263.dts +++ b/arch/arm/boot/dts/tny_a9263.dts @@ -42,50 +42,69 @@ }; }; - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; + ebi0: ebi@10000000 { status = "okay"; - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; + + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + oftree@80000 { + label = "oftree"; + reg = <0xa0000 0x20000>; + }; + + kernel@a0000 { + label = "kernel"; + reg = <0xc0000 0x400000>; + }; + + rootfs@4a0000 { + label = "rootfs"; + reg = <0x4c0000 0x7800000>; + }; + + data@7ca0000 { + label = "data"; + reg = <0x7cc0000 0x8340000>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi index 7514b347cdd2..34a49995eda3 100644 --- a/arch/arm/boot/dts/usb_a9260_common.dtsi +++ b/arch/arm/boot/dts/usb_a9260_common.dtsi @@ -34,50 +34,69 @@ }; }; - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; + ebi: ebi@10000000 { status = "okay"; - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; + + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + oftree@80000 { + label = "oftree"; + reg = <0xa0000 0x20000>; + }; + + kernel@a0000 { + label = "kernel"; + reg = <0xc0000 0x400000>; + }; + + rootfs@4a0000 { + label = "rootfs"; + reg = <0x4c0000 0x7800000>; + }; + + data@7ca0000 { + label = "data"; + reg = <0x7cc0000 0x8340000>; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts index bfc48a272417..482381c1c962 100644 --- a/arch/arm/boot/dts/usb_a9263.dts +++ b/arch/arm/boot/dts/usb_a9263.dts @@ -62,50 +62,69 @@ }; }; - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; + ebi0: ebi@10000000 { status = "okay"; - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; + nand_controller: nand-controller { + status = "okay"; + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; + pinctrl-names = "default"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; + + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + oftree@80000 { + label = "oftree"; + reg = <0xa0000 0x20000>; + }; + + kernel@a0000 { + label = "kernel"; + reg = <0xc0000 0x400000>; + }; + + rootfs@4a0000 { + label = "rootfs"; + reg = <0x4c0000 0x7800000>; + }; + + data@7ca0000 { + label = "data"; + reg = <0x7cc0000 0x8340000>; + }; + }; + }; }; }; -- cgit v1.2.3 From 07c0986d6e850548fbe7707fbcfb47127aa0c0a9 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Tue, 30 May 2017 11:20:54 +0200 Subject: ARM: dts: at91: Add the NOR flash available on sama5d3 dev kits sama5d3 CPU modules embed a parallel NOR flash connected to the EBI bus. Signed-off-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/sama5d3xcm.dtsi | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index 4606e1d7e6f2..9506daf5efb6 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -37,10 +37,33 @@ }; ebi@10000000 { - pinctrl-0 = <&pinctrl_ebi_nand_addr>; - pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ebi_addr &pinctrl_ebi_cs0>; + pinctr-name = "default"; status = "okay"; + nor: flash@0,0 { + compatible = "cfi-flash"; + linux,mtd-name = "physmap-flash.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x0 0x1000000>; + bank-width = <2>; + atmel,smc-read-mode = "nrd"; + atmel,smc-write-mode = "nwe"; + atmel,smc-bus-width = <16>; + atmel,smc-ncs-rd-setup-ns = <0>; + atmel,smc-ncs-wr-setup-ns = <0>; + atmel,smc-nwe-setup-ns = <8>; + atmel,smc-nrd-setup-ns = <16>; + atmel,smc-ncs-rd-pulse-ns = <84>; + atmel,smc-ncs-wr-pulse-ns = <84>; + atmel,smc-nrd-pulse-ns = <76>; + atmel,smc-nwe-pulse-ns = <76>; + atmel,smc-nrd-cycle-ns = <107>; + atmel,smc-nwe-cycle-ns = <84>; + atmel,smc-tdf-ns = <16>; + }; + nand_controller: nand-controller { status = "okay"; -- cgit v1.2.3 From eb0b59d49bf46670414acd7b9b32c0db7c856f3e Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 31 May 2017 12:23:12 +0300 Subject: ARM: dts: at91: sama5d2_xplained: add pwm controller Add pwm controller bindings for sama5d2_xplained and enable it. Signed-off-by: Claudiu Beznea Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 4 ++++ arch/arm/boot/dts/sama5d2.dtsi | 8 ++++++++ 2 files changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index 37de94fc9b5a..dbce6f7a73dd 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -227,6 +227,10 @@ }; }; + pwm0: pwm@f802c000 { + status = "okay"; + }; + flx0: flexcom@f8034000 { atmel,flexcom-mode = ; status = "disabled"; /* conflict with ISC_D2 & ISC_D3 data pins */ diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index e77fa36cb6f1..cc06da394366 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -1142,6 +1142,14 @@ status = "disabled"; }; + pwm0: pwm@f802c000 { + compatible = "atmel,sama5d2-pwm"; + reg = <0xf802c000 0x4000>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>; + #pwm-cells = <3>; + clocks = <&pwm_clk>; + }; + sfr: sfr@f8030000 { compatible = "atmel,sama5d2-sfr", "syscon"; reg = <0xf8030000 0x98>; -- cgit v1.2.3 From c56ee52622cef6c8110b5e9eebf35513d3a93544 Mon Sep 17 00:00:00 2001 From: Rick Chang Date: Wed, 14 Dec 2016 16:04:49 +0800 Subject: arm: dts: mt2701: Add node for Mediatek JPEG Decoder Signed-off-by: Rick Chang Signed-off-by: Minghsiu Tsai [mb: include mt2701-larb-port.h to fix build errors] Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt2701.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 18a851b266d4..15537bc47d48 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -16,6 +16,7 @@ #include #include #include +#include #include #include "skeleton64.dtsi" #include "mt2701-pinfunc.h" @@ -414,6 +415,20 @@ power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; }; + jpegdec: jpegdec@15004000 { + compatible = "mediatek,mt2701-jpgdec"; + reg = <0 0x15004000 0 0x1000>; + interrupts = ; + clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, + <&imgsys CLK_IMG_JPGDEC>; + clock-names = "jpgdec-smi", + "jpgdec"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; + mediatek,larb = <&larb2>; + iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, + <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; + }; + vdecsys: syscon@16000000 { compatible = "mediatek,mt2701-vdecsys", "syscon"; reg = <0 0x16000000 0 0x1000>; -- cgit v1.2.3 From 729b7f8dbdaff270c53052897ea06486221a49a2 Mon Sep 17 00:00:00 2001 From: Jun Gao Date: Fri, 26 May 2017 15:35:07 +0800 Subject: arm: dts: Add Mediatek MT2701 i2c device node Add MT2701 i2c device node. Signed-off-by: Jun Gao Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt2701-evb.dts | 42 ++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/mt2701.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 84 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts index 0474fd2d602b..98bf12c141cb 100644 --- a/arch/arm/boot/dts/mt2701-evb.dts +++ b/arch/arm/boot/dts/mt2701-evb.dts @@ -28,7 +28,49 @@ status = "okay"; }; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + &pio { + i2c0_pins_a: i2c0@0 { + pins1 { + pinmux = , + ; + bias-disable; + }; + }; + + i2c1_pins_a: i2c1@0 { + pins1 { + pinmux = , + ; + bias-disable; + }; + }; + + i2c2_pins_a: i2c2@0 { + pins1 { + pinmux = , + ; + bias-disable; + }; + }; + spi_pins_a: spi0@0 { pins_spi { pinmux = , diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 15537bc47d48..50a483ce5c47 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -297,6 +297,48 @@ status = "disabled"; }; + i2c0: i2c@11007000 { + compatible = "mediatek,mt2701-i2c", + "mediatek,mt6577-i2c"; + reg = <0 0x11007000 0 0x70>, + <0 0x11000200 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt2701-i2c", + "mediatek,mt6577-i2c"; + reg = <0 0x11008000 0 0x70>, + <0 0x11000280 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt2701-i2c", + "mediatek,mt6577-i2c"; + reg = <0 0x11009000 0 0x70>, + <0 0x11000300 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spi0: spi@1100a000 { compatible = "mediatek,mt2701-spi"; #address-cells = <1>; -- cgit v1.2.3 From 5e7e276a9c3fa4a33aee712f5e28776140895775 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 24 May 2017 11:43:41 +0300 Subject: ARM: dts: am43xx-clocks: Add support for CLKOUT2 Add the needed clock nodes for the CLKOUT2 to be usable by boards. Signed-off-by: Peter Ujfalusi Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am43xx-clocks.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index d1d73b725f47..430be5829f8f 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -833,4 +833,40 @@ ti,bit-shift = <23>; reg = <0x4100>; }; + + clkout2_src_mux_ck: clkout2_src_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, + <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, + <&dpll_mpu_m2_ck>, <&dpll_extdev_ck>; + reg = <0x4108>; + }; + + clkout2_pre_div_ck: clkout2_pre_div_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&clkout2_src_mux_ck>; + ti,bit-shift = <4>; + ti,max-div = <8>; + reg = <0x4108>; + }; + + clkout2_post_div_ck: clkout2_post_div_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&clkout2_pre_div_ck>; + ti,bit-shift = <8>; + ti,max-div = <32>; + ti,index-power-of-two; + reg = <0x4108>; + }; + + clkout2_ck: clkout2_ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkout2_post_div_ck>; + ti,bit-shift = <16>; + reg = <0x4108>; + }; }; -- cgit v1.2.3 From 44fc41f92694241917a1590eb03081a68a38f480 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 24 May 2017 17:58:34 +0200 Subject: ARM: s3c64xx: Do not select ARM_AMBA from S3C64XX_PL080 While trying a fix a build warning unrelated to s3c64xx, I ran into a circular dependency: drivers/i2c/Kconfig:7: symbol I2C is selected by FB_DDC drivers/video/fbdev/Kconfig:63: symbol FB_DDC is selected by FB_CYBER2000_DDC drivers/video/fbdev/Kconfig:381: symbol FB_CYBER2000_DDC depends on FB_CYBER2000 drivers/video/fbdev/Kconfig:369: symbol FB_CYBER2000 depends on FB drivers/video/fbdev/Kconfig:5: symbol FB is selected by DRM_KMS_FB_HELPER drivers/gpu/drm/Kconfig:72: symbol DRM_KMS_FB_HELPER is selected by DRM_KMS_CMA_HELPER drivers/gpu/drm/Kconfig:137: symbol DRM_KMS_CMA_HELPER is selected by DRM_PL111 drivers/gpu/drm/pl111/Kconfig:1: symbol DRM_PL111 depends on ARM_AMBA drivers/amba/Kconfig:1: symbol ARM_AMBA is selected by S3C64XX_PL080 arch/arm/mach-s3c64xx/Kconfig:42: symbol S3C64XX_PL080 default value contains DMADEVICES drivers/dma/Kconfig:5: symbol DMADEVICES is selected by SND_SOC_SH4_SIU sound/soc/sh/Kconfig:29: symbol SND_SOC_SH4_SIU is selected by SND_SIU_MIGOR sound/soc/sh/Kconfig:59: symbol SND_SIU_MIGOR depends on I2C The I2C and FB dependencies are hard to untangle, but I notice that S3C64XX_PL080 selecting ARM_AMBA is one piece of the puzzle that can easily be avoided, as ARCH_S3C64XX already select ARM_AMBA. Removing the redundant 'select' now can help us in the future if we run into a variation of the same dependency. Signed-off-by: Arnd Bergmann Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-s3c64xx/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 459214fa20b4..5ee5ad74a3d6 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -40,7 +40,6 @@ config CPU_S3C6410 config S3C64XX_PL080 def_bool DMADEVICES - select ARM_AMBA select AMBA_PL08X config S3C64XX_SETUP_SDHCI -- cgit v1.2.3 From 2ed2388bc0c5b7d04c7b079d673ce61a0333c818 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 30 May 2017 17:42:50 +0000 Subject: ARM: dts: sun8i: h3: Add initial NanoPi M1 Plus support NanoPi M1 Plus is designed and developed by FriendlyElec for professionals, enterprise users, makers and hobbyists using the Allwinner H3 SOC. NanoPi M1 Plus key features - Allwinner H3, Quad-core Cortex-A7@1.2GHz - 1GB DDR3 RAM - 8GB eMMC - microSD slot - 10/100/1000M Ethernet - Serial Debug Port - 5V 2A DC power-supply Signed-off-by: Jagan Teki Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 64 +++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 929a4167fcaa..2d9b5b0b5747 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -895,6 +895,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-bananapi-m2-plus.dtb \ sun8i-h3-beelink-x2.dtb \ sun8i-h3-nanopi-m1.dtb \ + sun8i-h3-nanopi-m1-plus.dtb \ sun8i-h3-nanopi-neo.dtb \ sun8i-h3-nanopi-neo-air.dtb \ sun8i-h3-orangepi-2.dtb \ diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts new file mode 100644 index 000000000000..8ddd1b2cc097 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2017 Jagan Teki + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun8i-h3-nanopi.dtsi" + +/ { + model = "FriendlyArm NanoPi M1 Plus"; + compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; -- cgit v1.2.3 From 4d8061a5918dea53402170932a861c09f3b88df5 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Sun, 21 May 2017 10:23:36 +0000 Subject: crypto: arm/aes-ce - enable module autoloading based on CPU feature bits Make the module autoloadable by tying it to the CPU feature bit that describes whether the optional instructions it relies on are implemented by the current CPU. Signed-off-by: Ard Biesheuvel Signed-off-by: Herbert Xu --- arch/arm/crypto/aes-ce-glue.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/crypto/aes-ce-glue.c b/arch/arm/crypto/aes-ce-glue.c index 883b84d828c5..0f966a8ca1ce 100644 --- a/arch/arm/crypto/aes-ce-glue.c +++ b/arch/arm/crypto/aes-ce-glue.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -425,9 +426,6 @@ static int __init aes_init(void) int err; int i; - if (!(elf_hwcap2 & HWCAP2_AES)) - return -ENODEV; - err = crypto_register_skciphers(aes_algs, ARRAY_SIZE(aes_algs)); if (err) return err; @@ -451,5 +449,5 @@ unregister_simds: return err; } -module_init(aes_init); +module_cpu_feature_match(AES, aes_init); module_exit(aes_exit); -- cgit v1.2.3 From c9d9f608b4339435ccec6bd2ec1a5c42e066788e Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Sun, 21 May 2017 10:23:37 +0000 Subject: crypto: arm/ghash-ce - enable module autoloading based on CPU feature bits Make the module autoloadable by tying it to the CPU feature bit that describes whether the optional instructions it relies on are implemented by the current CPU. Signed-off-by: Ard Biesheuvel Signed-off-by: Herbert Xu --- arch/arm/crypto/ghash-ce-glue.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/crypto/ghash-ce-glue.c b/arch/arm/crypto/ghash-ce-glue.c index 7546b3c02466..6bac8bea9f1e 100644 --- a/arch/arm/crypto/ghash-ce-glue.c +++ b/arch/arm/crypto/ghash-ce-glue.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -311,9 +312,6 @@ static int __init ghash_ce_mod_init(void) { int err; - if (!(elf_hwcap2 & HWCAP2_PMULL)) - return -ENODEV; - err = crypto_register_shash(&ghash_alg); if (err) return err; @@ -334,5 +332,5 @@ static void __exit ghash_ce_mod_exit(void) crypto_unregister_shash(&ghash_alg); } -module_init(ghash_ce_mod_init); +module_cpu_feature_match(PMULL, ghash_ce_mod_init); module_exit(ghash_ce_mod_exit); -- cgit v1.2.3 From bd56f95ea933d1dd1628373a8213716225605d1c Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Sun, 21 May 2017 10:23:38 +0000 Subject: crypto: arm/sha1-ce - enable module autoloading based on CPU feature bits Make the module autoloadable by tying it to the CPU feature bit that describes whether the optional instructions it relies on are implemented by the current CPU. Signed-off-by: Ard Biesheuvel Signed-off-by: Herbert Xu --- arch/arm/crypto/sha1-ce-glue.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/crypto/sha1-ce-glue.c b/arch/arm/crypto/sha1-ce-glue.c index 80bc2fcd241a..555f72b5e659 100644 --- a/arch/arm/crypto/sha1-ce-glue.c +++ b/arch/arm/crypto/sha1-ce-glue.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -82,8 +83,6 @@ static struct shash_alg alg = { static int __init sha1_ce_mod_init(void) { - if (!(elf_hwcap2 & HWCAP2_SHA1)) - return -ENODEV; return crypto_register_shash(&alg); } @@ -92,5 +91,5 @@ static void __exit sha1_ce_mod_fini(void) crypto_unregister_shash(&alg); } -module_init(sha1_ce_mod_init); +module_cpu_feature_match(SHA1, sha1_ce_mod_init); module_exit(sha1_ce_mod_fini); -- cgit v1.2.3 From a83ff88bedb2794f5990439276bf0abbc4b3aeb8 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Sun, 21 May 2017 10:23:39 +0000 Subject: crypto: arm/sha2-ce - enable module autoloading based on CPU feature bits Make the module autoloadable by tying it to the CPU feature bit that describes whether the optional instructions it relies on are implemented by the current CPU. Signed-off-by: Ard Biesheuvel Signed-off-by: Herbert Xu --- arch/arm/crypto/sha2-ce-glue.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/crypto/sha2-ce-glue.c b/arch/arm/crypto/sha2-ce-glue.c index 0755b2d657f3..df4dcef054ae 100644 --- a/arch/arm/crypto/sha2-ce-glue.c +++ b/arch/arm/crypto/sha2-ce-glue.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -100,8 +101,6 @@ static struct shash_alg algs[] = { { static int __init sha2_ce_mod_init(void) { - if (!(elf_hwcap2 & HWCAP2_SHA2)) - return -ENODEV; return crypto_register_shashes(algs, ARRAY_SIZE(algs)); } @@ -110,5 +109,5 @@ static void __exit sha2_ce_mod_fini(void) crypto_unregister_shashes(algs, ARRAY_SIZE(algs)); } -module_init(sha2_ce_mod_init); +module_cpu_feature_match(SHA2, sha2_ce_mod_init); module_exit(sha2_ce_mod_fini); -- cgit v1.2.3 From 2a9faf8b7e4350967ed7b59e39522972b9ead0c9 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Sun, 21 May 2017 10:23:40 +0000 Subject: crypto: arm/crc32 - enable module autoloading based on CPU feature bits Make the module autoloadable by tying it to the CPU feature bits that describe whether the optional instructions it relies on are implemented by the current CPU. Signed-off-by: Ard Biesheuvel Signed-off-by: Herbert Xu --- arch/arm/crypto/crc32-ce-glue.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/crypto/crc32-ce-glue.c b/arch/arm/crypto/crc32-ce-glue.c index e1566bec1016..1b0e0e86ee9c 100644 --- a/arch/arm/crypto/crc32-ce-glue.c +++ b/arch/arm/crypto/crc32-ce-glue.c @@ -8,6 +8,7 @@ * published by the Free Software Foundation. */ +#include #include #include #include @@ -233,6 +234,11 @@ static void __exit crc32_pmull_mod_exit(void) ARRAY_SIZE(crc32_pmull_algs)); } +static const struct cpu_feature crc32_cpu_feature[] = { + { cpu_feature(CRC32) }, { cpu_feature(PMULL) }, { } +}; +MODULE_DEVICE_TABLE(cpu, crc32_cpu_feature); + module_init(crc32_pmull_mod_init); module_exit(crc32_pmull_mod_exit); -- cgit v1.2.3 From 23c0c210a1adcfca27a52808d1a0cbd807e86518 Mon Sep 17 00:00:00 2001 From: Randy Li Date: Tue, 30 May 2017 23:52:46 +0800 Subject: ARM: dts: rockchip: add adc button for Firefly The only adc button connected to adc input is recovery button. Signed-off-by: Randy Li Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-firefly-reload.dts | 17 +++++++++++++++++ arch/arm/boot/dts/rk3288-firefly.dtsi | 13 +++++++++++++ 2 files changed, 30 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts index d0b3204a4799..b11a282c334c 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload.dts +++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts @@ -48,6 +48,19 @@ model = "Firefly-RK3288-reload"; compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288"; + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + gpio-keys { compatible = "gpio-keys"; @@ -246,6 +259,10 @@ status = "okay"; }; +&saradc { + status = "okay"; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index 864747342e3e..32dabae12e67 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -49,6 +49,19 @@ reg = <0 0x80000000>; }; + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + dovdd_1v8: dovdd-1v8-regulator { compatible = "regulator-fixed"; regulator-name = "dovdd_1v8"; -- cgit v1.2.3 From f46b563f2f270e451b2e1cee78573508cc1de256 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 24 May 2017 11:07:48 +0200 Subject: ARM: dts: augment Moxa and Aspeed DTS for FTTMR010 This augments the Moxa Art and Aspeed device trees to: - Explicitly name the clock "PCLK" as the Faraday FTTMR010 names it. - List the Moxa timer as compatible with the Faradat FTTMR010 vanilla version. - Add a comment that the Aspeed driver is a Faraday FTTMR010 derivative. - Pass all IRQs to the timer from Aspeed: they are all there so they should be in the device tree, we only use the first one anyways. Tested-by: Joel Stanley Tested-by: Jonas Jensen Signed-off-by: Linus Walleij Signed-off-by: Olof Johansson --- arch/arm/boot/dts/aspeed-g4.dtsi | 7 +++---- arch/arm/boot/dts/aspeed-g5.dtsi | 7 +++---- arch/arm/boot/dts/moxart.dtsi | 3 ++- 3 files changed, 8 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 8c6bc29eb7f6..8a04c7e2d818 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -886,13 +886,12 @@ }; timer: timer@1e782000 { + /* This timer is a Faraday FTTMR010 derivative */ compatible = "aspeed,ast2400-timer"; reg = <0x1e782000 0x90>; - // The moxart_timer driver registers only one - // interrupt and assumes it's for timer 1 - //interrupts = <16 17 18 35 36 37 38 39>; - interrupts = <16>; + interrupts = <16 17 18 35 36 37 38 39>; clocks = <&clk_apb>; + clock-names = "PCLK"; }; wdt1: wdt@1e785000 { diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index a0bea4a6ec77..9cffe347b828 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -993,13 +993,12 @@ }; timer: timer@1e782000 { + /* This timer is a Faraday FTTMR010 derivative */ compatible = "aspeed,ast2400-timer"; reg = <0x1e782000 0x90>; - // The moxart_timer driver registers only one - // interrupt and assumes it's for timer 1 - //interrupts = <16 17 18 35 36 37 38 39>; - interrupts = <16>; + interrupts = <16 17 18 35 36 37 38 39>; clocks = <&clk_apb>; + clock-names = "PCLK"; }; diff --git a/arch/arm/boot/dts/moxart.dtsi b/arch/arm/boot/dts/moxart.dtsi index e86f8c905ac5..1f4c795d3f72 100644 --- a/arch/arm/boot/dts/moxart.dtsi +++ b/arch/arm/boot/dts/moxart.dtsi @@ -58,10 +58,11 @@ }; timer: timer@98400000 { - compatible = "moxa,moxart-timer"; + compatible = "moxa,moxart-timer", "faraday,fttmr010"; reg = <0x98400000 0x42>; interrupts = <19 IRQ_TYPE_EDGE_FALLING>; clocks = <&clk_apb>; + clock-names = "PCLK"; }; gpio: gpio@98700000 { -- cgit v1.2.3 From 2d4c44e979eaa846dfa63717c4f4818e11161c66 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Szemz=C5=91=20Andr=C3=A1s?= Date: Wed, 31 May 2017 03:06:21 +0200 Subject: ARM: at91: Add armv7m support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Atmel SAME70/SAMS70/SAMV71 SoC support. Signed-off-by: Szemző András Acked-by: Nicolas Ferre Signed-off-by: Alexandre Belloni --- arch/arm/mach-at91/Kconfig | 10 +++++++++- arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/Makefile.boot | 3 +++ arch/arm/mach-at91/samv7.c | 25 +++++++++++++++++++++++++ 4 files changed, 38 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-at91/Makefile.boot create mode 100644 arch/arm/mach-at91/samv7.c (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 841e924143f9..2594b6a412f0 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -1,12 +1,20 @@ menuconfig ARCH_AT91 bool "Atmel SoCs" - depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V7 + depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M select COMMON_CLK_AT91 select GPIOLIB select PINCTRL select SOC_BUS if ARCH_AT91 +config SOC_SAMV7 + bool "SAM Cortex-M7 family" if ARM_SINGLE_ARMV7M + select COMMON_CLK_AT91 + select PINCTRL_AT91 + help + Select this if you are using an SoC from Atmel's SAME7, SAMS7 or SAMV7 + families. + config SOC_SAMA5D2 bool "SAMA5D2 family" depends on ARCH_MULTI_V7 diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index cfd8f60a9268..a189081dccc0 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o obj-$(CONFIG_SOC_SAMA5) += sama5.o +obj-$(CONFIG_SOC_SAMV7) += samv7.o # Power Management obj-$(CONFIG_PM) += pm.o diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot new file mode 100644 index 000000000000..eacfc3f5c33e --- /dev/null +++ b/arch/arm/mach-at91/Makefile.boot @@ -0,0 +1,3 @@ +# Empty file waiting for deletion once Makefile.boot isn't needed any more. +# Patch waits for application at +# http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 . diff --git a/arch/arm/mach-at91/samv7.c b/arch/arm/mach-at91/samv7.c new file mode 100644 index 000000000000..11386f190c83 --- /dev/null +++ b/arch/arm/mach-at91/samv7.c @@ -0,0 +1,25 @@ +/* + * Setup code for SAMv7x + * + * Copyright (C) 2013 Atmel, + * 2016 Andras Szemzo + * + * Licensed under GPLv2 or later. + */ +#include +#include +#include +#include +#include +#include +#include +#include "generic.h" + +static const char *const samv7_dt_board_compat[] __initconst = { + "atmel,samv7", + NULL +}; + +DT_MACHINE_START(samv7_dt, "Atmel SAMV7") + .dt_compat = samv7_dt_board_compat, +MACHINE_END -- cgit v1.2.3 From b2f06274337074a64ad42550f336b9f279eb835a Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 31 May 2017 03:06:22 +0200 Subject: ARM: at91: handle CONFIG_PM for armv7m configurations There is currently no PM support for samx7 but the symbol can still be selected. This avoids compilation issues. Acked-by: Nicolas Ferre Signed-off-by: Alexandre Belloni --- arch/arm/mach-at91/Kconfig | 6 ++++++ arch/arm/mach-at91/Makefile | 3 +-- arch/arm/mach-at91/samv7.c | 9 +++++++++ 3 files changed, 16 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 2594b6a412f0..7497a28a79d1 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -60,6 +60,7 @@ config SOC_AT91RM9200 bool "AT91RM9200" depends on ARCH_MULTI_V4T select ATMEL_AIC_IRQ + select ATMEL_PM if PM select ATMEL_ST select CPU_ARM920T select HAVE_AT91_USB_CLK @@ -73,6 +74,7 @@ config SOC_AT91SAM9 bool "AT91SAM9" depends on ARCH_MULTI_V5 select ATMEL_AIC_IRQ + select ATMEL_PM if PM select ATMEL_SDRAMC select CPU_ARM926T select HAVE_AT91_SMD @@ -131,9 +133,13 @@ config SOC_SAM_V7 config SOC_SAMA5 bool select ATMEL_AIC5_IRQ + select ATMEL_PM if PM select ATMEL_SDRAMC select MEMORY select SOC_SAM_V7 select SRAM if PM +config ATMEL_PM + bool + endif diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index a189081dccc0..ee34aa34cc51 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -9,8 +9,7 @@ obj-$(CONFIG_SOC_SAMA5) += sama5.o obj-$(CONFIG_SOC_SAMV7) += samv7.o # Power Management -obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_PM) += pm_suspend.o +obj-$(CONFIG_ATMEL_PM) += pm.o pm_suspend.o ifeq ($(CONFIG_CPU_V7),y) AFLAGS_pm_suspend.o := -march=armv7-a diff --git a/arch/arm/mach-at91/samv7.c b/arch/arm/mach-at91/samv7.c index 11386f190c83..910f0c68db62 100644 --- a/arch/arm/mach-at91/samv7.c +++ b/arch/arm/mach-at91/samv7.c @@ -15,6 +15,15 @@ #include #include "generic.h" +#ifdef CONFIG_PM +/* This function has to be defined for various drivers that are using it */ +int at91_suspend_entering_slow_clock(void) +{ + return 0; +} +EXPORT_SYMBOL(at91_suspend_entering_slow_clock); +#endif + static const char *const samv7_dt_board_compat[] __initconst = { "atmel,samv7", NULL -- cgit v1.2.3 From 63e07c0fdc41d7d585dad72ed01856c68ce52bbe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Szemz=C5=91=20Andr=C3=A1s?= Date: Wed, 31 May 2017 03:06:24 +0200 Subject: ARM: at91: debug: add samv7x support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for low level debugging on Atmel samv7x. Signed-off-by: Szemző András Acked-by: Nicolas Ferre Signed-off-by: Alexandre Belloni --- arch/arm/Kconfig.debug | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 426d2716f55d..e10fb1842b1d 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -145,6 +145,15 @@ choice Say Y here if you want kernel low-level debugging support on the USART3 port of sama5d4. + config DEBUG_AT91_SAMV7_USART1 + bool "Kernel low-level debugging via SAMV7 USART1" + select DEBUG_AT91_UART + depends on SOC_SAMV7 + help + Say Y here if you want the debug print routines to direct + their output to the USART1 port on SAMV7 based + machines. + config DEBUG_BCM2835 bool "Kernel low-level debugging on BCM2835 PL011 UART" depends on ARCH_BCM2835 && ARCH_MULTI_V6 @@ -1481,6 +1490,7 @@ config DEBUG_UART_PHYS default 0x3f201000 if DEBUG_BCM2836 default 0x3e000000 if DEBUG_BCM_KONA_UART default 0x4000e400 if DEBUG_LL_UART_EFM32 + default 0x40028000 if DEBUG_AT91_SAMV7_USART1 default 0x40081000 if DEBUG_LPC18XX_UART0 default 0x40090000 if DEBUG_LPC32XX default 0x40100000 if DEBUG_PXA_UART1 -- cgit v1.2.3 From 3880af4541a178b38cce0456c9afa3ab96534e90 Mon Sep 17 00:00:00 2001 From: William Wu Date: Fri, 2 Jun 2017 15:04:24 +0800 Subject: ARM: dts: rockchip: add usb nodes on rk322x This patch adds usb otg/host controllers and phys nodes on rk322x. Signed-off-by: William Wu Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 138 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 137 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index df574135797a..f3e4ffd9f818 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -210,8 +210,61 @@ }; grf: syscon@11000000 { - compatible = "syscon"; + compatible = "syscon", "simple-mfd"; reg = <0x11000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy0: usb2-phy@760 { + compatible = "rockchip,rk3228-usb2phy"; + reg = <0x0760 0x0c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + #clock-cells = <0>; + status = "disabled"; + + u2phy0_otg: otg-port { + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy0_host: host-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + u2phy1: usb2-phy@800 { + compatible = "rockchip,rk3228-usb2phy"; + reg = <0x0800 0x0c>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; + #clock-cells = <0>; + status = "disabled"; + + u2phy1_otg: otg-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy1_host: host-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; }; uart0: serial@11010000 { @@ -467,6 +520,89 @@ status = "disabled"; }; + usb_otg: usb@30040000 { + compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x30040000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + g-use-dma; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host0_ehci: usb@30080000 { + compatible = "generic-ehci"; + reg = <0x30080000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&u2phy0>; + clock-names = "usbhost", "utmi"; + phys = <&u2phy0_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host0_ohci: usb@300a0000 { + compatible = "generic-ohci"; + reg = <0x300a0000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&u2phy0>; + clock-names = "usbhost", "utmi"; + phys = <&u2phy0_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ehci: usb@300c0000 { + compatible = "generic-ehci"; + reg = <0x300c0000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&u2phy1>; + clock-names = "usbhost", "utmi"; + phys = <&u2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ohci: usb@300e0000 { + compatible = "generic-ohci"; + reg = <0x300e0000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&u2phy1>; + clock-names = "usbhost", "utmi"; + phys = <&u2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host2_ehci: usb@30100000 { + compatible = "generic-ehci"; + reg = <0x30100000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST2>, <&u2phy1>; + phys = <&u2phy1_host>; + phy-names = "usb"; + clock-names = "usbhost", "utmi"; + status = "disabled"; + }; + + usb_host2_ohci: usb@30120000 { + compatible = "generic-ohci"; + reg = <0x30120000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST2>, <&u2phy1>; + clock-names = "usbhost", "utmi"; + phys = <&u2phy1_host>; + phy-names = "usb"; + status = "disabled"; + }; + gmac: ethernet@30200000 { compatible = "rockchip,rk3228-gmac"; reg = <0x30200000 0x10000>; -- cgit v1.2.3 From 81b61d37705173b8b9eb52c4566a8fc7c7099520 Mon Sep 17 00:00:00 2001 From: William Wu Date: Fri, 2 Jun 2017 15:04:25 +0800 Subject: ARM: dts: rockchip: enable usb for rk3229 evb board Rockchip's rk3229 evaluation board has one usb otg controller and three usb host controllers. Each usb controller connect with one usb2 phy port through UTMI+ interface. And the three usb host interfaces use the same GPIO VBUS drive. Let's enable them to support usb on rk3229 evb board. Signed-off-by: William Wu Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3229-evb.dts | 74 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts index 275092a950ef..1b55192b7d04 100644 --- a/arch/arm/boot/dts/rk3229-evb.dts +++ b/arch/arm/boot/dts/rk3229-evb.dts @@ -58,6 +58,17 @@ #clock-cells = <0>; }; + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + regulator-boot-on; + }; + vcc_phy: vcc-phy-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -85,6 +96,69 @@ status = "okay"; }; +&pinctrl { + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + &uart2 { status = "okay"; }; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host2_ehci { + status = "okay"; +}; + +&usb_host2_ohci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; -- cgit v1.2.3 From 5343b1579247875ccfa88778e8db17e181c9f3fe Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 31 May 2017 13:00:17 +0200 Subject: ARM: dts: exynos: Add HDMI CEC device to Exynos5 SoC family Exynos5250 and Exynos542x SoCs have the same CEC hardware module as Exynos4 SoC series, so enable support for it using the same compatible string. Tested on Odroid XU3 (Exynos5422) and Google Snow (Exynos5250) boards. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 7 +++++++ arch/arm/boot/dts/exynos5250-snow-common.dtsi | 4 ++++ arch/arm/boot/dts/exynos5250.dtsi | 13 +++++++++++++ arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 7 +++++++ arch/arm/boot/dts/exynos5420.dtsi | 13 +++++++++++++ arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ 6 files changed, 48 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi index 2f6ab32b5954..1fd122db18e6 100644 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi @@ -589,6 +589,13 @@ samsung,pin-pud = ; samsung,pin-drv = ; }; + + hdmi_cec: hdmi-cec { + samsung,pins = "gpx3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; }; &pinctrl_1 { diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi index 8f3a80430748..e1d293dbbe5d 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi @@ -272,6 +272,10 @@ vdd_pll-supply = <&ldo8_reg>; }; +&hdmicec { + status = "okay"; +}; + &i2c_0 { status = "okay"; samsung,i2c-sda-delay = <100>; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 79c9c885613a..fbdc1d53a2ce 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -689,6 +689,19 @@ samsung,syscon-phandle = <&pmu_system_controller>; }; + hdmicec: cec@101B0000 { + compatible = "samsung,s5p-cec"; + reg = <0x101B0000 0x200>; + interrupts = ; + clocks = <&clock CLK_HDMI_CEC>; + clock-names = "hdmicec"; + samsung,syscon-phandle = <&pmu_system_controller>; + hdmi-phandle = <&hdmi>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "disabled"; + }; + mixer@14450000 { compatible = "samsung,exynos5250-mixer"; reg = <0x14450000 0x10000>; diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index 3924b4fafe72..65aa0e300c23 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -67,6 +67,13 @@ samsung,pin-pud = ; samsung,pin-drv = ; }; + + hdmi_cec: hdmi-cec { + samsung,pins = "gpx3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; }; &pinctrl_1 { diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 0db0bcf8da36..acd77b10b3df 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -624,6 +624,19 @@ reg = <0x145D0000 0x20>; }; + hdmicec: cec@101B0000 { + compatible = "samsung,s5p-cec"; + reg = <0x101B0000 0x200>; + interrupts = ; + clocks = <&clock CLK_HDMI_CEC>; + clock-names = "hdmicec"; + samsung,syscon-phandle = <&pmu_system_controller>; + hdmi-phandle = <&hdmi>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "disabled"; + }; + mixer: mixer@14450000 { compatible = "samsung,exynos5420-mixer"; reg = <0x14450000 0x10000>; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 657535e2e3cc..f92f95741207 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -264,6 +264,10 @@ vdd-supply = <&ldo6_reg>; }; +&hdmicec { + status = "okay"; +}; + &hsi2c_4 { status = "okay"; -- cgit v1.2.3 From c80aec5e0596858f8e8b26fb4844969ea5eb66e7 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 31 May 2017 15:58:20 +0800 Subject: ARM: sun8i: a83t: Add device node for PRCM The A83T's PRCM has the same set of clocks and resets as the A64. However, a few dividers are different. And due to the lack of a low speed 32.768 kHz oscillator, a few of the clock parents are different. The PRCM also has controls for various power domains. These are not supported yet, neither in software nor in the device tree binding. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 1dc4cfe81534..49aeb56970ba 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -270,5 +270,15 @@ #interrupt-cells = <3>; interrupts = ; }; + + r_ccu: clock@1f01400 { + compatible = "allwinner,sun8i-a83t-r-ccu"; + reg = <0x01f01400 0x400>; + clocks = <&osc24M>, <&osc16Md512>, <&osc16M>, + <&ccu 6>; + clock-names = "hosc", "losc", "iosc", "pll-periph"; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; }; -- cgit v1.2.3 From 95adb4e59263d3056d75eb385e79f9e037b5b7bc Mon Sep 17 00:00:00 2001 From: Juri Lelli Date: Wed, 31 May 2017 17:59:26 +0100 Subject: arm: fix return value of parse_cpu_capacity parse_cpu_capacity() has to return 0 on failure, but it currently returns 1 instead if raw_capacity kcalloc failed. Fix it (by directly returning 0). Reported-by: Morten Rasmussen Fixes: 06073ee26775 ('ARM: 8621/3: parse cpu capacity-dmips-mhz from DT') Signed-off-by: Juri Lelli Acked-by: Russell King Acked-by: Vincent Guittot Signed-off-by: Greg Kroah-Hartman --- arch/arm/kernel/topology.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c index f8a3ab82e77f..1b8ec3054642 100644 --- a/arch/arm/kernel/topology.c +++ b/arch/arm/kernel/topology.c @@ -166,7 +166,7 @@ static int __init parse_cpu_capacity(struct device_node *cpu_node, int cpu) if (!raw_capacity) { pr_err("cpu_capacity: failed to allocate memory for raw capacities\n"); cap_parsing_failed = true; - return !ret; + return 0; } } capacity_scale = max(cpu_capacity, capacity_scale); -- cgit v1.2.3 From f70b281b59a871545362a494d99a644153fbbaac Mon Sep 17 00:00:00 2001 From: Juri Lelli Date: Wed, 31 May 2017 17:59:27 +0100 Subject: arm: remove wrong CONFIG_PROC_SYSCTL ifdef The sysfs cpu_capacity entry for each CPU has nothing to do with PROC_FS, nor it's in /proc/sys path. Remove such ifdef. Cc: Russell King Reported-and-suggested-by: Sudeep Holla Fixes: 7e5930aaef5d ('ARM: 8622/3: add sysfs cpu_capacity attribute') Signed-off-by: Juri Lelli Acked-by: Russell King Signed-off-by: Greg Kroah-Hartman --- arch/arm/kernel/topology.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c index 1b8ec3054642..40dd35aa46d0 100644 --- a/arch/arm/kernel/topology.c +++ b/arch/arm/kernel/topology.c @@ -57,7 +57,6 @@ static void set_capacity_scale(unsigned int cpu, unsigned long capacity) per_cpu(cpu_scale, cpu) = capacity; } -#ifdef CONFIG_PROC_SYSCTL static ssize_t cpu_capacity_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -114,7 +113,6 @@ static int register_cpu_capacity_sysctl(void) return 0; } subsys_initcall(register_cpu_capacity_sysctl); -#endif #ifdef CONFIG_OF struct cpu_efficiency { -- cgit v1.2.3 From 2ef7a2953c81ee6b341e3ffb33570adc894cf4a5 Mon Sep 17 00:00:00 2001 From: Juri Lelli Date: Wed, 31 May 2017 17:59:28 +0100 Subject: arm, arm64: factorize common cpu capacity default code arm and arm64 share lot of code relative to parsing CPU capacity information from DT, using that information for appropriate scaling and exposing a sysfs interface for chaging such values at runtime. Factorize such code in a common place (driver/base/arch_topology.c) in preparation for further additions. Suggested-by: Will Deacon Suggested-by: Mark Rutland Suggested-by: Catalin Marinas Cc: Russell King Cc: Catalin Marinas Cc: Will Deacon Cc: Greg Kroah-Hartman Signed-off-by: Juri Lelli Acked-by: Russell King Acked-by: Catalin Marinas Acked-by: Greg Kroah-Hartman Signed-off-by: Greg Kroah-Hartman --- arch/arm/Kconfig | 1 + arch/arm/kernel/topology.c | 213 ++------------------------------------------- 2 files changed, 7 insertions(+), 207 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4c1a35f15838..7ef16700cb88 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -25,6 +25,7 @@ config ARM select EDAC_SUPPORT select EDAC_ATOMIC_SCRUB select GENERIC_ALLOCATOR + select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) select GENERIC_CLOCKEVENTS_BROADCAST if SMP select GENERIC_CPU_AUTOPROBE diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c index 40dd35aa46d0..49ef025ffaa0 100644 --- a/arch/arm/kernel/topology.c +++ b/arch/arm/kernel/topology.c @@ -44,75 +44,10 @@ * to run the rebalance_domains for all idle cores and the cpu_capacity can be * updated during this sequence. */ -static DEFINE_PER_CPU(unsigned long, cpu_scale) = SCHED_CAPACITY_SCALE; -static DEFINE_MUTEX(cpu_scale_mutex); -unsigned long arch_scale_cpu_capacity(struct sched_domain *sd, int cpu) -{ - return per_cpu(cpu_scale, cpu); -} - -static void set_capacity_scale(unsigned int cpu, unsigned long capacity) -{ - per_cpu(cpu_scale, cpu) = capacity; -} - -static ssize_t cpu_capacity_show(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct cpu *cpu = container_of(dev, struct cpu, dev); - - return sprintf(buf, "%lu\n", - arch_scale_cpu_capacity(NULL, cpu->dev.id)); -} - -static ssize_t cpu_capacity_store(struct device *dev, - struct device_attribute *attr, - const char *buf, - size_t count) -{ - struct cpu *cpu = container_of(dev, struct cpu, dev); - int this_cpu = cpu->dev.id, i; - unsigned long new_capacity; - ssize_t ret; - - if (count) { - ret = kstrtoul(buf, 0, &new_capacity); - if (ret) - return ret; - if (new_capacity > SCHED_CAPACITY_SCALE) - return -EINVAL; - - mutex_lock(&cpu_scale_mutex); - for_each_cpu(i, &cpu_topology[this_cpu].core_sibling) - set_capacity_scale(i, new_capacity); - mutex_unlock(&cpu_scale_mutex); - } - - return count; -} - -static DEVICE_ATTR_RW(cpu_capacity); - -static int register_cpu_capacity_sysctl(void) -{ - int i; - struct device *cpu; - - for_each_possible_cpu(i) { - cpu = get_cpu_device(i); - if (!cpu) { - pr_err("%s: too early to get CPU%d device!\n", - __func__, i); - continue; - } - device_create_file(cpu, &dev_attr_cpu_capacity); - } - - return 0; -} -subsys_initcall(register_cpu_capacity_sysctl); +extern unsigned long +arch_scale_cpu_capacity(struct sched_domain *sd, int cpu); +extern void set_capacity_scale(unsigned int cpu, unsigned long capacity); #ifdef CONFIG_OF struct cpu_efficiency { @@ -141,145 +76,9 @@ static unsigned long *__cpu_capacity; static unsigned long middle_capacity = 1; static bool cap_from_dt = true; -static u32 *raw_capacity; -static bool cap_parsing_failed; -static u32 capacity_scale; - -static int __init parse_cpu_capacity(struct device_node *cpu_node, int cpu) -{ - int ret = 1; - u32 cpu_capacity; - - if (cap_parsing_failed) - return !ret; - - ret = of_property_read_u32(cpu_node, - "capacity-dmips-mhz", - &cpu_capacity); - if (!ret) { - if (!raw_capacity) { - raw_capacity = kcalloc(num_possible_cpus(), - sizeof(*raw_capacity), - GFP_KERNEL); - if (!raw_capacity) { - pr_err("cpu_capacity: failed to allocate memory for raw capacities\n"); - cap_parsing_failed = true; - return 0; - } - } - capacity_scale = max(cpu_capacity, capacity_scale); - raw_capacity[cpu] = cpu_capacity; - pr_debug("cpu_capacity: %s cpu_capacity=%u (raw)\n", - cpu_node->full_name, raw_capacity[cpu]); - } else { - if (raw_capacity) { - pr_err("cpu_capacity: missing %s raw capacity\n", - cpu_node->full_name); - pr_err("cpu_capacity: partial information: fallback to 1024 for all CPUs\n"); - } - cap_parsing_failed = true; - kfree(raw_capacity); - } - - return !ret; -} - -static void normalize_cpu_capacity(void) -{ - u64 capacity; - int cpu; - - if (!raw_capacity || cap_parsing_failed) - return; - - pr_debug("cpu_capacity: capacity_scale=%u\n", capacity_scale); - mutex_lock(&cpu_scale_mutex); - for_each_possible_cpu(cpu) { - capacity = (raw_capacity[cpu] << SCHED_CAPACITY_SHIFT) - / capacity_scale; - set_capacity_scale(cpu, capacity); - pr_debug("cpu_capacity: CPU%d cpu_capacity=%lu\n", - cpu, arch_scale_cpu_capacity(NULL, cpu)); - } - mutex_unlock(&cpu_scale_mutex); -} - -#ifdef CONFIG_CPU_FREQ -static cpumask_var_t cpus_to_visit; -static bool cap_parsing_done; -static void parsing_done_workfn(struct work_struct *work); -static DECLARE_WORK(parsing_done_work, parsing_done_workfn); - -static int -init_cpu_capacity_callback(struct notifier_block *nb, - unsigned long val, - void *data) -{ - struct cpufreq_policy *policy = data; - int cpu; - - if (cap_parsing_failed || cap_parsing_done) - return 0; - - switch (val) { - case CPUFREQ_NOTIFY: - pr_debug("cpu_capacity: init cpu capacity for CPUs [%*pbl] (to_visit=%*pbl)\n", - cpumask_pr_args(policy->related_cpus), - cpumask_pr_args(cpus_to_visit)); - cpumask_andnot(cpus_to_visit, - cpus_to_visit, - policy->related_cpus); - for_each_cpu(cpu, policy->related_cpus) { - raw_capacity[cpu] = arch_scale_cpu_capacity(NULL, cpu) * - policy->cpuinfo.max_freq / 1000UL; - capacity_scale = max(raw_capacity[cpu], capacity_scale); - } - if (cpumask_empty(cpus_to_visit)) { - normalize_cpu_capacity(); - kfree(raw_capacity); - pr_debug("cpu_capacity: parsing done\n"); - cap_parsing_done = true; - schedule_work(&parsing_done_work); - } - } - return 0; -} - -static struct notifier_block init_cpu_capacity_notifier = { - .notifier_call = init_cpu_capacity_callback, -}; - -static int __init register_cpufreq_notifier(void) -{ - if (cap_parsing_failed) - return -EINVAL; - - if (!alloc_cpumask_var(&cpus_to_visit, GFP_KERNEL)) { - pr_err("cpu_capacity: failed to allocate memory for cpus_to_visit\n"); - return -ENOMEM; - } - cpumask_copy(cpus_to_visit, cpu_possible_mask); - - return cpufreq_register_notifier(&init_cpu_capacity_notifier, - CPUFREQ_POLICY_NOTIFIER); -} -core_initcall(register_cpufreq_notifier); - -static void parsing_done_workfn(struct work_struct *work) -{ - cpufreq_unregister_notifier(&init_cpu_capacity_notifier, - CPUFREQ_POLICY_NOTIFIER); -} - -#else -static int __init free_raw_capacity(void) -{ - kfree(raw_capacity); - - return 0; -} -core_initcall(free_raw_capacity); -#endif +extern bool cap_parsing_failed; +extern void normalize_cpu_capacity(void); +extern int __init parse_cpu_capacity(struct device_node *cpu_node, int cpu); /* * Iterate all CPUs' descriptor in DT and compute the efficiency -- cgit v1.2.3 From c105aa31183a6ebec395681b6df47c8b65259322 Mon Sep 17 00:00:00 2001 From: Juri Lelli Date: Wed, 31 May 2017 17:59:29 +0100 Subject: arm,arm64,drivers: reduce scope of cap_parsing_failed Reduce the scope of cap_parsing_failed (making it static in drivers/base/arch_topology.c) by slightly changing {arm,arm64} DT parsing code. For arm checking for !cap_parsing_failed before calling normalize_ cpu_capacity() is superfluous, as returning an error from parse_ cpu_capacity() (above) means cap_from _dt is set to false. For arm64 we can simply check if raw_capacity points to something, which is not if capacity parsing has failed. Suggested-by: Morten Rasmussen Signed-off-by: Juri Lelli Acked-by: Russell King Acked-by: Catalin Marinas Acked-by: Greg Kroah-Hartman Signed-off-by: Greg Kroah-Hartman --- arch/arm/kernel/topology.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c index 49ef025ffaa0..1e35a3265ddf 100644 --- a/arch/arm/kernel/topology.c +++ b/arch/arm/kernel/topology.c @@ -76,7 +76,6 @@ static unsigned long *__cpu_capacity; static unsigned long middle_capacity = 1; static bool cap_from_dt = true; -extern bool cap_parsing_failed; extern void normalize_cpu_capacity(void); extern int __init parse_cpu_capacity(struct device_node *cpu_node, int cpu); @@ -165,7 +164,7 @@ static void __init parse_dt_topology(void) middle_capacity = ((max_capacity / 3) >> (SCHED_CAPACITY_SHIFT-1)) + 1; - if (cap_from_dt && !cap_parsing_failed) + if (cap_from_dt) normalize_cpu_capacity(); } -- cgit v1.2.3 From 615ffd63149117aa5693d6672944966b490cdb66 Mon Sep 17 00:00:00 2001 From: Juri Lelli Date: Wed, 31 May 2017 17:59:30 +0100 Subject: arm,arm64,drivers: move externs in a new header file Create a new header file (include/linux/arch_topology.h) and put there declarations of interfaces used by arm, arm64 and drivers code. Signed-off-by: Juri Lelli Acked-by: Russell King Acked-by: Catalin Marinas Acked-by: Greg Kroah-Hartman Signed-off-by: Greg Kroah-Hartman --- arch/arm/kernel/topology.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c index 1e35a3265ddf..557be4f1d2d7 100644 --- a/arch/arm/kernel/topology.c +++ b/arch/arm/kernel/topology.c @@ -11,6 +11,7 @@ * for more details. */ +#include #include #include #include @@ -45,10 +46,6 @@ * updated during this sequence. */ -extern unsigned long -arch_scale_cpu_capacity(struct sched_domain *sd, int cpu); -extern void set_capacity_scale(unsigned int cpu, unsigned long capacity); - #ifdef CONFIG_OF struct cpu_efficiency { const char *compatible; @@ -76,8 +73,6 @@ static unsigned long *__cpu_capacity; static unsigned long middle_capacity = 1; static bool cap_from_dt = true; -extern void normalize_cpu_capacity(void); -extern int __init parse_cpu_capacity(struct device_node *cpu_node, int cpu); /* * Iterate all CPUs' descriptor in DT and compute the efficiency -- cgit v1.2.3 From 4ca4f26a9c66103ca158689b7554f07f4968a32c Mon Sep 17 00:00:00 2001 From: Juri Lelli Date: Wed, 31 May 2017 17:59:31 +0100 Subject: arm,arm64,drivers: add a prefix to drivers arch_topology interfaces Now that some functions that deal with arch topology information live under drivers, there is a clash of naming that might create confusion. Tidy things up by creating a topology namespace for interfaces used by arch code; achieve this by prepending a 'topology_' prefix to driver interfaces. Signed-off-by: Juri Lelli Acked-by: Russell King Acked-by: Catalin Marinas Signed-off-by: Greg Kroah-Hartman --- arch/arm/kernel/topology.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c index 557be4f1d2d7..bf949a763dbe 100644 --- a/arch/arm/kernel/topology.c +++ b/arch/arm/kernel/topology.c @@ -111,7 +111,7 @@ static void __init parse_dt_topology(void) continue; } - if (parse_cpu_capacity(cn, cpu)) { + if (topology_parse_cpu_capacity(cn, cpu)) { of_node_put(cn); continue; } @@ -160,7 +160,7 @@ static void __init parse_dt_topology(void) >> (SCHED_CAPACITY_SHIFT-1)) + 1; if (cap_from_dt) - normalize_cpu_capacity(); + topology_normalize_cpu_scale(); } /* @@ -173,10 +173,10 @@ static void update_cpu_capacity(unsigned int cpu) if (!cpu_capacity(cpu) || cap_from_dt) return; - set_capacity_scale(cpu, cpu_capacity(cpu) / middle_capacity); + topology_set_cpu_scale(cpu, cpu_capacity(cpu) / middle_capacity); pr_info("CPU%u: update cpu_capacity %lu\n", - cpu, arch_scale_cpu_capacity(NULL, cpu)); + cpu, topology_get_cpu_scale(NULL, cpu)); } #else -- cgit v1.2.3 From 7e9eb6268809cace1601bb4f0603412355cf9dde Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Fri, 26 May 2017 14:26:06 +0300 Subject: ARM: imx_v6_v7_defconfig: Explicitly restore CONFIG_DEBUG_FS This option was removed by "make savedefconfig" in commit c5054a98bce4 ("ARM: imx_v6_v7_defconfig: Select SMSC_PHY") This happened because CONFIG_DEBUG_FS was implicitly selected by CONFIG_TREE_RCU_TRACE which defaulted to true because CONFIG_RCU_TRACE was enabled by default by commit 961518259b3b ("rcu: Enable RCU tracepoints by default to aid in debugging") Recently however CONFIG_RCU_TRACE was completely removed by commit 6e74c237c410 ("rcu: Remove debugfs tracing") The result is that imx_v6_v7_defconfig no longer includes DEBUG_FS on linux-next since next-20170517. This is bad, DEBUG_FS is extremely useful for kernel introspection and testing. Signed-off-by: Leonard Crestez Signed-off-by: Shawn Guo --- arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index bf1e7e316918..51ca814f38fd 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -381,6 +381,7 @@ CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=m CONFIG_NLS_UTF8=y CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_FS=y CONFIG_MAGIC_SYSRQ=y # CONFIG_SCHED_DEBUG is not set CONFIG_PROVE_LOCKING=y -- cgit v1.2.3 From 37de44f238d37c96ab1fec8c88b6d207f5b85635 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 27 May 2017 10:17:52 -0300 Subject: ARM: dts: imx7: Fix typo in watchdog pin name Change "WDOD1" to "WDOG1" in watchdog pin names. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-nitrogen7.dts | 2 +- arch/arm/boot/dts/imx7d-pico.dts | 2 +- arch/arm/boot/dts/imx7d-pinfunc.h | 6 +++--- arch/arm/boot/dts/imx7d-sdb.dts | 2 +- arch/arm/boot/dts/imx7s-warp.dts | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index dd40e49f6c42..e7998308861f 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -738,7 +738,7 @@ pinctrl_wdog1: wdog1grp { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x75 + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x75 >; }; }; diff --git a/arch/arm/boot/dts/imx7d-pico.dts b/arch/arm/boot/dts/imx7d-pico.dts index 79b5d83aaace..e78c2c9cc28a 100644 --- a/arch/arm/boot/dts/imx7d-pico.dts +++ b/arch/arm/boot/dts/imx7d-pico.dts @@ -397,7 +397,7 @@ &iomuxc_lpsr { pinctrl_wdog: wdoggrp { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x74 + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 >; }; }; diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h index f6f7e78f8820..f2493bc63da4 100644 --- a/arch/arm/boot/dts/imx7d-pinfunc.h +++ b/arch/arm/boot/dts/imx7d-pinfunc.h @@ -17,9 +17,9 @@ #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0 diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 77c400f0017a..4a4b522d17d2 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -660,7 +660,7 @@ &iomuxc_lpsr { pinctrl_wdog: wdoggrp { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x74 + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 >; }; diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index 8dfed85471e1..07b63f8b7314 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -443,7 +443,7 @@ &iomuxc_lpsr { pinctrl_wdog: wdoggrp { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x74 + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 >; }; }; -- cgit v1.2.3 From 6bc51cbaa9d75c7c240282da5ff270815caccac0 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Sat, 3 Jun 2017 21:01:02 +0200 Subject: signal: Remove non-uapi By moving the kernel side __SI_* defintions right next to the userspace ones we can kill the non-uapi versions of include include/asm-generic/siginfo.h and untangle the unholy mess of includes. [ tglx: Removed uapi/asm/siginfo.h from m32r, microblaze, mn10300 and score ] Signed-off-by: Christoph Hellwig Signed-off-by: Thomas Gleixner Cc: linux-arch@vger.kernel.org Cc: Fenghua Yu Cc: Tony Luck Cc: linux-ia64@vger.kernel.org Cc: Arnd Bergmann Cc: sparclinux@vger.kernel.org Cc: "David S. Miller" Link: http://lkml.kernel.org/r/20170603190102.28866-6-hch@lst.de --- arch/arm/include/asm/Kbuild | 1 - arch/arm/include/uapi/asm/Kbuild | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild index 3a36d99ff836..d8360501c082 100644 --- a/arch/arm/include/asm/Kbuild +++ b/arch/arm/include/asm/Kbuild @@ -28,7 +28,6 @@ generic-y += segment.h generic-y += sembuf.h generic-y += serial.h generic-y += shmbuf.h -generic-y += siginfo.h generic-y += simd.h generic-y += sizes.h generic-y += socket.h diff --git a/arch/arm/include/uapi/asm/Kbuild b/arch/arm/include/uapi/asm/Kbuild index 607f702c2d62..e9b098d6b766 100644 --- a/arch/arm/include/uapi/asm/Kbuild +++ b/arch/arm/include/uapi/asm/Kbuild @@ -4,3 +4,5 @@ include include/uapi/asm-generic/Kbuild.asm genhdr-y += unistd-common.h genhdr-y += unistd-oabi.h genhdr-y += unistd-eabi.h + +generic-y += siginfo.h -- cgit v1.2.3 From 2387149eade25f32dcf1398811b3d0293181d005 Mon Sep 17 00:00:00 2001 From: Andrew Jones Date: Sun, 4 Jun 2017 14:43:51 +0200 Subject: KVM: improve arch vcpu request defining Marc Zyngier suggested that we define the arch specific VCPU request base, rather than requiring each arch to remember to start from 8. That suggestion, along with Radim Krcmar's recent VCPU request flag addition, snowballed into defining something of an arch VCPU request defining API. No functional change. (Looks like x86 is running out of arch VCPU request bits. Maybe someday we'll need to extend to 64.) Signed-off-by: Andrew Jones Acked-by: Christoffer Dall Signed-off-by: Christoffer Dall --- arch/arm/include/asm/kvm_host.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h index 12274d46df70..c556babe467c 100644 --- a/arch/arm/include/asm/kvm_host.h +++ b/arch/arm/include/asm/kvm_host.h @@ -44,7 +44,8 @@ #define KVM_MAX_VCPUS VGIC_V2_MAX_CPUS #endif -#define KVM_REQ_VCPU_EXIT (8 | KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) +#define KVM_REQ_VCPU_EXIT \ + KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode); int __attribute_const__ kvm_target_cpu(void); -- cgit v1.2.3 From 6a6d73be12fbe492d0678cd84d3b35e2bc9698e4 Mon Sep 17 00:00:00 2001 From: Andrew Jones Date: Sun, 4 Jun 2017 14:43:54 +0200 Subject: KVM: arm/arm64: properly use vcpu requests arm/arm64 already has one VCPU request used when setting pause, but it doesn't properly check requests in VCPU RUN. Check it and also make sure we set vcpu->mode at the appropriate time (before the check) and with the appropriate barriers. See Documentation/virtual/kvm/vcpu-requests.rst. Also make sure we don't leave any vcpu requests we don't intend to handle later set in the request bitmap. If we don't clear them, then kvm_request_pending() may return true when it shouldn't. Using VCPU requests properly fixes a small race where pause could get set just as a VCPU was entering guest mode. Signed-off-by: Andrew Jones Reviewed-by: Christoffer Dall Signed-off-by: Christoffer Dall --- arch/arm/kvm/handle_exit.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/kvm/handle_exit.c b/arch/arm/kvm/handle_exit.c index 5fd7968cdae9..a2b4f7b82356 100644 --- a/arch/arm/kvm/handle_exit.c +++ b/arch/arm/kvm/handle_exit.c @@ -72,6 +72,7 @@ static int kvm_handle_wfx(struct kvm_vcpu *vcpu, struct kvm_run *run) trace_kvm_wfx(*vcpu_pc(vcpu), false); vcpu->stat.wfi_exit_stat++; kvm_vcpu_block(vcpu); + kvm_clear_request(KVM_REQ_UNHALT, vcpu); } kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); -- cgit v1.2.3 From 7b244e2be654d90d77800015d23395357dbc82ba Mon Sep 17 00:00:00 2001 From: Andrew Jones Date: Sun, 4 Jun 2017 14:43:58 +0200 Subject: KVM: arm/arm64: change exit request to sleep request A request called EXIT is too generic. All requests are meant to cause exits, but different requests have different flags. Let's not make it difficult to decide if the EXIT request is correct for some case by just always providing unique requests for each case. This patch changes EXIT to SLEEP, because that's what the request is asking the VCPU to do. Signed-off-by: Andrew Jones Acked-by: Christoffer Dall Signed-off-by: Christoffer Dall --- arch/arm/include/asm/kvm_host.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h index c556babe467c..fdd644c01c89 100644 --- a/arch/arm/include/asm/kvm_host.h +++ b/arch/arm/include/asm/kvm_host.h @@ -44,7 +44,7 @@ #define KVM_MAX_VCPUS VGIC_V2_MAX_CPUS #endif -#define KVM_REQ_VCPU_EXIT \ +#define KVM_REQ_SLEEP \ KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode); -- cgit v1.2.3 From 325f9c649c8a4e447e4d3babacc7a60b75012d5d Mon Sep 17 00:00:00 2001 From: Andrew Jones Date: Sun, 4 Jun 2017 14:43:59 +0200 Subject: KVM: arm/arm64: use vcpu requests for irq injection Don't use request-less VCPU kicks when injecting IRQs, as a VCPU kick meant to trigger the interrupt injection could be sent while the VCPU is outside guest mode, which means no IPI is sent, and after it has called kvm_vgic_flush_hwstate(), meaning it won't see the updated GIC state until its next exit some time later for some other reason. The receiving VCPU only needs to check this request in VCPU RUN to handle it. By checking it, if it's pending, a memory barrier will be issued that ensures all state is visible. See "Ensuring Requests Are Seen" of Documentation/virtual/kvm/vcpu-requests.rst Signed-off-by: Andrew Jones Reviewed-by: Christoffer Dall Signed-off-by: Christoffer Dall --- arch/arm/include/asm/kvm_host.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h index fdd644c01c89..00ad56ee6455 100644 --- a/arch/arm/include/asm/kvm_host.h +++ b/arch/arm/include/asm/kvm_host.h @@ -46,6 +46,7 @@ #define KVM_REQ_SLEEP \ KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) +#define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode); int __attribute_const__ kvm_target_cpu(void); -- cgit v1.2.3 From 12de44f55dcd99f740c19fa514c181be5c686625 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 4 Jun 2017 14:31:15 -0300 Subject: ARM: dts: imx: Fix Ethernet PHY reset polarity The FEC driver ignores the GPIO polarity from 'phy-reset-gpios' and considers that the Ethernet PHY is active low, unless the property 'phy-reset-active-high' is present. Fix the device tree description by explicitly passing the 'GPIO_ACTIVE_LOW' flag to the 'phy-reset-gpios' property. Signed-off-by: Fabio Estevam Reviewed-by: Andrew Lunn Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-karo-tx25.dts | 2 +- arch/arm/boot/dts/imx25-pdk.dts | 2 +- arch/arm/boot/dts/imx25.dtsi | 1 + arch/arm/boot/dts/imx28-cfa10037.dts | 2 +- arch/arm/boot/dts/imx28-cfa10049.dts | 2 +- arch/arm/boot/dts/imx28-cfa10057.dts | 2 +- arch/arm/boot/dts/imx28-cfa10058.dts | 2 +- arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts | 2 +- arch/arm/boot/dts/imx28-evk.dts | 2 +- arch/arm/boot/dts/imx28-m28cu3.dts | 2 +- arch/arm/boot/dts/imx50-evk.dts | 2 +- arch/arm/boot/dts/imx50.dtsi | 1 + arch/arm/boot/dts/imx51-apf51.dts | 2 +- arch/arm/boot/dts/imx53-mba53.dts | 2 +- arch/arm/boot/dts/imx53-qsb-common.dtsi | 2 +- arch/arm/boot/dts/imx53-smd.dts | 2 +- arch/arm/boot/dts/imx53-tx53.dtsi | 2 +- arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi | 2 +- arch/arm/boot/dts/imx6dl-riotboard.dts | 2 +- arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 2 +- arch/arm/boot/dts/imx6q-evi.dts | 2 +- arch/arm/boot/dts/imx6q-gw5400-a.dts | 2 +- arch/arm/boot/dts/imx6q-novena.dts | 2 +- arch/arm/boot/dts/imx6qdl-aristainetos.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-tx6.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 2 +- arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts | 2 +- arch/arm/boot/dts/imx6ul-tx6ul.dtsi | 4 ++-- 32 files changed, 33 insertions(+), 31 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts index 9b31faa96377..30a62d4be8d9 100644 --- a/arch/arm/boot/dts/imx25-karo-tx25.dts +++ b/arch/arm/boot/dts/imx25-karo-tx25.dts @@ -97,7 +97,7 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; - phy-reset-gpios = <&gpio3 7 0>; + phy-reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; phy-mode = "rmii"; phy-supply = <®_fec_phy>; status = "okay"; diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index d921dd2ed676..c52692821fb1 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -125,7 +125,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; phy-supply = <®_fec_3v3>; - phy-reset-gpios = <&gpio4 8 0>; + phy-reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 0cdf333336cd..dfcc8e00cf1c 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -9,6 +9,7 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include #include "imx25-pinfunc.h" / { diff --git a/arch/arm/boot/dts/imx28-cfa10037.dts b/arch/arm/boot/dts/imx28-cfa10037.dts index e5beaa58bb40..3d13b321d27b 100644 --- a/arch/arm/boot/dts/imx28-cfa10037.dts +++ b/arch/arm/boot/dts/imx28-cfa10037.dts @@ -64,7 +64,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mac0_pins_a &mac0_pins_cfa10037>; - phy-reset-gpios = <&gpio2 21 0>; + phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; phy-reset-duration = <100>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index a9c347e48bcf..4cd52d53cf00 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -327,7 +327,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mac0_pins_a &mac0_pins_cfa10049>; - phy-reset-gpios = <&gpio2 21 0>; + phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; phy-reset-duration = <100>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts index 7a80bd686c40..c6067915b238 100644 --- a/arch/arm/boot/dts/imx28-cfa10057.dts +++ b/arch/arm/boot/dts/imx28-cfa10057.dts @@ -162,7 +162,7 @@ phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio2 21 0>; + phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; phy-reset-duration = <100>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts b/arch/arm/boot/dts/imx28-cfa10058.dts index f5c6dce34abe..70c7bb4a5a0e 100644 --- a/arch/arm/boot/dts/imx28-cfa10058.dts +++ b/arch/arm/boot/dts/imx28-cfa10058.dts @@ -129,7 +129,7 @@ phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio2 21 0>; + phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; phy-reset-duration = <100>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts b/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts index e773144e1e03..b61fd61eb1c7 100644 --- a/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts +++ b/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts @@ -31,7 +31,7 @@ phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&mac1_pins_a>; - phy-reset-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; + phy-reset-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index b88c087f1fea..5309bb90d7d5 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -262,7 +262,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mac0_pins_a>; phy-supply = <®_fec_3v3>; - phy-reset-gpios = <&gpio4 13 0>; + phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; phy-reset-duration = <100>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts index bb5329479c62..9d6c8fe28d74 100644 --- a/arch/arm/boot/dts/imx28-m28cu3.dts +++ b/arch/arm/boot/dts/imx28-m28cu3.dts @@ -188,7 +188,7 @@ phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio4 13 0>; + phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; phy-reset-duration = <100>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/imx50-evk.dts index dba2d951aa15..98b5faa06e27 100644 --- a/arch/arm/boot/dts/imx50-evk.dts +++ b/arch/arm/boot/dts/imx50-evk.dts @@ -53,7 +53,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; phy-mode = "rmii"; - phy-reset-gpios = <&gpio4 12 0>; + phy-reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 2a98afcd8a4e..3747d80104f4 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -12,6 +12,7 @@ */ #include "imx50-pinfunc.h" +#include #include / { diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts index e88b2a6be079..c83ac1600322 100644 --- a/arch/arm/boot/dts/imx51-apf51.dts +++ b/arch/arm/boot/dts/imx51-apf51.dts @@ -36,7 +36,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; phy-mode = "mii"; - phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; phy-reset-duration = <1>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts index 2e44d2aba14e..df705ba48897 100644 --- a/arch/arm/boot/dts/imx53-mba53.dts +++ b/arch/arm/boot/dts/imx53-mba53.dts @@ -195,7 +195,7 @@ }; &fec { - phy-reset-gpios = <&gpio7 6 0>; + phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi index 40b3e31935d0..683dcbe27cbd 100644 --- a/arch/arm/boot/dts/imx53-qsb-common.dtsi +++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi @@ -344,7 +344,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 6 0>; + phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index 472f6f0f55b3..33cb64fc8372 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts @@ -273,6 +273,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 6 0>; + phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi index 3a3220141988..7807c1fa1101 100644 --- a/arch/arm/boot/dts/imx53-tx53.dtsi +++ b/arch/arm/boot/dts/imx53-tx53.dtsi @@ -201,7 +201,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; + phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; phy-handle = <&phy0>; mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */ status = "okay"; diff --git a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi index 524192cf6a0f..df8dafe2564d 100644 --- a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi +++ b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi @@ -137,7 +137,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; phy-mode = "rmii"; - phy-reset-gpios = <&gpio4 2 0>; + phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index 2cb72824e800..29b45f2e64e0 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -94,7 +94,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 31 0>; + phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index f28883bbe7b1..0c5b2c38214e 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -118,7 +118,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 0>; + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; phy-supply = <&vgen2_1v2_eth>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts index fd2220aa49e2..1f0f950dc11e 100644 --- a/arch/arm/boot/dts/imx6q-evi.dts +++ b/arch/arm/boot/dts/imx6q-evi.dts @@ -135,7 +135,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 0>; + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index 687ab911c13f..9dbeea05a949 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -153,7 +153,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts index 0fa32b2f3aec..c21db67349c4 100644 --- a/arch/arm/boot/dts/imx6q-novena.dts +++ b/arch/arm/boot/dts/imx6q-novena.dts @@ -217,7 +217,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet_novena>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; + phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; rxc-skew-ps = <3000>; rxdv-skew-ps = <0>; txc-skew-ps = <3000>; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi index b2debc0aa720..7d64075204ae 100644 --- a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi +++ b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi @@ -118,7 +118,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rmii"; - phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; + phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi index ec68f1cace31..ed6a89f724a5 100644 --- a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi @@ -320,7 +320,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_HIGH>; + phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_LOW>; txd0-skew-ps = <0>; txd1-skew-ps = <0>; txd2-skew-ps = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi index a9b207751a02..900e8c781f91 100644 --- a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi +++ b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi @@ -46,7 +46,7 @@ pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; phy-mode = "rgmii"; phy-reset-duration = <2>; - phy-reset-gpios = <&gpio4 15 0>; + phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index 70772ebadd4d..f22e5879340b 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -271,7 +271,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 27 0>; + phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; txen-skew-ps = <0>; txc-skew-ps = <3000>; rxdv-skew-ps = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 58055ceec6dc..db705f1cbe37 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -178,7 +178,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 0>; + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index a146fe7fdc5a..c6bec97fbeaf 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -248,7 +248,7 @@ <&clks IMX6QDL_CLK_ENET_REF>; clock-names = "ipg", "ahb", "ptp", "enet_out"; phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; + phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; phy-handle = <&etnphy>; phy-supply = <®_3v3_etn>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index 850ceadbc2cf..b4fa7f1d63da 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -209,7 +209,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 29 0>; + phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts b/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts index 7c5dd1b316ca..28d055e3f301 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts +++ b/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts @@ -78,7 +78,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio &pinctrl_etnphy1_rst>; phy-mode = "rmii"; - phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; phy-supply = <®_3v3_etn>; phy-handle = <&etnphy1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi index 4ccc9e9d2c29..ec745eb3b6a8 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi @@ -307,7 +307,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>; phy-mode = "rmii"; - phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>; + phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; phy-supply = <®_3v3_etn>; phy-handle = <&etnphy0>; status = "okay"; @@ -342,7 +342,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>; phy-mode = "rmii"; - phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; phy-supply = <®_3v3_etn>; phy-handle = <&etnphy1>; status = "disabled"; -- cgit v1.2.3 From b877039aa1fe3a9ac784619a3415feed50e6fb91 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 5 Jun 2017 08:17:47 -0300 Subject: ARM: dts: imx7d-sdb: Adjust the regulator nodes It is not recommended to place the regulator nodes inside 'simple-bus', so adjust them accordingly. The motivation for rearranging this is to make it easier to add new regulator nodes in the future. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-sdb.dts | 66 +++++++++++++++++------------------------ 1 file changed, 28 insertions(+), 38 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 4a4b522d17d2..291f556029f6 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -73,47 +73,37 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb_otg1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_usb_otg2_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usb_otg2_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_can2_3v3: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "can2-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; + reg_can2_3v3: regulator-can2-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; - reg_vref_1v8: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; }; -- cgit v1.2.3 From 6e823e9720b7e2aa36138bc776001069df851e13 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 5 Jun 2017 08:17:48 -0300 Subject: ARM: dts: imx7d-sdb: Add Wifi support imx7d-sdb has a BCM4339 Wifi chip connected to USDHC2. Add support for it. While at it, move the WL_REG_ON pin to the correct pinctrl node. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-sdb.dts | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 291f556029f6..52e40c1d8d40 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -105,6 +105,18 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + reg_brcm: regulator-brcm { + compatible = "regulator-fixed"; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "brcm_reg"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <200000>; + }; }; &adc1 { @@ -379,6 +391,19 @@ status = "okay"; }; +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + wakeup-source; + keep-power-in-suspend; + non-removable; + vmmc-supply = <®_brcm>; + fsl,tuning-step = <2>; + status = "okay"; +}; + &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -403,6 +428,12 @@ pinctrl-0 = <&pinctrl_hog>; imx7d-sdb { + pinctrl_brcm_reg: brcmreggrp { + fsl,pins = < + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14 + >; + }; + pinctrl_ecspi3: ecspi3grp { fsl,pins = < MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 @@ -570,7 +601,6 @@ MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 - MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59 /* WL_REG_ON */ >; }; -- cgit v1.2.3 From 3229f83bd8baf7bdbe8056e468743fdcba492e28 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 5 Jun 2017 08:17:49 -0300 Subject: ARM: dts: imx7d-sdb: Add Bluetooth support imx7d-sdb has a BCM4339 BT chip connected to UART6. Add support for it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-sdb.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 52e40c1d8d40..54c45402286b 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -370,6 +370,15 @@ status = "okay"; }; +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + uart-has-rtscts; + status = "okay"; +}; + &usbotg1 { vbus-supply = <®_usb_otg1_vbus>; status = "okay"; -- cgit v1.2.3 From bb817bef3b1989a9cdb40362cfb8d2aa224ac1bc Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Fri, 2 Jun 2017 13:52:07 +0000 Subject: efi/arm: Enable DMI/SMBIOS Wire up the existing arm64 support for SMBIOS tables (aka DMI) for ARM as well, by moving the arm64 init code to drivers/firmware/efi/arm-runtime.c (which is shared between ARM and arm64), and adding a asm/dmi.h header to ARM that defines the mapping routines for the firmware tables. This allows userspace to access these tables to discover system information exposed by the firmware. It also sets the hardware name used in crash dumps, e.g.: Unable to handle kernel NULL pointer dereference at virtual address 00000000 pgd = ed3c0000 [00000000] *pgd=bf1f3835 Internal error: Oops: 817 [#1] SMP THUMB2 Modules linked in: CPU: 0 PID: 759 Comm: bash Not tainted 4.10.0-09601-g0e8f38792120-dirty #112 Hardware name: QEMU KVM Virtual Machine, BIOS 0.0.0 02/06/2015 ^^^ NOTE: This does *NOT* enable or encourage the use of DMI quirks, i.e., the the practice of identifying the platform via DMI to decide whether certain workarounds for buggy hardware and/or firmware need to be enabled. This would require the DMI subsystem to be enabled much earlier than we do on ARM, which is non-trivial. Signed-off-by: Ard Biesheuvel Acked-by: Russell King Cc: Linus Torvalds Cc: Matt Fleming Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: linux-efi@vger.kernel.org Link: http://lkml.kernel.org/r/20170602135207.21708-14-ard.biesheuvel@linaro.org Signed-off-by: Ingo Molnar --- arch/arm/Kconfig | 17 +++++++++++++++++ arch/arm/include/asm/dmi.h | 19 +++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 arch/arm/include/asm/dmi.h (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4c1a35f15838..dabcaeb2ee3e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -2061,6 +2061,23 @@ config EFI is only useful for kernels that may run on systems that have UEFI firmware. +config DMI + bool "Enable support for SMBIOS (DMI) tables" + depends on EFI + default y + help + This enables SMBIOS/DMI feature for systems. + + This option is only useful on systems that have UEFI firmware. + However, even with this option, the resultant kernel should + continue to boot on existing non-UEFI platforms. + + NOTE: This does *NOT* enable or encourage the use of DMI quirks, + i.e., the the practice of identifying the platform via DMI to + decide whether certain workarounds for buggy hardware and/or + firmware need to be enabled. This would require the DMI subsystem + to be enabled much earlier than we do on ARM, which is non-trivial. + endmenu menu "CPU Power Management" diff --git a/arch/arm/include/asm/dmi.h b/arch/arm/include/asm/dmi.h new file mode 100644 index 000000000000..df2d2ff06f5b --- /dev/null +++ b/arch/arm/include/asm/dmi.h @@ -0,0 +1,19 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_DMI_H +#define __ASM_DMI_H + +#include +#include + +#define dmi_early_remap(x, l) memremap(x, l, MEMREMAP_WB) +#define dmi_early_unmap(x, l) memunmap(x) +#define dmi_remap(x, l) memremap(x, l, MEMREMAP_WB) +#define dmi_unmap(x) memunmap(x) +#define dmi_alloc(l) kzalloc(l, GFP_KERNEL) + +#endif -- cgit v1.2.3 From 031229b862f13ee5af8e1b06af258614f94dcbcd Mon Sep 17 00:00:00 2001 From: Markus Elfring Date: Sun, 4 Jun 2017 20:50:55 +0200 Subject: arm/xen: Improve a size determination in __set_phys_to_machine_multi() Replace the specification of a data structure by a pointer dereference as the parameter for the operator "sizeof" to make the corresponding size determination a bit safer according to the Linux coding style convention. Signed-off-by: Markus Elfring Reviewed-by: Stefano Stabellini --- arch/arm/xen/p2m.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/xen/p2m.c b/arch/arm/xen/p2m.c index 0ed01f2d5ee4..11e78432b663 100644 --- a/arch/arm/xen/p2m.c +++ b/arch/arm/xen/p2m.c @@ -144,7 +144,7 @@ bool __set_phys_to_machine_multi(unsigned long pfn, return true; } - p2m_entry = kzalloc(sizeof(struct xen_p2m_entry), GFP_NOWAIT); + p2m_entry = kzalloc(sizeof(*p2m_entry), GFP_NOWAIT); if (!p2m_entry) { pr_warn("cannot allocate xen_p2m_entry\n"); return false; -- cgit v1.2.3 From d6bb4ec32c832fb0fcc43636327e17a0724e2324 Mon Sep 17 00:00:00 2001 From: Markus Elfring Date: Sun, 4 Jun 2017 21:12:36 +0200 Subject: arm/xen: Delete an error message for a failed memory allocation in __set_phys_to_machine_multi() Omit an extra message for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Link: http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings-WSang_0.pdf Signed-off-by: Markus Elfring Reviewed-by: Stefano Stabellini --- arch/arm/xen/p2m.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/xen/p2m.c b/arch/arm/xen/p2m.c index 11e78432b663..f5f74ac637b9 100644 --- a/arch/arm/xen/p2m.c +++ b/arch/arm/xen/p2m.c @@ -145,10 +145,9 @@ bool __set_phys_to_machine_multi(unsigned long pfn, } p2m_entry = kzalloc(sizeof(*p2m_entry), GFP_NOWAIT); - if (!p2m_entry) { - pr_warn("cannot allocate xen_p2m_entry\n"); + if (!p2m_entry) return false; - } + p2m_entry->pfn = pfn; p2m_entry->nr_pages = nr_pages; p2m_entry->mfn = mfn; -- cgit v1.2.3 From 84a0a967a44b9da6c5effff628aafa7698050574 Mon Sep 17 00:00:00 2001 From: Markus Elfring Date: Sun, 4 Jun 2017 21:21:20 +0200 Subject: arm/xen: Adjust one function call together with a variable assignment The script "checkpatch.pl" pointed information out like the following. ERROR: do not use assignment in if condition Thus fix the affected source code place. Signed-off-by: Markus Elfring Reviewed-by: Stefano Stabellini --- arch/arm/xen/p2m.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/xen/p2m.c b/arch/arm/xen/p2m.c index f5f74ac637b9..e71eefa2e427 100644 --- a/arch/arm/xen/p2m.c +++ b/arch/arm/xen/p2m.c @@ -153,7 +153,8 @@ bool __set_phys_to_machine_multi(unsigned long pfn, p2m_entry->mfn = mfn; write_lock_irqsave(&p2m_lock, irqflags); - if ((rc = xen_add_phys_to_mach_entry(p2m_entry)) < 0) { + rc = xen_add_phys_to_mach_entry(p2m_entry); + if (rc < 0) { write_unlock_irqrestore(&p2m_lock, irqflags); return false; } -- cgit v1.2.3 From f21683ae6ef99d79b3113367cfc6cd51852e8202 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Thu, 20 Apr 2017 16:25:10 +0530 Subject: ARM: dts: uniphier: Use - instead of @ for DT OPP entries Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by: Krzysztof Kozlowski Reported-by: Masahiro Yamada Suggested-by: Mark Rutland Signed-off-by: Viresh Kumar Acked-by: Rob Herring Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-pro5.dtsi | 32 ++++++++++++++++---------------- arch/arm/boot/dts/uniphier-pxs2.dtsi | 16 ++++++++-------- 2 files changed, 24 insertions(+), 24 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index df07b555cbed..81605e3a5e0a 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -77,67 +77,67 @@ compatible = "operating-points-v2"; opp-shared; - opp@100000000 { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; clock-latency-ns = <300>; }; - opp@116667000 { + opp-116667000 { opp-hz = /bits/ 64 <116667000>; clock-latency-ns = <300>; }; - opp@150000000 { + opp-150000000 { opp-hz = /bits/ 64 <150000000>; clock-latency-ns = <300>; }; - opp@175000000 { + opp-175000000 { opp-hz = /bits/ 64 <175000000>; clock-latency-ns = <300>; }; - opp@200000000 { + opp-200000000 { opp-hz = /bits/ 64 <200000000>; clock-latency-ns = <300>; }; - opp@233334000 { + opp-233334000 { opp-hz = /bits/ 64 <233334000>; clock-latency-ns = <300>; }; - opp@300000000 { + opp-300000000 { opp-hz = /bits/ 64 <300000000>; clock-latency-ns = <300>; }; - opp@350000000 { + opp-350000000 { opp-hz = /bits/ 64 <350000000>; clock-latency-ns = <300>; }; - opp@400000000 { + opp-400000000 { opp-hz = /bits/ 64 <400000000>; clock-latency-ns = <300>; }; - opp@466667000 { + opp-466667000 { opp-hz = /bits/ 64 <466667000>; clock-latency-ns = <300>; }; - opp@600000000 { + opp-600000000 { opp-hz = /bits/ 64 <600000000>; clock-latency-ns = <300>; }; - opp@700000000 { + opp-700000000 { opp-hz = /bits/ 64 <700000000>; clock-latency-ns = <300>; }; - opp@800000000 { + opp-800000000 { opp-hz = /bits/ 64 <800000000>; clock-latency-ns = <300>; }; - opp@933334000 { + opp-933334000 { opp-hz = /bits/ 64 <933334000>; clock-latency-ns = <300>; }; - opp@1200000000 { + opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; clock-latency-ns = <300>; }; - opp@1400000000 { + opp-1400000000 { opp-hz = /bits/ 64 <1400000000>; clock-latency-ns = <300>; }; diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index 58c3e2f35706..bc5a1afedee8 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -97,35 +97,35 @@ compatible = "operating-points-v2"; opp-shared; - opp@100000000 { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; clock-latency-ns = <300>; }; - opp@150000000 { + opp-150000000 { opp-hz = /bits/ 64 <150000000>; clock-latency-ns = <300>; }; - opp@200000000 { + opp-200000000 { opp-hz = /bits/ 64 <200000000>; clock-latency-ns = <300>; }; - opp@300000000 { + opp-300000000 { opp-hz = /bits/ 64 <300000000>; clock-latency-ns = <300>; }; - opp@400000000 { + opp-400000000 { opp-hz = /bits/ 64 <400000000>; clock-latency-ns = <300>; }; - opp@600000000 { + opp-600000000 { opp-hz = /bits/ 64 <600000000>; clock-latency-ns = <300>; }; - opp@800000000 { + opp-800000000 { opp-hz = /bits/ 64 <800000000>; clock-latency-ns = <300>; }; - opp@1200000000 { + opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; clock-latency-ns = <300>; }; -- cgit v1.2.3 From 18088678597a27901bc03eb6b67284c68f838417 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sun, 14 May 2017 02:20:49 +0900 Subject: ARM: dts: uniphier: fix simple-bus unit address format error Compiling the UniPhier DT files with W=1, DTC warns like follows: Warning (simple_bus_reg): Node /soc/system-bus@58c00000/support_card@1,1f00000/ethernet@00000000 simple-bus unit address format error, expected "0" Warning (simple_bus_reg): Node /soc/system-bus@58c00000/support_card@1,1f00000/uart@000b0000 simple-bus unit address format error, expected "b0000" Warning (simple_bus_reg): Node /soc/smpctrl@59800000 simple-bus unit address format error, expected "59801000" Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-ld4.dtsi | 2 +- arch/arm/boot/dts/uniphier-pro4.dtsi | 2 +- arch/arm/boot/dts/uniphier-pro5.dtsi | 2 +- arch/arm/boot/dts/uniphier-pxs2.dtsi | 2 +- arch/arm/boot/dts/uniphier-sld3.dtsi | 2 +- arch/arm/boot/dts/uniphier-sld8.dtsi | 2 +- arch/arm/boot/dts/uniphier-support-card.dtsi | 4 ++-- 7 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi index 4f5fe15eaee2..e608895eec2c 100644 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -201,7 +201,7 @@ pinctrl-0 = <&pinctrl_system_bus>; }; - smpctrl@59800000 { + smpctrl@59801000 { compatible = "socionext,uniphier-smpctrl"; reg = <0x59801000 0x400>; }; diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi index 794a85a7068b..f55708efaf1a 100644 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -233,7 +233,7 @@ pinctrl-0 = <&pinctrl_system_bus>; }; - smpctrl@59800000 { + smpctrl@59801000 { compatible = "socionext,uniphier-smpctrl"; reg = <0x59801000 0x400>; }; diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index 81605e3a5e0a..9577769a0add 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -320,7 +320,7 @@ pinctrl-0 = <&pinctrl_system_bus>; }; - smpctrl@59800000 { + smpctrl@59801000 { compatible = "socionext,uniphier-smpctrl"; reg = <0x59801000 0x400>; }; diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index bc5a1afedee8..bf3bafced451 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -304,7 +304,7 @@ pinctrl-0 = <&pinctrl_system_bus>; }; - smpctrl@59800000 { + smpctrl@59801000 { compatible = "socionext,uniphier-smpctrl"; reg = <0x59801000 0x400>; }; diff --git a/arch/arm/boot/dts/uniphier-sld3.dtsi b/arch/arm/boot/dts/uniphier-sld3.dtsi index 01d77edac01f..7c9f41d04e39 100644 --- a/arch/arm/boot/dts/uniphier-sld3.dtsi +++ b/arch/arm/boot/dts/uniphier-sld3.dtsi @@ -216,7 +216,7 @@ #size-cells = <1>; }; - smpctrl@59800000 { + smpctrl@59801000 { compatible = "socionext,uniphier-smpctrl"; reg = <0x59801000 0x400>; }; diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index eb06fdc04b02..19aa13998489 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -201,7 +201,7 @@ pinctrl-0 = <&pinctrl_system_bus>; }; - smpctrl@59800000 { + smpctrl@59801000 { compatible = "socionext,uniphier-smpctrl"; reg = <0x59801000 0x400>; }; diff --git a/arch/arm/boot/dts/uniphier-support-card.dtsi b/arch/arm/boot/dts/uniphier-support-card.dtsi index f61dfec2807f..fdbf0f6e99ae 100644 --- a/arch/arm/boot/dts/uniphier-support-card.dtsi +++ b/arch/arm/boot/dts/uniphier-support-card.dtsi @@ -53,14 +53,14 @@ #size-cells = <1>; ranges = <0x00000000 1 0x01f00000 0x00100000>; - ethsc: ethernet@00000000 { + ethsc: ethernet@0 { compatible = "smsc,lan9118", "smsc,lan9115"; reg = <0x00000000 0x1000>; phy-mode = "mii"; reg-io-width = <4>; }; - serialsc: uart@000b0000 { + serialsc: uart@b0000 { compatible = "ns16550a"; reg = <0x000b0000 0x20>; clock-frequency = <12288000>; -- cgit v1.2.3 From fa53757bca338028338e4e9b8b59ac4ebbdeb80a Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 5 Jun 2017 12:57:58 +0900 Subject: ARM: dts: uniphier: use SPDX-License-Identifier Follow the recent trend for the license description, and fix the wrongly stated X11 to MIT. The X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-ld4-ref.dts | 38 +--------------------------- arch/arm/boot/dts/uniphier-ld4.dtsi | 38 +--------------------------- arch/arm/boot/dts/uniphier-ld6b-ref.dts | 38 +--------------------------- arch/arm/boot/dts/uniphier-ld6b.dtsi | 38 +--------------------------- arch/arm/boot/dts/uniphier-pro4-ace.dts | 38 +--------------------------- arch/arm/boot/dts/uniphier-pro4-ref.dts | 38 +--------------------------- arch/arm/boot/dts/uniphier-pro4-sanji.dts | 38 +--------------------------- arch/arm/boot/dts/uniphier-pro4.dtsi | 38 +--------------------------- arch/arm/boot/dts/uniphier-pxs2-gentil.dts | 38 +--------------------------- arch/arm/boot/dts/uniphier-pxs2-vodka.dts | 38 +--------------------------- arch/arm/boot/dts/uniphier-pxs2.dtsi | 38 +--------------------------- arch/arm/boot/dts/uniphier-ref-daughter.dtsi | 38 +--------------------------- arch/arm/boot/dts/uniphier-sld3-ref.dts | 38 +--------------------------- arch/arm/boot/dts/uniphier-sld3.dtsi | 38 +--------------------------- arch/arm/boot/dts/uniphier-sld8-ref.dts | 38 +--------------------------- arch/arm/boot/dts/uniphier-sld8.dtsi | 38 +--------------------------- arch/arm/boot/dts/uniphier-support-card.dtsi | 38 +--------------------------- 17 files changed, 17 insertions(+), 629 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/uniphier-ld4-ref.dts b/arch/arm/boot/dts/uniphier-ld4-ref.dts index e0da4ee21c21..4817ebb28eb2 100644 --- a/arch/arm/boot/dts/uniphier-ld4-ref.dts +++ b/arch/arm/boot/dts/uniphier-ld4-ref.dts @@ -4,43 +4,7 @@ * Copyright (C) 2015-2016 Socionext Inc. * Author: Masahiro Yamada * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /dts-v1/; diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi index e608895eec2c..fb2fd9605b9d 100644 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -4,43 +4,7 @@ * Copyright (C) 2015-2016 Socionext Inc. * Author: Masahiro Yamada * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ / { diff --git a/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ld6b-ref.dts index a397a8811c78..96db4abc02c3 100644 --- a/arch/arm/boot/dts/uniphier-ld6b-ref.dts +++ b/arch/arm/boot/dts/uniphier-ld6b-ref.dts @@ -4,43 +4,7 @@ * Copyright (C) 2015-2016 Socionext Inc. * Author: Masahiro Yamada * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /dts-v1/; diff --git a/arch/arm/boot/dts/uniphier-ld6b.dtsi b/arch/arm/boot/dts/uniphier-ld6b.dtsi index 905c77d499eb..8b9a79731bd3 100644 --- a/arch/arm/boot/dts/uniphier-ld6b.dtsi +++ b/arch/arm/boot/dts/uniphier-ld6b.dtsi @@ -4,43 +4,7 @@ * Copyright (C) 2015-2016 Socionext Inc. * Author: Masahiro Yamada * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* diff --git a/arch/arm/boot/dts/uniphier-pro4-ace.dts b/arch/arm/boot/dts/uniphier-pro4-ace.dts index fefc89149234..e45bf4f418b9 100644 --- a/arch/arm/boot/dts/uniphier-pro4-ace.dts +++ b/arch/arm/boot/dts/uniphier-pro4-ace.dts @@ -4,43 +4,7 @@ * Copyright (C) 2016 Socionext Inc. * Author: Masahiro Yamada * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /dts-v1/; diff --git a/arch/arm/boot/dts/uniphier-pro4-ref.dts b/arch/arm/boot/dts/uniphier-pro4-ref.dts index 6077e634d14a..4cf539245f2e 100644 --- a/arch/arm/boot/dts/uniphier-pro4-ref.dts +++ b/arch/arm/boot/dts/uniphier-pro4-ref.dts @@ -4,43 +4,7 @@ * Copyright (C) 2015-2016 Socionext Inc. * Author: Masahiro Yamada * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /dts-v1/; diff --git a/arch/arm/boot/dts/uniphier-pro4-sanji.dts b/arch/arm/boot/dts/uniphier-pro4-sanji.dts index 6c63c8bad825..18836886bc31 100644 --- a/arch/arm/boot/dts/uniphier-pro4-sanji.dts +++ b/arch/arm/boot/dts/uniphier-pro4-sanji.dts @@ -4,43 +4,7 @@ * Copyright (C) 2016 Socionext Inc. * Author: Masahiro Yamada * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /dts-v1/; diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi index f55708efaf1a..37400becf4ba 100644 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -4,43 +4,7 @@ * Copyright (C) 2015-2016 Socionext Inc. * Author: Masahiro Yamada * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ / { diff --git a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts index cccc86658d20..bb39bd171d1a 100644 --- a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts +++ b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts @@ -4,43 +4,7 @@ * Copyright (C) 2015-2016 Socionext Inc. * Author: Masahiro Yamada * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /dts-v1/; diff --git a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts index 803a39aa39d0..dc2d0579c666 100644 --- a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts +++ b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts @@ -4,43 +4,7 @@ * Copyright (C) 2015-2016 Socionext Inc. * Author: Masahiro Yamada * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /dts-v1/; diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index bf3bafced451..bace751d4023 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -4,43 +4,7 @@ * Copyright (C) 2015-2016 Socionext Inc. * Author: Masahiro Yamada * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ / { diff --git a/arch/arm/boot/dts/uniphier-ref-daughter.dtsi b/arch/arm/boot/dts/uniphier-ref-daughter.dtsi index c62ae1a81f47..7a1c29b558d5 100644 --- a/arch/arm/boot/dts/uniphier-ref-daughter.dtsi +++ b/arch/arm/boot/dts/uniphier-ref-daughter.dtsi @@ -4,43 +4,7 @@ * Copyright (C) 2015-2017 Socionext Inc. * Author: Masahiro Yamada * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ &i2c0 { diff --git a/arch/arm/boot/dts/uniphier-sld3-ref.dts b/arch/arm/boot/dts/uniphier-sld3-ref.dts index eb63dcca92b5..70cda39a3dd2 100644 --- a/arch/arm/boot/dts/uniphier-sld3-ref.dts +++ b/arch/arm/boot/dts/uniphier-sld3-ref.dts @@ -4,43 +4,7 @@ * Copyright (C) 2015-2016 Socionext Inc. * Author: Masahiro Yamada * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /dts-v1/; diff --git a/arch/arm/boot/dts/uniphier-sld3.dtsi b/arch/arm/boot/dts/uniphier-sld3.dtsi index 7c9f41d04e39..408287936613 100644 --- a/arch/arm/boot/dts/uniphier-sld3.dtsi +++ b/arch/arm/boot/dts/uniphier-sld3.dtsi @@ -4,43 +4,7 @@ * Copyright (C) 2015-2016 Socionext Inc. * Author: Masahiro Yamada * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ / { diff --git a/arch/arm/boot/dts/uniphier-sld8-ref.dts b/arch/arm/boot/dts/uniphier-sld8-ref.dts index 737d276349fd..4536d5b71297 100644 --- a/arch/arm/boot/dts/uniphier-sld8-ref.dts +++ b/arch/arm/boot/dts/uniphier-sld8-ref.dts @@ -4,43 +4,7 @@ * Copyright (C) 2015-2016 Socionext Inc. * Author: Masahiro Yamada * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /dts-v1/; diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index 19aa13998489..9fb9167f2db4 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -4,43 +4,7 @@ * Copyright (C) 2015-2016 Socionext Inc. * Author: Masahiro Yamada * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ / { diff --git a/arch/arm/boot/dts/uniphier-support-card.dtsi b/arch/arm/boot/dts/uniphier-support-card.dtsi index fdbf0f6e99ae..6c825f192e65 100644 --- a/arch/arm/boot/dts/uniphier-support-card.dtsi +++ b/arch/arm/boot/dts/uniphier-support-card.dtsi @@ -4,43 +4,7 @@ * Copyright (C) 2015-2017 Socionext Inc. * Author: Masahiro Yamada * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ &system_bus { -- cgit v1.2.3 From 5533b0cda3bf8b17e3688cce4b66bd5448d6cd1e Mon Sep 17 00:00:00 2001 From: Sven Eckelmann Date: Fri, 28 Apr 2017 12:10:36 +0200 Subject: ARM: dts: qcom: add gsbi7 serial to ipq8064 SoC device tree The gsbi_serial7 under gsbi7 is used by the IPQ8068 based board EWS870AP as main serial console. Signed-off-by: Sven Eckelmann Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 76f4e8921d58..f1fbffe59b93 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -284,6 +284,29 @@ }; }; + gsbi7: gsbi@16600000 { + status = "disabled"; + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <7>; + reg = <0x16600000 0x100>; + clocks = <&gcc GSBI7_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + syscon-tcsr = <&tcsr>; + + gsbi7_serial: serial@16640000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16640000 0x1000>, + <0x16600000 0x1000>; + interrupts = <0 158 0x0>; + clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + sata_phy: sata-phy@1b400000 { compatible = "qcom,ipq806x-sata-phy"; reg = <0x1b400000 0x200>; -- cgit v1.2.3 From 650df439cfb96c303328935559b2d06127a5a0b0 Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Tue, 2 May 2017 21:19:24 +0200 Subject: ARM: dts: qcom: ipq4019: fix i2c_0 node This patch fixes two typos in the i2c_0 node for the ipq4019. The reg property length is just 0x600. The core clock is GCC_BLSP1_QUP1_I2C_APPS_CLK. GCC_BLSP1_QUP2_I2C_APPS_CLK is used by the second i2c. Fixes: e76b4284b520ba3 ("qcom: ipq4019: add i2c node to ipq4019 SoC and DK01 device tree") Signed-off-by: Christian Lamparter Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index b7a24af8f47b..4b7d97275c62 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -154,10 +154,10 @@ i2c_0: i2c@78b7000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x78b7000 0x6000>; + reg = <0x78b7000 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; clock-names = "iface", "core"; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 6d78cea61c31bca8a8c84a3e1121453a2f147da2 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 13 May 2017 16:15:43 +0200 Subject: ARM: dts: add XOADC and IIO HWMON to MSM8660/APQ8060 This adds the PM8058 XOADC node to the PM8058 PMIC node, defines the 16 channels and further also define an IIO HWMON node for the channels that are used for housekeeping of voltages and die temperature for the PMIC chip die. Tested on the APQ8060 DragonBoard: cd /sys/class/hwmon/hwmon0 cat in2_input 4773 (DC mains ~5V) cat in4_input 625 (0.625V reference voltage) cat in5_input 1250 (1.25V reference voltage) cat temp1_input 35852 (die temperature) Signed-off-by: Linus Walleij Acked-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-msm8660.dtsi | 59 +++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 747669a62aa8..f5631e810e9d 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -63,6 +63,22 @@ }; }; + /* + * These channels from the ADC are simply hardware monitors. + * That is why the ADC is referred to as "HKADC" - HouseKeeping + * ADC. + */ + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&xoadc 0x00 0x01>, /* Battery */ + <&xoadc 0x00 0x02>, /* DC in (charger) */ + <&xoadc 0x00 0x04>, /* VPH the main system voltage */ + <&xoadc 0x00 0x0b>, /* Die temperature */ + <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ + <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ + <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */ + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -267,6 +283,49 @@ row-hold = <91500>; }; + xoadc: xoadc@197 { + compatible = "qcom,pm8058-adc"; + reg = <0x197>; + interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>; + #address-cells = <2>; + #size-cells = <0>; + #io-channel-cells = <2>; + + vcoin: adc-channel@00 { + reg = <0x00 0x00>; + }; + vbat: adc-channel@01 { + reg = <0x00 0x01>; + }; + dcin: adc-channel@02 { + reg = <0x00 0x02>; + }; + ichg: adc-channel@03 { + reg = <0x00 0x03>; + }; + vph_pwr: adc-channel@04 { + reg = <0x00 0x04>; + }; + usb_vbus: adc-channel@0a { + reg = <0x00 0x0a>; + }; + die_temp: adc-channel@0b { + reg = <0x00 0x0b>; + }; + ref_625mv: adc-channel@0c { + reg = <0x00 0x0c>; + }; + ref_1250mv: adc-channel@0d { + reg = <0x00 0x0d>; + }; + ref_325mv: adc-channel@0e { + reg = <0x00 0x0e>; + }; + ref_muxoff: adc-channel@0f { + reg = <0x00 0x0f>; + }; + }; + rtc@1e8 { compatible = "qcom,pm8058-rtc"; reg = <0x1e8>; -- cgit v1.2.3 From 567cf21350e443802c382104c3ebd5cd7a2b70c2 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 13 May 2017 16:15:53 +0200 Subject: ARM: dts: Qualcomm APQ8060 DragonBoard ALS sensor This adds the Capella CM3605 ambient light and proximity sensor to the APQ8060 DragonBoard device tree. Notice that we also set up pin config for the AOUT line and GPIO lines, and that we set the default trigger on the infrared LED to associate with the "cm3605" trigger so the IR LED is controlled by this the CM3605 driver. Signed-off-by: Linus Walleij Acked-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8060-dragonboard.dts | 80 ++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index 2da1413f5720..5225e489ef52 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -23,6 +23,7 @@ #include #include #include +#include #include "qcom-msm8660.dtsi" / { @@ -83,6 +84,25 @@ }; }; + /* + * Capella CM3605 light and proximity sensor mounted directly + * on the sensor board. + */ + cm3605 { + compatible = "capella,cm3605"; + vdd-supply = <&pm8058_l14>; // 2.85V + aset-gpios = <&pm8058_gpio 35 GPIO_ACTIVE_LOW>; + capella,aset-resistance-ohms = <100000>; + /* GPIO34 has interrupt 225 on the PM8058 */ + /* Trig on both edges - getting close or far away */ + interrupts-extended = <&pm8058 225 IRQ_TYPE_EDGE_BOTH>; + /* MPP05 analog input to the XOADC */ + io-channels = <&xoadc 0x00 0x05>; + io-channel-names = "aout"; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_cm3605_gpios>, <&dragon_cm3605_mpps>; + }; + soc { pinctrl@800000 { /* eMMMC pins, all 8 data lines connected */ @@ -317,6 +337,24 @@ power-source = ; }; }; + dragon_cm3605_gpios: cm3605-gpios { + /* Pin 34 connected to the proxy IRQ */ + pinconf_gpio34 { + pins = "gpio34"; + function = "normal"; + input-enable; + bias-disable; + power-source = ; + }; + /* Pin 35 connected to ASET */ + pinconf_gpio35 { + pins = "gpio35"; + function = "normal"; + output-high; + bias-disable; + power-source = ; + }; + }; dragon_veth_gpios: veth-gpios { pinconf { pins = "gpio40"; @@ -327,6 +365,47 @@ }; }; + mpps@50 { + dragon_cm3605_mpps: cm3605-mpps { + pinconf { + pins = "mpp5"; + function = "analog"; + input-enable; + bias-high-impedance; + /* Let's use channel 5 */ + qcom,amux-route = ; + power-source = ; + }; + }; + }; + + xoadc@197 { + /* Reference voltage 2.2 V */ + xoadc-ref-supply = <&pm8058_l18>; + + /* Board-specific channels */ + mpp5@05 { + /* Connected to AOUT of ALS sensor */ + reg = <0x00 0x05>; + }; + mpp6@06 { + /* Connected to test point TP43 */ + reg = <0x00 0x06>; + }; + mpp7@07 { + /* Connected to battery thermistor */ + reg = <0x00 0x07>; + }; + mpp8@08 { + /* Connected to battery ID detector */ + reg = <0x00 0x08>; + }; + mpp9@09 { + /* Connected to XO thermistor */ + reg = <0x00 0x09>; + }; + }; + led@48 { /* * The keypad LED @0x48 is routed to @@ -340,6 +419,7 @@ reg = <0x48>; label = "pm8058:infrared:proximitysensor"; default-state = "off"; + linux,default-trigger = "cm3605"; }; led@131 { compatible = "qcom,pm8058-led"; -- cgit v1.2.3 From 5594207294fcbfe8e9fe86c81d1d8b88cb530e66 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 15 May 2017 09:50:12 +0200 Subject: ARM: dts: add GSBI8 defines to the MSM8660 family This defines the memory location and interrupt used by the GSBI8 I2C adapter on the MSM8660 SoCs. We add it as "disabled" by default so that boards using this I2C can enable it. Signed-off-by: Linus Walleij Acked-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-msm8660.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index f5631e810e9d..1b5d31b33b5e 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -123,6 +123,31 @@ reg = <0x900000 0x4000>; }; + + gsbi8: gsbi@19800000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; + reg = <0x19800000 0x100>; + clocks = <&gcc GSBI8_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi8_i2c: i2c@19880000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x19880000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + gsbi12: gsbi@19c00000 { compatible = "qcom,gsbi-v1.0.0"; cell-index = <12>; -- cgit v1.2.3 From 1d917530c9ed2585cf3ed7db933e85a41b45141f Mon Sep 17 00:00:00 2001 From: Abhishek Sahu Date: Fri, 28 Apr 2017 15:57:53 +0530 Subject: ARM: qcom_defconfig: Enable IPQ4019 clock and pinctrl These configs are required for booting kernel in QCOM IPQ4019 boards. Signed-off-by: Abhishek Sahu Signed-off-by: Andy Gross --- arch/arm/configs/qcom_defconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig index 07666a7a9de5..33f248058284 100644 --- a/arch/arm/configs/qcom_defconfig +++ b/arch/arm/configs/qcom_defconfig @@ -113,6 +113,7 @@ CONFIG_SPI_QUP=y CONFIG_SPMI=y CONFIG_PINCTRL_APQ8064=y CONFIG_PINCTRL_APQ8084=y +CONFIG_PINCTRL_IPQ4019=y CONFIG_PINCTRL_IPQ8064=y CONFIG_PINCTRL_MSM8660=y CONFIG_PINCTRL_MSM8960=y @@ -182,6 +183,7 @@ CONFIG_COMMON_CLK_QCOM=y CONFIG_QCOM_CLK_RPM=y CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_APQ_MMCC_8084=y +CONFIG_IPQ_GCC_4019=y CONFIG_IPQ_LCC_806X=y CONFIG_MSM_GCC_8660=y CONFIG_MSM_LCC_8960=y -- cgit v1.2.3 From 7b87fe94299c965adcab384486ee3bf82ad15f9c Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Tue, 28 Mar 2017 01:11:40 +0200 Subject: ARM: debug: qcom: add UART addresses to Kconfig help for IPQ4019 Add information about the IPQ4019 debug UART physical and virtual addresses in the DEBUG_QCOM_UARTDM Kconfig help section. Signed-off-by: Christian Lamparter Signed-off-by: Andy Gross --- arch/arm/Kconfig.debug | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 426d2716f55d..0e5c1f9c546a 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -751,6 +751,7 @@ choice ARCH DEBUG_UART_PHYS DEBUG_UART_VIRT APQ8064 0x16640000 0xf0040000 APQ8084 0xf995e000 0xfa75e000 + IPQ4019 0x078af000 0xf78af000 MSM8X60 0x19c40000 0xf0040000 MSM8960 0x16440000 0xf0040000 MSM8974 0xf991e000 0xfa71e000 -- cgit v1.2.3 From 8d39ff3d1696f7c6122500e21016f6837984ad8b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 31 May 2017 15:51:30 -0700 Subject: ARM: OMAP2+: Remove unused legacy code for timer We are now booting all mach-omap2 in device tree only mode. Any code that is only called in legacy boot mode where of_have_populated_dt() is not set is safe to remove now. Reviewed-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/timer.c | 169 +++++--------------------------------------- 1 file changed, 19 insertions(+), 150 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 07dd692c4737..e4be76016939 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -232,37 +232,27 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, const char **timer_name, int posted) { - char name[10]; /* 10 = sizeof("gptXX_Xck0") */ const char *oh_name = NULL; struct device_node *np; struct omap_hwmod *oh; - struct resource irq, mem; struct clk *src; int r = 0; - if (of_have_populated_dt()) { - np = omap_get_timer_dt(omap_timer_match, property); - if (!np) - return -ENODEV; + np = omap_get_timer_dt(omap_timer_match, property); + if (!np) + return -ENODEV; - of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); - if (!oh_name) - return -ENODEV; + of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); + if (!oh_name) + return -ENODEV; - timer->irq = irq_of_parse_and_map(np, 0); - if (!timer->irq) - return -ENXIO; + timer->irq = irq_of_parse_and_map(np, 0); + if (!timer->irq) + return -ENXIO; - timer->io_base = of_iomap(np, 0); + timer->io_base = of_iomap(np, 0); - of_node_put(np); - } else { - if (omap_dm_timer_reserve_systimer(timer->id)) - return -ENODEV; - - sprintf(name, "timer%d", timer->id); - oh_name = name; - } + of_node_put(np); oh = omap_hwmod_lookup(oh_name); if (!oh) @@ -270,22 +260,6 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, *timer_name = oh->name; - if (!of_have_populated_dt()) { - r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, - &irq); - if (r) - return -ENXIO; - timer->irq = irq.start; - - r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, - &mem); - if (r) - return -ENXIO; - - /* Static mapping, never released */ - timer->io_base = ioremap(mem.start, mem.end - mem.start); - } - if (!timer->io_base) return -ENXIO; @@ -405,18 +379,15 @@ static int __init __maybe_unused omap2_sync32k_clocksource_init(void) const char *oh_name = "counter_32k"; /* - * If device-tree is present, then search the DT blob - * to see if the 32kHz counter is supported. + * See if the 32kHz counter is supported. */ - if (of_have_populated_dt()) { - np = omap_get_timer_dt(omap_counter_match, NULL); - if (!np) - return -ENODEV; - - of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); - if (!oh_name) - return -ENODEV; - } + np = omap_get_timer_dt(omap_counter_match, NULL); + if (!np) + return -ENODEV; + + of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); + if (!oh_name) + return -ENODEV; /* * First check hwmod data is available for sync32k counter @@ -434,18 +405,6 @@ static int __init __maybe_unused omap2_sync32k_clocksource_init(void) return ret; } - if (!of_have_populated_dt()) { - void __iomem *vbase; - - vbase = omap_hwmod_get_mpu_rt_va(oh); - - ret = omap_init_clocksource_32k(vbase); - if (ret) { - pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", - __func__, ret); - omap_hwmod_idle(oh); - } - } return ret; } @@ -660,96 +619,6 @@ void __init omap5_realtime_timer_init(void) } #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */ -/** - * omap_timer_init - build and register timer device with an - * associated timer hwmod - * @oh: timer hwmod pointer to be used to build timer device - * @user: parameter that can be passed from calling hwmod API - * - * Called by omap_hwmod_for_each_by_class to register each of the timer - * devices present in the system. The number of timer devices is known - * by parsing through the hwmod database for a given class name. At the - * end of function call memory is allocated for timer device and it is - * registered to the framework ready to be proved by the driver. - */ -static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) -{ - int id; - int ret = 0; - char *name = "omap_timer"; - struct dmtimer_platform_data *pdata; - struct platform_device *pdev; - struct omap_timer_capability_dev_attr *timer_dev_attr; - - pr_debug("%s: %s\n", __func__, oh->name); - - /* on secure device, do not register secure timer */ - timer_dev_attr = oh->dev_attr; - if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) - if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) - return ret; - - pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); - if (!pdata) { - pr_err("%s: No memory for [%s]\n", __func__, oh->name); - return -ENOMEM; - } - - /* - * Extract the IDs from name field in hwmod database - * and use the same for constructing ids' for the - * timer devices. In a way, we are avoiding usage of - * static variable witin the function to do the same. - * CAUTION: We have to be careful and make sure the - * name in hwmod database does not change in which case - * we might either make corresponding change here or - * switch back static variable mechanism. - */ - sscanf(oh->name, "timer%2d", &id); - - if (timer_dev_attr) - pdata->timer_capability = timer_dev_attr->timer_capability; - - pdata->timer_errata = omap_dm_timer_get_errata(); - pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; - - pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata)); - - if (IS_ERR(pdev)) { - pr_err("%s: Can't build omap_device for %s: %s.\n", - __func__, name, oh->name); - ret = -EINVAL; - } - - kfree(pdata); - - return ret; -} - -/** - * omap2_dm_timer_init - top level regular device initialization - * - * Uses dedicated hwmod api to parse through hwmod database for - * given class name and then build and register the timer device. - */ -static int __init omap2_dm_timer_init(void) -{ - int ret; - - /* If dtb is there, the devices will be created dynamically */ - if (of_have_populated_dt()) - return -ENODEV; - - ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); - if (unlikely(ret)) { - pr_err("%s: device registration failed.\n", __func__); - return -EINVAL; - } - - return 0; -} -omap_arch_initcall(omap2_dm_timer_init); - /** * omap2_override_clocksource - clocksource override with user configuration * -- cgit v1.2.3 From 138f7ca78f5a0677f591fdf23d0309c2f4774bf7 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 31 May 2017 17:59:58 +0300 Subject: ARM: OMAP2+: timer: add support for fetching fck handle from DT The mux clock handle shall be provided via "fck" DT handle. This avoids the need to lookup the main clock via hwmod core, which will not work with the clkctrl clock support anymore; the main clock is not going to be a mux. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/timer.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 07dd692c4737..af90f95c2433 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -255,6 +255,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, timer->io_base = of_iomap(np, 0); + timer->fclk = of_clk_get_by_name(np, "fck"); + of_node_put(np); } else { if (omap_dm_timer_reserve_systimer(timer->id)) @@ -292,7 +294,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, omap_hwmod_setup_one(oh_name); /* After the dmtimer is using hwmod these clocks won't be needed */ - timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); + if (IS_ERR_OR_NULL(timer->fclk)) + timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); if (IS_ERR(timer->fclk)) return PTR_ERR(timer->fclk); -- cgit v1.2.3 From 24d8d498a8703462f0141f2fcdcd325de1ab2bb8 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 31 May 2017 17:59:59 +0300 Subject: ARM: OMAP4: hwmod_data: add opt clks for dss_hdmi and dss_venc These extra optional clocks are required as main clock for these modules are going to be routed to the main module clock. Otherwise, the hdmi / tv clocks are not going to be enabled during usage, leading to failure. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 94f09c720f29..0855434773fa 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -775,6 +775,7 @@ static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { { .role = "sys_clk", .clk = "dss_sys_clk" }, + { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, }; static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { @@ -785,7 +786,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { * HDMI audio requires to use no-idle mode. Hence, * set idle mode by software. */ - .flags = HWMOD_SWSUP_SIDLE, + .flags = HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED, .mpu_irqs = omap44xx_dss_hdmi_irqs, .xlate_irq = omap4_xlate_irq, .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, @@ -858,11 +859,16 @@ static struct omap_hwmod_class omap44xx_venc_hwmod_class = { }; /* dss_venc */ +static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { + { .role = "tv_clk", .clk = "dss_tv_clk" }, +}; + static struct omap_hwmod omap44xx_dss_venc_hwmod = { .name = "dss_venc", .class = &omap44xx_venc_hwmod_class, .clkdm_name = "l3_dss_clkdm", .main_clk = "dss_tv_clk", + .flags = HWMOD_OPT_CLKS_NEEDED, .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, @@ -870,6 +876,8 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = { }, }, .parent_hwmod = &omap44xx_dss_hwmod, + .opt_clks = dss_venc_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), }; /* -- cgit v1.2.3 From 90129336712c3c8dcd0d81a5dfaea52dd8391e62 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 31 May 2017 18:00:00 +0300 Subject: ARM: OMAP2+: PRCM: store also physical addresses for instances In some cases the physical address info is needed, so store this under the existing cm*_base, prm_base and prcm_mpu_base variables. These are converted now to structs that contain both virtual and physical address base for the instance. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/cm.h | 7 +++++-- arch/arm/mach-omap2/cm2xxx_3xxx.h | 4 ++-- arch/arm/mach-omap2/cm33xx.c | 4 ++-- arch/arm/mach-omap2/cm3xxx.c | 3 ++- arch/arm/mach-omap2/cm_common.c | 31 +++++++++++++++++++------------ arch/arm/mach-omap2/cminst44xx.c | 19 ++++++++++--------- arch/arm/mach-omap2/prcm-common.h | 7 +++++++ arch/arm/mach-omap2/prcm_mpu44xx.c | 4 ++-- arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h | 4 +++- arch/arm/mach-omap2/prm.h | 2 +- arch/arm/mach-omap2/prm2xxx_3xxx.h | 4 ++-- arch/arm/mach-omap2/prm33xx.c | 4 ++-- arch/arm/mach-omap2/prm3xxx.c | 2 +- arch/arm/mach-omap2/prm44xx.c | 4 ++-- arch/arm/mach-omap2/prm_common.c | 23 +++++++++++++---------- arch/arm/mach-omap2/prminst44xx.c | 16 +++++++++------- 16 files changed, 82 insertions(+), 56 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index de75cbcdc9d1..e833984cc85e 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -24,8 +24,11 @@ # ifndef __ASSEMBLER__ #include -extern void __iomem *cm_base; -extern void __iomem *cm2_base; + +#include "prcm-common.h" + +extern struct omap_domain_base cm_base; +extern struct omap_domain_base cm2_base; extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2); # endif diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h index 72928a3ce2aa..aa148cd57cc1 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h @@ -52,12 +52,12 @@ static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx) { - return readl_relaxed(cm_base + module + idx); + return readl_relaxed(cm_base.va + module + idx); } static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx) { - writel_relaxed(val, cm_base + module + idx); + writel_relaxed(val, cm_base.va + module + idx); } /* Read-modify-write a register in a CM module. Caller must lock */ diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c index 6f2d0aec0513..a9e08d89104e 100644 --- a/arch/arm/mach-omap2/cm33xx.c +++ b/arch/arm/mach-omap2/cm33xx.c @@ -50,13 +50,13 @@ /* Read a register in a CM instance */ static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx) { - return readl_relaxed(cm_base + inst + idx); + return readl_relaxed(cm_base.va + inst + idx); } /* Write into a register in a CM */ static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx) { - writel_relaxed(val, cm_base + inst + idx); + writel_relaxed(val, cm_base.va + inst + idx); } /* Read-modify-write a register in CM */ diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c index 55b046a719dc..961bc478b9de 100644 --- a/arch/arm/mach-omap2/cm3xxx.c +++ b/arch/arm/mach-omap2/cm3xxx.c @@ -669,7 +669,8 @@ static struct cm_ll_data omap3xxx_cm_ll_data = { int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data) { - omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base + OMAP3430_IVA2_MOD); + omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base.va + + OMAP3430_IVA2_MOD); return cm_register(&omap3xxx_cm_ll_data); } diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c index bbe41f4c9dc8..d555791cf349 100644 --- a/arch/arm/mach-omap2/cm_common.c +++ b/arch/arm/mach-omap2/cm_common.c @@ -32,10 +32,10 @@ static struct cm_ll_data null_cm_ll_data; static struct cm_ll_data *cm_ll_data = &null_cm_ll_data; /* cm_base: base virtual address of the CM IP block */ -void __iomem *cm_base; +struct omap_domain_base cm_base; /* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */ -void __iomem *cm2_base; +struct omap_domain_base cm2_base; #define CM_NO_CLOCKS 0x1 #define CM_SINGLE_INSTANCE 0x2 @@ -49,8 +49,8 @@ void __iomem *cm2_base; */ void __init omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2) { - cm_base = cm; - cm2_base = cm2; + cm_base.va = cm; + cm2_base.va = cm2; } /** @@ -315,27 +315,34 @@ int __init omap2_cm_base_init(void) struct device_node *np; const struct of_device_id *match; struct omap_prcm_init_data *data; - void __iomem *mem; + struct resource res; + int ret; + struct omap_domain_base *mem = NULL; for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) { data = (struct omap_prcm_init_data *)match->data; - mem = of_iomap(np, 0); - if (!mem) - return -ENOMEM; + ret = of_address_to_resource(np, 0, &res); + if (ret) + return ret; if (data->index == TI_CLKM_CM) - cm_base = mem + data->offset; + mem = &cm_base; if (data->index == TI_CLKM_CM2) - cm2_base = mem + data->offset; + mem = &cm2_base; + + data->mem = ioremap(res.start, resource_size(&res)); - data->mem = mem; + if (mem) { + mem->pa = res.start + data->offset; + mem->va = data->mem + data->offset; + } data->np = np; if (data->init && (data->flags & CM_SINGLE_INSTANCE || - (cm_base && cm2_base))) + (cm_base.va && cm2_base.va))) data->init(data); } diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c index 2ab27ade136a..cfa10a31b953 100644 --- a/arch/arm/mach-omap2/cminst44xx.c +++ b/arch/arm/mach-omap2/cminst44xx.c @@ -55,7 +55,7 @@ #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 #define CLKCTRL_IDLEST_DISABLED 0x3 -static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS]; +static struct omap_domain_base _cm_bases[OMAP4_MAX_PRCM_PARTITIONS]; /** * omap_cm_base_init - Populates the cm partitions @@ -65,10 +65,11 @@ static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS]; */ static void omap_cm_base_init(void) { - _cm_bases[OMAP4430_PRM_PARTITION] = prm_base; - _cm_bases[OMAP4430_CM1_PARTITION] = cm_base; - _cm_bases[OMAP4430_CM2_PARTITION] = cm2_base; - _cm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base; + memcpy(&_cm_bases[OMAP4430_PRM_PARTITION], &prm_base, sizeof(prm_base)); + memcpy(&_cm_bases[OMAP4430_CM1_PARTITION], &cm_base, sizeof(cm_base)); + memcpy(&_cm_bases[OMAP4430_CM2_PARTITION], &cm2_base, sizeof(cm2_base)); + memcpy(&_cm_bases[OMAP4430_PRCM_MPU_PARTITION], &prcm_mpu_base, + sizeof(prcm_mpu_base)); } /* Private functions */ @@ -116,8 +117,8 @@ static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx) { BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || part == OMAP4430_INVALID_PRCM_PARTITION || - !_cm_bases[part]); - return readl_relaxed(_cm_bases[part] + inst + idx); + !_cm_bases[part].va); + return readl_relaxed(_cm_bases[part].va + inst + idx); } /* Write into a register in a CM instance */ @@ -125,8 +126,8 @@ static void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx) { BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || part == OMAP4430_INVALID_PRCM_PARTITION || - !_cm_bases[part]); - writel_relaxed(val, _cm_bases[part] + inst + idx); + !_cm_bases[part].va); + writel_relaxed(val, _cm_bases[part].va + inst + idx); } /* Read-modify-write a register in CM1. Caller must lock */ diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index c8f590b7c32d..ee7041d523cf 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -526,10 +526,16 @@ struct omap_prcm_irq_setup { .priority = _priority \ } +struct omap_domain_base { + u32 pa; + void __iomem *va; +}; + /** * struct omap_prcm_init_data - PRCM driver init data * @index: clock memory mapping index to be used * @mem: IO mem pointer for this module + * @phys: IO mem physical base address for this module * @offset: module base address offset from the IO base * @flags: PRCM module init flags * @device_inst_offset: device instance offset within the module address space @@ -539,6 +545,7 @@ struct omap_prcm_irq_setup { struct omap_prcm_init_data { int index; void __iomem *mem; + u32 phys; s16 offset; u16 flags; s32 device_inst_offset; diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.c b/arch/arm/mach-omap2/prcm_mpu44xx.c index cdbee6326d29..9c782f5c3f94 100644 --- a/arch/arm/mach-omap2/prcm_mpu44xx.c +++ b/arch/arm/mach-omap2/prcm_mpu44xx.c @@ -24,7 +24,7 @@ * prcm_mpu_base: the virtual address of the start of the PRCM_MPU IP * block registers */ -void __iomem *prcm_mpu_base; +struct omap_domain_base prcm_mpu_base; /* PRCM_MPU low-level functions */ @@ -58,5 +58,5 @@ u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) */ void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu) { - prcm_mpu_base = prcm_mpu; + prcm_mpu_base.va = prcm_mpu; } diff --git a/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h index ca149e70bed0..f565f7f73175 100644 --- a/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h +++ b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h @@ -24,7 +24,9 @@ #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H #ifndef __ASSEMBLER__ -extern void __iomem *prcm_mpu_base; +#include "prcm-common.h" + +extern struct omap_domain_base prcm_mpu_base; extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx); extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx); diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 233bc84fbc0e..94dc3565add8 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -16,7 +16,7 @@ #include "prcm-common.h" # ifndef __ASSEMBLER__ -extern void __iomem *prm_base; +extern struct omap_domain_base prm_base; extern u16 prm_features; extern void omap2_set_globals_prm(void __iomem *prm); int omap_prcm_init(void); diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h index f57e29b0e041..6775e10883fb 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h @@ -55,12 +55,12 @@ /* Power/reset management domain register get/set */ static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx) { - return readl_relaxed(prm_base + module + idx); + return readl_relaxed(prm_base.va + module + idx); } static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx) { - writel_relaxed(val, prm_base + module + idx); + writel_relaxed(val, prm_base.va + module + idx); } /* Read-modify-write a register in a PRM module. Caller must lock */ diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c index dcb5001d77da..d2c5bcabdbeb 100644 --- a/arch/arm/mach-omap2/prm33xx.c +++ b/arch/arm/mach-omap2/prm33xx.c @@ -30,13 +30,13 @@ /* Read a register in a PRM instance */ static u32 am33xx_prm_read_reg(s16 inst, u16 idx) { - return readl_relaxed(prm_base + inst + idx); + return readl_relaxed(prm_base.va + inst + idx); } /* Write into a register in a PRM instance */ static void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx) { - writel_relaxed(val, prm_base + inst + idx); + writel_relaxed(val, prm_base.va + inst + idx); } /* Read-modify-write a register in PRM. Caller must lock */ diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c index 718981bb80cd..50291a063aab 100644 --- a/arch/arm/mach-omap2/prm3xxx.c +++ b/arch/arm/mach-omap2/prm3xxx.c @@ -676,7 +676,7 @@ static struct prm_ll_data omap3xxx_prm_ll_data = { int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data) { omap2_clk_legacy_provider_init(TI_CLKM_PRM, - prm_base + OMAP3430_IVA2_MOD); + prm_base.va + OMAP3430_IVA2_MOD); if (omap3_has_io_wakeup()) prm_features |= PRM_HAS_IO_WAKEUP; diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index 30768003f854..090a13173589 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -91,13 +91,13 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = { /* Read a register in a CM/PRM instance in the PRM module */ static u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) { - return readl_relaxed(prm_base + inst + reg); + return readl_relaxed(prm_base.va + inst + reg); } /* Write into a register in a CM/PRM instance in the PRM module */ static void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) { - writel_relaxed(val, prm_base + inst + reg); + writel_relaxed(val, prm_base.va + inst + reg); } /* Read-modify-write a register in a PRM module. Caller must lock */ diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index 2b138b65129a..ae13aa710c75 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -66,7 +66,7 @@ static struct irq_chip_generic **prcm_irq_chips; static struct omap_prcm_irq_setup *prcm_irq_setup; /* prm_base: base virtual address of the PRM IP block */ -void __iomem *prm_base; +struct omap_domain_base prm_base; u16 prm_features; @@ -325,7 +325,7 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup) for (i = 0; i < irq_setup->nr_regs; i++) { gc = irq_alloc_generic_chip("PRCM", 1, - irq_setup->base_irq + i * 32, prm_base, + irq_setup->base_irq + i * 32, prm_base.va, handle_level_irq); if (!gc) { @@ -364,7 +364,7 @@ err: */ void __init omap2_set_globals_prm(void __iomem *prm) { - prm_base = prm; + prm_base.va = prm; } /** @@ -755,19 +755,22 @@ int __init omap2_prm_base_init(void) struct device_node *np; const struct of_device_id *match; struct omap_prcm_init_data *data; - void __iomem *mem; + struct resource res; + int ret; for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) { data = (struct omap_prcm_init_data *)match->data; - mem = of_iomap(np, 0); - if (!mem) - return -ENOMEM; + ret = of_address_to_resource(np, 0, &res); + if (ret) + return ret; - if (data->index == TI_CLKM_PRM) - prm_base = mem + data->offset; + data->mem = ioremap(res.start, resource_size(&res)); - data->mem = mem; + if (data->index == TI_CLKM_PRM) { + prm_base.va = data->mem + data->offset; + prm_base.pa = res.start + data->offset; + } data->np = np; diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c index d0b15dbafa2e..48b8127b4e99 100644 --- a/arch/arm/mach-omap2/prminst44xx.c +++ b/arch/arm/mach-omap2/prminst44xx.c @@ -29,7 +29,7 @@ #include "prcm_mpu44xx.h" #include "soc.h" -static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS]; +static struct omap_domain_base _prm_bases[OMAP4_MAX_PRCM_PARTITIONS]; static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN; @@ -41,8 +41,10 @@ static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN; */ void omap_prm_base_init(void) { - _prm_bases[OMAP4430_PRM_PARTITION] = prm_base; - _prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base; + memcpy(&_prm_bases[OMAP4430_PRM_PARTITION], &prm_base, + sizeof(prm_base)); + memcpy(&_prm_bases[OMAP4430_PRCM_MPU_PARTITION], &prcm_mpu_base, + sizeof(prcm_mpu_base)); } s32 omap4_prmst_get_prm_dev_inst(void) @@ -60,8 +62,8 @@ u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx) { BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || part == OMAP4430_INVALID_PRCM_PARTITION || - !_prm_bases[part]); - return readl_relaxed(_prm_bases[part] + inst + idx); + !_prm_bases[part].va); + return readl_relaxed(_prm_bases[part].va + inst + idx); } /* Write into a register in a PRM instance */ @@ -69,8 +71,8 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) { BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || part == OMAP4430_INVALID_PRCM_PARTITION || - !_prm_bases[part]); - writel_relaxed(val, _prm_bases[part] + inst + idx); + !_prm_bases[part].va); + writel_relaxed(val, _prm_bases[part].va + inst + idx); } /* Read-modify-write a register in PRM. Caller must lock */ -- cgit v1.2.3 From 0bf76e00e5d8410a77b07b32ac9afea61d1e0ecd Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 31 May 2017 18:00:01 +0300 Subject: ARM: omap2+: clockdomain: add clkdm_xlate_address This new function can be used to get the physical address of a clockdomain. Required for mapping the clkctrl clocks under hwmod without modification to DT data. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clockdomain.c | 8 ++++++++ arch/arm/mach-omap2/clockdomain.h | 2 ++ 2 files changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index b79b1ca9aee9..518926410b62 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -1224,6 +1224,14 @@ ccd_exit: return 0; } +u32 clkdm_xlate_address(struct clockdomain *clkdm) +{ + if (arch_clkdm->clkdm_xlate_address) + return arch_clkdm->clkdm_xlate_address(clkdm); + + return 0; +} + /** * clkdm_hwmod_enable - add an enabled downstream hwmod to this clkdm * @clkdm: struct clockdomain * diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 24667a5a9dc0..827f01e2d0af 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -175,6 +175,7 @@ struct clkdm_ops { void (*clkdm_deny_idle)(struct clockdomain *clkdm); int (*clkdm_clk_enable)(struct clockdomain *clkdm); int (*clkdm_clk_disable)(struct clockdomain *clkdm); + u32 (*clkdm_xlate_address)(struct clockdomain *clkdm); }; int clkdm_register_platform_funcs(struct clkdm_ops *co); @@ -213,6 +214,7 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh); int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh); +u32 clkdm_xlate_address(struct clockdomain *clkdm); extern void __init omap242x_clockdomains_init(void); extern void __init omap243x_clockdomains_init(void); -- cgit v1.2.3 From 308b4e381b5849c190ca4a93388c9ccfbc525e3b Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 31 May 2017 18:00:02 +0300 Subject: ARM: OMAP4: cminst: add support for clkdm_xlate_address This function gets the physical base address of a clockdomain. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/cminst44xx.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c index cfa10a31b953..8774e983bea1 100644 --- a/arch/arm/mach-omap2/cminst44xx.c +++ b/arch/arm/mach-omap2/cminst44xx.c @@ -476,6 +476,14 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm) return 0; } +static u32 omap4_clkdm_xlate_address(struct clockdomain *clkdm) +{ + u32 addr = _cm_bases[clkdm->prcm_partition].pa + clkdm->cm_inst + + clkdm->clkdm_offs; + + return addr; +} + struct clkdm_ops omap4_clkdm_operations = { .clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep, .clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep, @@ -491,6 +499,7 @@ struct clkdm_ops omap4_clkdm_operations = { .clkdm_deny_idle = omap4_clkdm_deny_idle, .clkdm_clk_enable = omap4_clkdm_clk_enable, .clkdm_clk_disable = omap4_clkdm_clk_disable, + .clkdm_xlate_address = omap4_clkdm_xlate_address, }; struct clkdm_ops am43xx_clkdm_operations = { @@ -500,6 +509,7 @@ struct clkdm_ops am43xx_clkdm_operations = { .clkdm_deny_idle = omap4_clkdm_deny_idle, .clkdm_clk_enable = omap4_clkdm_clk_enable, .clkdm_clk_disable = omap4_clkdm_clk_disable, + .clkdm_xlate_address = omap4_clkdm_xlate_address, }; static struct cm_ll_data omap4xxx_cm_ll_data = { -- cgit v1.2.3 From 70f05be3213393f20f01e4d59625df7ee49fe32f Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 31 May 2017 18:00:03 +0300 Subject: ARM: OMAP2+: hwmod: populate clkctrl clocks for hwmods if available If clkctrl clocks are available on a device, populate these automatically to replace hwmod main_clk info. First, the patch parses all "ti,clkctrl" compatible nodes and maps these against existing clockdomain data. Once done, individual hwmod init routines can search for a clkctrl clock handle based on the clockdomain info and the created mapping. This patch also drops the obsolete "_mod_ck" search as the implementation required for this was not accepted usptream. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod.c | 145 +++++++++++++++++++++++++++++++++++---- 1 file changed, 130 insertions(+), 15 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 8bcea0d83fa0..e1107670acb6 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -141,6 +141,7 @@ #include #include #include +#include #include @@ -181,6 +182,24 @@ */ #define MOD_CLK_MAX_NAME_LEN 32 +/** + * struct clkctrl_provider - clkctrl provider mapping data + * @addr: base address for the provider + * @offset: base offset for the provider + * @clkdm: base clockdomain for provider + * @node: device node associated with the provider + * @link: list link + */ +struct clkctrl_provider { + u32 addr; + u16 offset; + struct clockdomain *clkdm; + struct device_node *node; + struct list_head link; +}; + +static LIST_HEAD(clkctrl_providers); + /** * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations * @enable_module: function to enable a module (via MODULEMODE) @@ -204,6 +223,8 @@ struct omap_hwmod_soc_ops { void (*update_context_lost)(struct omap_hwmod *oh); int (*get_context_lost)(struct omap_hwmod *oh); int (*disable_direct_prcm)(struct omap_hwmod *oh); + u32 (*xlate_clkctrl)(struct omap_hwmod *oh, + struct clkctrl_provider *provider); }; /* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */ @@ -690,6 +711,103 @@ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) return clkdm_del_sleepdep(clkdm, init_clkdm); } +static const struct of_device_id ti_clkctrl_match_table[] __initconst = { + { .compatible = "ti,clkctrl" }, + { } +}; + +static int _match_clkdm(struct clockdomain *clkdm, void *user) +{ + struct clkctrl_provider *provider = user; + + if (clkdm_xlate_address(clkdm) == provider->addr) { + pr_debug("%s: Matched clkdm %s for addr %x (%s)\n", __func__, + clkdm->name, provider->addr, + provider->node->parent->name); + provider->clkdm = clkdm; + + return -1; + } + + return 0; +} + +static int _setup_clkctrl_provider(struct device_node *np) +{ + const __be32 *addrp; + struct clkctrl_provider *provider; + + provider = memblock_virt_alloc(sizeof(*provider), 0); + if (!provider) + return -ENOMEM; + + addrp = of_get_address(np, 0, NULL, NULL); + provider->addr = (u32)of_translate_address(np, addrp); + provider->offset = provider->addr & 0xff; + provider->addr &= ~0xff; + provider->node = np; + + clkdm_for_each(_match_clkdm, provider); + + if (!provider->clkdm) { + pr_err("%s: nothing matched for node %s (%x)\n", + __func__, np->parent->name, provider->addr); + memblock_free_early(__pa(provider), sizeof(*provider)); + return -EINVAL; + } + + list_add(&provider->link, &clkctrl_providers); + + return 0; +} + +static int _init_clkctrl_providers(void) +{ + struct device_node *np; + int ret = 0; + + for_each_matching_node(np, ti_clkctrl_match_table) { + ret = _setup_clkctrl_provider(np); + if (ret) + break; + } + + return ret; +} + +static u32 _omap4_xlate_clkctrl(struct omap_hwmod *oh, + struct clkctrl_provider *provider) +{ + return oh->prcm.omap4.clkctrl_offs - + provider->offset - provider->clkdm->clkdm_offs; +} + +static struct clk *_lookup_clkctrl_clk(struct omap_hwmod *oh) +{ + struct clkctrl_provider *provider; + struct clk *clk; + + if (!soc_ops.xlate_clkctrl) + return NULL; + + list_for_each_entry(provider, &clkctrl_providers, link) { + if (provider->clkdm == oh->clkdm) { + struct of_phandle_args clkspec; + + clkspec.np = provider->node; + clkspec.args_count = 2; + clkspec.args[0] = soc_ops.xlate_clkctrl(oh, provider); + clkspec.args[1] = 0; + + clk = of_clk_get_from_provider(&clkspec); + + return clk; + } + } + + return NULL; +} + /** * _init_main_clk - get a struct clk * for the the hwmod's main functional clk * @oh: struct omap_hwmod * @@ -701,22 +819,16 @@ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) static int _init_main_clk(struct omap_hwmod *oh) { int ret = 0; - char name[MOD_CLK_MAX_NAME_LEN]; - struct clk *clk; - static const char modck[] = "_mod_ck"; + struct clk *clk = NULL; - if (strlen(oh->name) >= MOD_CLK_MAX_NAME_LEN - strlen(modck)) - pr_warn("%s: warning: cropping name for %s\n", __func__, - oh->name); - - strlcpy(name, oh->name, MOD_CLK_MAX_NAME_LEN - strlen(modck)); - strlcat(name, modck, MOD_CLK_MAX_NAME_LEN); + clk = _lookup_clkctrl_clk(oh); - clk = clk_get(NULL, name); - if (!IS_ERR(clk)) { + if (!IS_ERR_OR_NULL(clk)) { + pr_debug("%s: mapped main_clk %s for %s\n", __func__, + __clk_get_name(clk), oh->name); + oh->main_clk = __clk_get_name(clk); oh->_clk = clk; soc_ops.disable_direct_prcm(oh); - oh->main_clk = kstrdup(name, GFP_KERNEL); } else { if (!oh->main_clk) return 0; @@ -1482,13 +1594,13 @@ static int _init_clkdm(struct omap_hwmod *oh) * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as * well the clockdomain. * @oh: struct omap_hwmod * - * @data: not used; pass NULL + * @np: device_node mapped to this hwmod * * Called by omap_hwmod_setup_*() (after omap2_clk_init()). * Resolves all clock names embedded in the hwmod. Returns 0 on * success, or a negative error code on failure. */ -static int _init_clocks(struct omap_hwmod *oh, void *data) +static int _init_clocks(struct omap_hwmod *oh, struct device_node *np) { int ret = 0; @@ -2360,7 +2472,7 @@ static int __init _init(struct omap_hwmod *oh, void *data) return 0; } - r = _init_clocks(oh, NULL); + r = _init_clocks(oh, np); if (r < 0) { WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name); return -EINVAL; @@ -3722,6 +3834,7 @@ void __init omap_hwmod_init(void) soc_ops.update_context_lost = _omap4_update_context_lost; soc_ops.get_context_lost = _omap4_get_context_lost; soc_ops.disable_direct_prcm = _omap4_disable_direct_prcm; + soc_ops.xlate_clkctrl = _omap4_xlate_clkctrl; } else if (cpu_is_ti814x() || cpu_is_ti816x() || soc_is_am33xx() || soc_is_am43xx()) { soc_ops.enable_module = _omap4_enable_module; @@ -3736,6 +3849,8 @@ void __init omap_hwmod_init(void) WARN(1, "omap_hwmod: unknown SoC type\n"); } + _init_clkctrl_providers(); + inited = true; } -- cgit v1.2.3 From 2277795eb8e384dbfcee43b0e74dd3bc1129b4f8 Mon Sep 17 00:00:00 2001 From: Marek Belisko Date: Sun, 21 May 2017 12:38:17 +0200 Subject: ARM: dts: twl4030: Add missing madc reference for bci subnode The twl4030_charger driver expects an iio channel to detect the presence of an AC charger by looking at VAC (madc channel 11). This definition is missing in the device tree. Signed-off-by: Marek Belisko Signed-off-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/twl4030.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi index 36ae9160b558..16533b62b0a2 100644 --- a/arch/arm/boot/dts/twl4030.dtsi +++ b/arch/arm/boot/dts/twl4030.dtsi @@ -23,6 +23,8 @@ compatible = "ti,twl4030-bci"; interrupts = <9>, <2>; bci3v1-supply = <&vusb3v1>; + io-channels = <&twl_madc 11>; + io-channel-names = "vac"; }; watchdog { -- cgit v1.2.3 From accc55d9baebee484d04ac198b91fc6568a242e9 Mon Sep 17 00:00:00 2001 From: Robert Nelson Date: Tue, 30 May 2017 11:20:23 -0500 Subject: ARM: dts: Add am335x-boneblue BeagleBone Blue is robotics-oriented version of the BeagleBone Black (BBB). This board can be indentified by the BLAx value after A335BNLT (BBB) in the at24 eeprom: BLAx [aa 55 33 ee 41 33 33 35 42 4e 4c 54 42 4c 41 30 |.U3.A335BNLTBLA2|] http://beagleboard.org/blue https://github.com/beagleboard/beaglebone-blue firmware: https://github.com/beagleboard/beaglebone-black-wireless/tree/master/firmware wl18xx mac address: /proc/device-tree/ocp/ethernet@4a100000/slave@4a100200/mac-address Signed-off-by: Robert Nelson CC: Jason Kridner CC: Drew Fustini Acked-by: Jason Kridner Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/am335x-boneblue.dts | 460 ++++++++++++++++++++++++++++++++++ 2 files changed, 461 insertions(+) create mode 100644 arch/arm/boot/dts/am335x-boneblue.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9c5e1d944d1c..663b1132c5c4 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -603,6 +603,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-bone.dtb \ am335x-boneblack.dtb \ am335x-boneblack-wireless.dtb \ + am335x-boneblue.dtb \ am335x-bonegreen.dtb \ am335x-bonegreen-wireless.dtb \ am335x-chiliboard.dtb \ diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts new file mode 100644 index 000000000000..cdc1b2be792f --- /dev/null +++ b/arch/arm/boot/dts/am335x-boneblue.dts @@ -0,0 +1,460 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include + +/ { + model = "TI AM335x BeagleBone Blue"; + compatible = "ti,am335x-bone-blue", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + chosen { + stdout-path = &uart0; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; + + compatible = "gpio-leds"; + + usr_0_led { + label = "beaglebone:green:usr0"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + usr_1_led { + label = "beaglebone:green:usr1"; + gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + usr_2_led { + label = "beaglebone:green:usr2"; + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + usr_3_led { + label = "beaglebone:green:usr3"; + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + wifi_led { + label = "wifi"; + gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "phy0assoc"; + }; + + red_led { + label = "red"; + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + green_led { + label = "green"; + gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + batt_1_led { + label = "bat25"; + gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + batt_2_led { + label = "bat50"; + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + batt_3_led { + label = "bat75"; + gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + batt_4_led { + label = "bat100"; + gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + vmmcsd_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + wlan_en_reg: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us= <70000>; + + /* WL_EN */ + gpio = <&gpio3 9 0>; + enable-active-high; + }; +}; + +&am33xx_pinmux { + user_leds_s0: user_leds_s0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ + AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ + AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ + AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ + AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] - WIFI_LED */ + AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE7) /* (R7) gpmc_advn_ale.gpio2[2] - P8.7, LED_RED, GP1_PIN_5 */ + AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE7) /* (T7) gpmc_oen_ren.gpio2[3] - P8.8, LED_GREEN, GP1_PIN_6 */ + AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE7) /* (U12) gpmc_ad11.gpio0[27] - P8.17, BATT_LED_1 */ + AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE7) /* (T5) lcd_data15.gpio0[11] - P8.32, BATT_LED_2 */ + AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE7) /* (V6) gpmc_csn0.gpio1[29] - P8.26, BATT_LED_3 */ + AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) /* (T11) gpmc_ad10.gpio0[26] - P8.14, BATT_LED_4 */ + + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */ + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */ + >; + }; + + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ + AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* (E15) uart0_rxd.uart0_rxd */ + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (E16) uart0_txd.uart0_txd */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* (U9) gpmc_csn1.mmc1_clk */ + AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* (V9) gpmc_csn2.mmc1_cmd */ + AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* (U7) gpmc_ad0.mmc1_dat0 */ + AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* (V7) gpmc_ad1.mmc1_dat1 */ + AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* (R8) gpmc_ad2.mmc1_dat2 */ + AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* (T8) gpmc_ad3.mmc1_dat3 */ + AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* (U8) gpmc_ad4.mmc1_dat4 */ + AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* (V8) gpmc_ad5.mmc1_dat5 */ + AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* (R9) gpmc_ad6.mmc1_dat6 */ + AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* (T9) gpmc_ad7.mmc1_dat7 */ + >; + }; + + mmc3_pins: pinmux_mmc3_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE6) /* (L15) gmii1_rxd1.mmc2_clk */ + AM33XX_IOPAD(0x914, PIN_INPUT_PULLUP | MUX_MODE6) /* (J16) gmii1_txen.mmc2_cmd */ + AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE5) /* (J17) gmii1_rxdv.mmc2_dat0 */ + AM33XX_IOPAD(0x91c, PIN_INPUT_PULLUP | MUX_MODE5) /* (J18) gmii1_txd3.mmc2_dat1 */ + AM33XX_IOPAD(0x920, PIN_INPUT_PULLUP | MUX_MODE5) /* (K15) gmii1_txd2.mmc2_dat2 */ + AM33XX_IOPAD(0x908, PIN_INPUT_PULLUP | MUX_MODE5) /* (H16) gmii1_col.mmc2_dat3 */ + >; + }; + + bt_pins: pinmux_bt_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLUP | MUX_MODE7) /* (K17) gmii1_txd0.gpio0[28] - BT_EN */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ + AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ + AM33XX_IOPAD(0x948, PIN_INPUT | MUX_MODE3) /* (M17) mdio_data.uart3_ctsn */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* (M18) mdio_clk.uart3_rtsn */ + >; + }; + + wl18xx_pins: pinmux_wl18xx_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] - WL_EN */ + AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (H18) rmii1_refclk.gpio0[29] - WL_IRQ */ + AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLUP | MUX_MODE7) /* (L18) gmii1_rxclk.gpio3[10] - LS_BUF_EN */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "peripheral"; + interrupts-extended = <&intc 18 &tps 0>; + interrupt-names = "mc", "vbus"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&cppi41dma { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; + + baseboard_eeprom: baseboard_eeprom@50 { + compatible = "at,24c256"; + reg = <0x50>; + + #address-cells = <1>; + #size-cells = <1>; + baseboard_data: baseboard_data@0 { + reg = <0 0x100>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + status = "okay"; + clock-frequency = <400000>; + + mpu9250@68 { + compatible = "invensense,mpu9250"; + reg = <0x68>; + interrupt-parent = <&gpio3>; + interrupts = <21 GPIO_ACTIVE_LOW>; + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + ax8975@c { + compatible = "ak,ak8975"; + reg = <0x0c>; + }; + }; + }; + + pressure@76 { + compatible = "bosch,bmp280"; + reg = <0x76>; + }; +}; + +/include/ "tps65217.dtsi" + +&tps { + interrupts = <7>; /* NMI */ + interrupt-parent = <&intc>; + + charger { + interrupts = <0>, <1>; + interrupt-names = "USB", "AC"; + status = "okay"; + }; + + pwrbutton { + interrupts = <2>; + status = "okay"; + }; + + regulators { + dcdc1_reg: regulator@0 { + regulator-name = "vdds_dpr"; + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1351500>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + regulator-name = "vio,vrtc,vdds"; + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + regulator-name = "vdd_3v3aux"; + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + regulator-name = "vdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + regulator-name = "vdd_3v3a"; + regulator-always-on; + }; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; +}; + +&mmc3 { + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; + dma-names = "tx", "rx"; + status = "okay"; + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + non-removable; + cap-power-off-card; + ti,needs-special-hs-handling; + keep-power-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins &wl18xx_pins>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio0>; + interrupts = <29 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&tscadc { + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins &bt_pins>; + status = "okay"; + + bluetooth { + compatible = "ti,wl1835-st"; + enable-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; +}; + +&aes { + status = "okay"; +}; + +&sham { + status = "okay"; +}; + +&rtc { + system-power-controller; + clocks = <&clk_32768_ck>, <&clkdiv32k_ick>; + clock-names = "ext-clk", "int-clk"; +}; + +&gpio3 { + ls_buf_en { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "LS_BUF_EN"; + }; +}; -- cgit v1.2.3 From d132a000887b47e2d8ba711224d19bd58727abe2 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Fri, 2 Jun 2017 14:54:01 +0530 Subject: ARM: dts: AM43XX: Remove min and max voltage values for dcdc3 dcdc3 supplies to DDR on AM43x series. When we set both min and max values to the same value. The regulator framework sets that particular voltage. This is bad as we are changing the ddr voltage when executing from ddr. Hence remove the min and max values. The ddr supply voltage shall be set from bootloader when not executing from ddr and not while executing from kernel. The previous discussion can be found here: http://www.spinics.net/lists/devicetree/msg56399.html Signed-off-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 2 -- arch/arm/boot/dts/am437x-sk-evm.dts | 2 -- arch/arm/boot/dts/am43x-epos-evm.dts | 2 -- 3 files changed, 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 397e98b7e246..29a538ecd405 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -549,8 +549,6 @@ dcdc3: regulator-dcdc3 { regulator-name = "vdcdc3"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; regulator-state-mem { diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index a62e1583da04..2c6bf0684f50 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -451,8 +451,6 @@ dcdc3: regulator-dcdc3 { regulator-name = "vdds_ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; regulator-state-mem { diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index f6648ab10d29..54f40f370011 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -442,8 +442,6 @@ dcdc3: regulator-dcdc3 { regulator-name = "vdcdc3"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; -- cgit v1.2.3 From 7ff64afbc73c32171d9e08aa5444c68a654bb9d0 Mon Sep 17 00:00:00 2001 From: Robert Nelson Date: Mon, 5 Jun 2017 10:36:21 -0500 Subject: ARM: dts: bonegreen-wireless: add WL1835 Bluetooth device node This adds the serial slave device for the WL1835 Bluetooth interface. Signed-off-by: Robert Nelson CC: Ricardo Salveti CC: Tony Lindgren CC: Jason Kridner Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-bonegreen-wireless.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts index 9d1a0fd555f3..57731f0daf10 100644 --- a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts +++ b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts @@ -97,6 +97,11 @@ pinctrl-names = "default"; pinctrl-0 = <&uart3_pins &bt_pins>; status = "okay"; + + bluetooth { + compatible = "ti,wl1835-st"; + enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + }; }; &gpio1 { -- cgit v1.2.3 From de09eb52a1cceb6f80464a008c67c7bebb242314 Mon Sep 17 00:00:00 2001 From: Suniel Mahesh Date: Mon, 5 Jun 2017 23:47:16 +0530 Subject: arm: dts: am33xx: Remove redundant interrupt-parent property Interrupt-parent property is defined in the root node as "interrupt-parent = <&intc>". This interrupt-parent value becomes the default for the system, so removed redundant "interrupt-parent" property from mmc, mac, lcdc and tscadc nodes. Signed-off-by: Suniel Mahesh Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx.dtsi | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index bdacb3dd689c..7d7ca054c557 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -431,7 +431,6 @@ &edma_xbar 25 0 0>; dma-names = "tx", "rx"; interrupts = <64>; - interrupt-parent = <&intc>; reg = <0x48060000 0x1000>; status = "disabled"; }; @@ -444,7 +443,6 @@ &edma 3 0>; dma-names = "tx", "rx"; interrupts = <28>; - interrupt-parent = <&intc>; reg = <0x481d8000 0x1000>; status = "disabled"; }; @@ -454,7 +452,6 @@ ti,hwmods = "mmc3"; ti,needs-special-reset; interrupts = <29>; - interrupt-parent = <&intc>; reg = <0x47810000 0x1000>; status = "disabled"; }; @@ -853,7 +850,6 @@ 0x4a101200 0x100>; #address-cells = <1>; #size-cells = <1>; - interrupt-parent = <&intc>; /* * c0_rx_thresh_pend * c0_rx_pend @@ -908,7 +904,6 @@ lcdc: lcdc@4830e000 { compatible = "ti,am33xx-tilcdc"; reg = <0x4830e000 0x1000>; - interrupt-parent = <&intc>; interrupts = <36>; ti,hwmods = "lcdc"; status = "disabled"; @@ -917,7 +912,6 @@ tscadc: tscadc@44e0d000 { compatible = "ti,am3359-tscadc"; reg = <0x44e0d000 0x1000>; - interrupt-parent = <&intc>; interrupts = <16>; ti,hwmods = "adc_tsc"; status = "disabled"; -- cgit v1.2.3 From 65878b126c8f2d761273241cf778b1c6aa50c500 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Tue, 30 May 2017 18:21:25 -0700 Subject: ARM: dts: da850-evm: fix tca6416 for use with GPIO hogs In order GPIOS from this controller to be used with the "gpio-hogs" property, the tca6416 node has to properly labeled as a gpio-controller, and use #gpio-cells. With that, the SEL_A, SEL_B, SEL_C lines that are used to select VPIF input can be configured using GPIO hogs. As an example, example, the configuration below selects the analog video input on the da850-evm UI board: &tca6416 { status = "okay"; sel_a { gpio-hog; gpios = <7 GPIO_ACTIVE_HIGH>; output-high; line-name = "ADC_ENn"; }; sel_b { gpio-hog; gpios = <6 GPIO_ACTIVE_HIGH>; output-high; line-name = "CAMERA_ENn"; }; sel_c { gpio-hog; gpios = <5 GPIO_ACTIVE_HIGH>; output-low; line-name = "VIDEO_IN_ENn"; }; }; Signed-off-by: Kevin Hilman Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850-evm.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index 8d244cd76c36..a423e8ebfb37 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -82,6 +82,8 @@ tca6416: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; }; }; wdt: wdt@21000 { -- cgit v1.2.3 From 98d87eb5664b5a39d6dcb66639b6b7e536d71ffb Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 5 Jun 2017 17:00:32 +0800 Subject: ARM: sunxi: h3-h5: Convert R_CCU raw numbers to macros Now that the R_CCU device tree binding headers have been merged, we can convert the raw number references in the device trees to use the defined macros. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 1aeeacb3a884..a7e858a82c90 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -41,8 +41,10 @@ */ #include +#include #include #include +#include / { interrupt-parent = <&gic>; @@ -573,9 +575,9 @@ ir: ir@01f02000 { compatible = "allwinner,sun5i-a13-ir"; - clocks = <&r_ccu 4>, <&r_ccu 11>; + clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; clock-names = "apb", "ir"; - resets = <&r_ccu 0>; + resets = <&r_ccu RST_APB0_IR>; interrupts = ; reg = <0x01f02000 0x40>; status = "disabled"; @@ -585,7 +587,7 @@ compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = ; - clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; + clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; -- cgit v1.2.3 From d91d3daf5de90e0118227d8ddcb7bb4ff40c1b91 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Wed, 31 May 2017 09:18:37 +0200 Subject: arm: sun8i: sunxi-h3-h5: Add dt node for the syscon control module This patch add the dt node for the syscon register present on the Allwinner H3/H5 Only two register are present in this syscon and the only one useful is the one dedicated to EMAC clock.. Signed-off-by: Corentin Labbe Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index a7e858a82c90..61f729168c89 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -85,6 +85,12 @@ #size-cells = <1>; ranges; + syscon: syscon@1c00000 { + compatible = "allwinner,sun8i-h3-system-controller", + "syscon"; + reg = <0x01c00000 0x1000>; + }; + dma: dma-controller@01c02000 { compatible = "allwinner,sun8i-h3-dma"; reg = <0x01c02000 0x1000>; -- cgit v1.2.3 From 0eba511a3cac29d6338b22b5b727f40cf8d163df Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Wed, 31 May 2017 09:18:38 +0200 Subject: arm: sun8i: sunxi-h3-h5: add dwmac-sun8i ethernet driver The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000 speed. This patch enable the dwmac-sun8i on Allwinner H3/H5 SoC Device-tree. SoC H3/H5 have an internal PHY, so optionals syscon and ephy are set. Signed-off-by: Corentin Labbe Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 61f729168c89..1fc663bdfdda 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -287,6 +287,14 @@ interrupt-controller; #interrupt-cells = <3>; + emac_rgmii_pins: emac0 { + pins = "PD0", "PD1", "PD2", "PD3", "PD4", + "PD5", "PD7", "PD8", "PD9", "PD10", + "PD12", "PD13", "PD15", "PD16", "PD17"; + function = "emac"; + drive-strength = <40>; + }; + i2c0_pins: i2c0 { pins = "PA11", "PA12"; function = "i2c0"; @@ -383,6 +391,32 @@ clocks = <&osc24M>; }; + emac: ethernet@1c30000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + }; + spi0: spi@01c68000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c68000 0x1000>; -- cgit v1.2.3 From d342cb6f018a6967e52ff7701beac2ead15530cb Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Wed, 31 May 2017 09:18:39 +0200 Subject: arm: sun8i: orangepi-pc: Enable dwmac-sun8i The dwmac-sun8i hardware is present on the Orange PI PC. It uses the internal PHY. This patch create the needed emac node. Signed-off-by: Corentin Labbe Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts index f148111c326d..52e65755c51a 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts @@ -52,6 +52,7 @@ compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -109,6 +110,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; -- cgit v1.2.3 From 25b9c3f58d2917c3e3cb572f4af5b67d562143dd Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Wed, 31 May 2017 09:18:41 +0200 Subject: arm: sun8i: orangepi-one: Enable dwmac-sun8i The dwmac-sun8i hardware is present on the Orange PI One. It uses the internal PHY. This patch create the needed emac node. Signed-off-by: Corentin Labbe Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts index 5fea430e0eb1..6880268e8b87 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts @@ -52,6 +52,7 @@ compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -97,6 +98,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; -- cgit v1.2.3 From a9992f2dd1890112643a93d621ff5a4c97c55d53 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Wed, 31 May 2017 09:18:42 +0200 Subject: arm: sun8i: orangepi-2: Enable dwmac-sun8i The dwmac-sun8i hardware is present on the Orange PI 2. It uses the internal PHY. This patch create the needed emac node. Signed-off-by: Corentin Labbe Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index 5b6d14555b7c..cedd326b6089 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -54,6 +54,7 @@ aliases { serial0 = &uart0; /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet0 = &emac; ethernet1 = &rtl8189; }; @@ -108,6 +109,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; -- cgit v1.2.3 From 75ee680cbd2e4d0156b94f9fec50076361ab12f2 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Wed, 31 May 2017 09:18:43 +0200 Subject: arm: sun8i: orangepi-pc-plus: Set EMAC activity LEDs to active high On the Orange Pi PC Plus, the polarity of the LEDs on the RJ45 Ethernet port were changed from active low to active high. Signed-off-by: Chen-Yu Tsai Signed-off-by: Corentin Labbe Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts index 8b93f5c781a7..a10281b455f5 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts @@ -53,6 +53,11 @@ }; }; +&emac { + /* LEDs changed to active high on the plus */ + /delete-property/ allwinner,leds-active-low; +}; + &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins_a>; -- cgit v1.2.3 From 378af662f8d4a30ceddae1e5c5d1acb6da7f9796 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Wed, 31 May 2017 09:18:44 +0200 Subject: arm: sun8i: nanopi-neo: Enable dwmac-sun8i The dwmac-sun8i hardware is present on the NanoPi Neo. It uses the internal PHY. This patch create the needed emac node. Signed-off-by: Corentin Labbe Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts index 8d2cc6e9a03f..78f6c24952dd 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts @@ -46,3 +46,10 @@ model = "FriendlyARM NanoPi NEO"; compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; }; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; -- cgit v1.2.3 From 1dcd0095019aca7533eaeed9475d995a4eb30137 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Mon, 5 Jun 2017 21:21:26 +0200 Subject: ARM: sun8i: orangepi-plus: Enable dwmac-sun8i The dwmac-sun8i hardware is present on the Orange PI plus. It uses an external PHY rtl8211e via RGMII. This patch create the needed regulator, emac and phy nodes. Signed-off-by: Corentin Labbe Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 32 ++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts index 8c40ab7bfa72..331ed683ac62 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts @@ -47,6 +47,20 @@ model = "Xunlong Orange Pi Plus / Plus 2"; compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; + aliases { + ethernet0 = &emac; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; + }; + reg_usb3_vbus: usb3-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -64,6 +78,24 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + allwinner,leds-active-low; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_pins>; -- cgit v1.2.3 From 8c7ba536e70976e09b148b43be1299abf3cc1560 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Mon, 5 Jun 2017 21:21:27 +0200 Subject: ARM: sun8i: bananapi-m2-plus: Enable dwmac-sun8i The dwmac-sun8i hardware is present on the Banana Pi M2+ It uses an external PHY rtl8211e via RGMII. This patch create the needed regulator, emac and phy nodes. Signed-off-by: Corentin Labbe Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 29 +++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts index 52acbe111cad..fef652b883fb 100644 --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts @@ -52,6 +52,7 @@ compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; }; @@ -84,6 +85,16 @@ }; }; + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; @@ -100,12 +111,30 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + allwinner,leds-active-low; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; status = "okay"; }; +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; -- cgit v1.2.3 From 252006cf0da13e65151cd7e7d0d6bb14bc0ca815 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Wed, 31 May 2017 09:18:40 +0200 Subject: arm: sun8i: orangepi-zero: Enable dwmac-sun8i The dwmac-sun8i hardware is present on the Orange PI Zero. It uses the internal PHY. This patch create the needed emac node. Signed-off-by: Corentin Labbe Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts index 9e8b082c134f..dd3525a0f06a 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts @@ -57,6 +57,7 @@ aliases { serial0 = &uart0; /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet0 = &emac; ethernet1 = &xr819; }; @@ -103,6 +104,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>; -- cgit v1.2.3 From cc20028f68e760d6958e892aba1f9bafbce63e22 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 5 Jun 2017 13:22:20 -0300 Subject: ARM: dts: imx6: Fix PCI GPIO reset polarity The imx6 PCI driver ignores the GPIO polarity from 'reset-gpio' and considers that the PCI reset is active low, unless the property 'reset-gpio-active-high' is present. Fix the device tree description by explicitly passing the 'GPIO_ACTIVE_LOW' flag to the 'reset-gpio' property. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-ba16.dtsi | 2 +- arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 2 +- arch/arm/boot/dts/imx6q-novena.dts | 2 +- arch/arm/boot/dts/imx6qdl-apf6dev.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 2 +- arch/arm/boot/dts/imx6sx-nitrogen6sx.dts | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi index 14fa6b25dc45..5fcb0372d58b 100644 --- a/arch/arm/boot/dts/imx6q-ba16.dtsi +++ b/arch/arm/boot/dts/imx6q-ba16.dtsi @@ -321,7 +321,7 @@ &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; fsl,tx-swing-full = <103>; fsl,tx-swing-low = <103>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index 0c5b2c38214e..33eb7f180995 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -435,7 +435,7 @@ &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 8 0>; + reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts index c21db67349c4..d83cfb6ec598 100644 --- a/arch/arm/boot/dts/imx6q-novena.dts +++ b/arch/arm/boot/dts/imx6q-novena.dts @@ -446,7 +446,7 @@ &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie_novena>; - reset-gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi index 550e100e85fc..9cd2a7477ed7 100644 --- a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi @@ -232,7 +232,7 @@ &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio6 2 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio6 2 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi index ed6a89f724a5..1b1872873207 100644 --- a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi @@ -335,7 +335,7 @@ }; &pcie { - reset-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio2 16 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 6e5cb6a99550..d81b0078a100 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -374,7 +374,7 @@ &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 17 0>; + reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts index ac1989e5d5ad..c5578d1c1ee4 100644 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -296,7 +296,7 @@ &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio4 10 GPIO_ACTIVE_LOW>; status = "okay"; }; -- cgit v1.2.3 From b3ea575770c7eeb259c77b6861cd14d00eb309df Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Tue, 6 Jun 2017 20:50:42 +0300 Subject: ARM: imx: Add MXC_CPU_IMX6ULL and cpu_is_imx6ull Support for imx6ull is already present but it's based on of_machine_is_compatible("fsl,imx6ull") checks. Add it to the MXC_CPU_* enumeration as well. This also fixes /sys/devices/soc0/soc_id reading "Unknown". Signed-off-by: Leonard Crestez Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/cpu.c | 3 +++ arch/arm/mach-imx/mxc.h | 6 ++++++ 2 files changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index b3347d32349f..94906ed49392 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -131,6 +131,9 @@ struct device * __init imx_soc_device_init(void) case MXC_CPU_IMX6UL: soc_id = "i.MX6UL"; break; + case MXC_CPU_IMX6ULL: + soc_id = "i.MX6ULL"; + break; case MXC_CPU_IMX7D: soc_id = "i.MX7D"; break; diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h index 34f2ff62583c..e00d6260c3df 100644 --- a/arch/arm/mach-imx/mxc.h +++ b/arch/arm/mach-imx/mxc.h @@ -39,6 +39,7 @@ #define MXC_CPU_IMX6SX 0x62 #define MXC_CPU_IMX6Q 0x63 #define MXC_CPU_IMX6UL 0x64 +#define MXC_CPU_IMX6ULL 0x65 #define MXC_CPU_IMX7D 0x72 #define IMX_DDR_TYPE_LPDDR2 1 @@ -73,6 +74,11 @@ static inline bool cpu_is_imx6ul(void) return __mxc_cpu_type == MXC_CPU_IMX6UL; } +static inline bool cpu_is_imx6ull(void) +{ + return __mxc_cpu_type == MXC_CPU_IMX6ULL; +} + static inline bool cpu_is_imx6q(void) { return __mxc_cpu_type == MXC_CPU_IMX6Q; -- cgit v1.2.3 From bf5a01d7c50fb0c4e1c3d320d670bad252d50bcb Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Tue, 6 Jun 2017 20:50:43 +0300 Subject: ARM: imx6ull: Make suspend/resume work like on 6ul Suspend and resume on imx6ull is currenty not working because of some missed checks where behavior should match imx6ul. Signed-off-by: Leonard Crestez Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/pm-imx6.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c index e61b1d1027e1..ecdf071653d4 100644 --- a/arch/arm/mach-imx/pm-imx6.c +++ b/arch/arm/mach-imx/pm-imx6.c @@ -295,7 +295,8 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) val &= ~BM_CLPCR_SBYOS; if (cpu_is_imx6sl()) val |= BM_CLPCR_BYPASS_PMIC_READY; - if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul()) + if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || + cpu_is_imx6ull()) val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; else val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; @@ -312,7 +313,8 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) val |= BM_CLPCR_SBYOS; if (cpu_is_imx6sl() || cpu_is_imx6sx()) val |= BM_CLPCR_BYPASS_PMIC_READY; - if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul()) + if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || + cpu_is_imx6ull()) val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; else val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; -- cgit v1.2.3 From d27a30bbc8b0c84a4cc922b201f9e85e9a2de741 Mon Sep 17 00:00:00 2001 From: Markus Elfring Date: Thu, 1 Jun 2017 21:48:11 +0200 Subject: ARM: OMAP1: DMA: Improve a size determination in omap1_system_dma_init() Replace the specification of a data structure by a pointer dereference as the parameter for the operator "sizeof" to make the corresponding size determination a bit safer according to the Linux coding style convention. Signed-off-by: Markus Elfring Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c index c821c1d5610e..823dba3dc033 100644 --- a/arch/arm/mach-omap1/dma.c +++ b/arch/arm/mach-omap1/dma.c @@ -339,7 +339,7 @@ static int __init omap1_system_dma_init(void) goto exit_iounmap; } - d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL); + d = kzalloc(sizeof(*d), GFP_KERNEL); if (!d) { dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n", __func__, pdev->name); -- cgit v1.2.3 From 61ee221ee45bc10d9115ba6ce8862ee62289a98f Mon Sep 17 00:00:00 2001 From: Markus Elfring Date: Thu, 1 Jun 2017 21:54:36 +0200 Subject: ARM: OMAP1: DMA: Delete an error message for a failed memory allocation in omap1_system_dma_init() Omit an extra message for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Link: http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings-WSang_0.pdf Signed-off-by: Markus Elfring Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/dma.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c index 823dba3dc033..c545b4e01d53 100644 --- a/arch/arm/mach-omap1/dma.c +++ b/arch/arm/mach-omap1/dma.c @@ -341,8 +341,6 @@ static int __init omap1_system_dma_init(void) d = kzalloc(sizeof(*d), GFP_KERNEL); if (!d) { - dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n", - __func__, pdev->name); ret = -ENOMEM; goto exit_iounmap; } -- cgit v1.2.3 From 2abe5b343dc790cc577700b07ca8d10fed62ae0e Mon Sep 17 00:00:00 2001 From: Markus Elfring Date: Thu, 1 Jun 2017 22:00:21 +0200 Subject: ARM: OMAP1: DMA: Delete an unnecessary return statement in omap1_show_dma_caps() The script "checkpatch.pl" pointed information out like the following. WARNING: void function return statements are not generally useful Thus remove such a statement in the affected function. Signed-off-by: Markus Elfring Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/dma.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c index c545b4e01d53..52d7eda1adec 100644 --- a/arch/arm/mach-omap1/dma.c +++ b/arch/arm/mach-omap1/dma.c @@ -240,7 +240,6 @@ static void omap1_show_dma_caps(void) w |= 1 << 3; dma_write(w, GSCR, 0); } - return; } static unsigned configure_dma_errata(void) -- cgit v1.2.3 From a9e317c388d48da80fc266f06dc6298cbd790b8c Mon Sep 17 00:00:00 2001 From: Markus Elfring Date: Thu, 1 Jun 2017 22:04:29 +0200 Subject: ARM: OMAP1: Delete an error message for a failed memory allocation in omap1_dm_timer_init() Omit an extra message for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Link: http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings-WSang_0.pdf Signed-off-by: Markus Elfring Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/timer.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c index 06c5ba7574a5..637f8c9d9f10 100644 --- a/arch/arm/mach-omap1/timer.c +++ b/arch/arm/mach-omap1/timer.c @@ -134,8 +134,6 @@ static int __init omap1_dm_timer_init(void) pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); if (!pdata) { - dev_err(&pdev->dev, "%s: Failed to allocate pdata.\n", - __func__); ret = -ENOMEM; goto err_free_pdata; } -- cgit v1.2.3 From 764e4ef0a8871339eeddaf27ccc47aeeea28b974 Mon Sep 17 00:00:00 2001 From: Markus Elfring Date: Thu, 1 Jun 2017 22:17:03 +0200 Subject: ARM: OMAP1: Fix a typo in a comment line Adjust a line in this description for the software module. Signed-off-by: Markus Elfring Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c index 637f8c9d9f10..8fb1ec6fa999 100644 --- a/arch/arm/mach-omap1/timer.c +++ b/arch/arm/mach-omap1/timer.c @@ -3,7 +3,7 @@ * * Contains first level initialization routines which internally * generates timer device information and registers with linux - * device model. It also has low level function to chnage the timer + * device model. It also has a low level function to change the timer * input clock source. * * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -- cgit v1.2.3 From aac5e972d4c7bc728df605f5427d9c2458c34ea9 Mon Sep 17 00:00:00 2001 From: Garlic Tseng Date: Thu, 1 Jun 2017 13:42:10 +0800 Subject: arm: dts: mediatek: Add audio driver node for MT2701 Add audio driver node for mt2701 Signed-off-by: Garlic Tseng Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt2701-evb.dts | 65 ++++++++++++++++++++++++++ arch/arm/boot/dts/mt2701.dtsi | 98 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 163 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts index 98bf12c141cb..f48497354221 100644 --- a/arch/arm/boot/dts/mt2701-evb.dts +++ b/arch/arm/boot/dts/mt2701-evb.dts @@ -22,6 +22,40 @@ memory { reg = <0 0x80000000 0 0x40000000>; }; + + sound:sound { + compatible = "mediatek,mt2701-cs42448-machine"; + mediatek,platform = <&afe>; + /* CS42448 Machine name */ + audio-routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "AMIC", + "AIN1R", "AMIC", + "AIN2L", "Tuner In", + "AIN2R", "Tuner In", + "AIN3L", "Satellite Tuner In", + "AIN3R", "Satellite Tuner In", + "AIN3L", "AUX In", + "AIN3R", "AUX In"; + mediatek,audio-codec = <&cs42448>; + mediatek,audio-codec-bt-mrg = <&bt_sco_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&aud_pins_default>; + i2s1-in-sel-gpio1 = <&pio 53 0>; + i2s1-in-sel-gpio2 = <&pio 54 0>; + status = "okay"; + }; + + bt_sco_codec:bt_sco_codec { + compatible = "linux,bt-sco"; + }; }; &auxadc { @@ -44,6 +78,12 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins_a>; status = "okay"; + cs42448: cs42448@48 { + compatible = "cirrus,cs42448"; + reg = <0x48>; + clocks = <&topckgen CLK_TOP_AUD_I2S1_MCLK>; + clock-names = "mclk"; + }; }; &pio { @@ -81,6 +121,31 @@ }; }; + aud_pins_default: audiodefault { + pins_cmd_dat { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength = ; + bias-pull-down; + }; + }; + spi_pins_b: spi1@0 { pins_spi { pinmux = , diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 50a483ce5c47..f1efdc63656a 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -425,6 +425,104 @@ status = "disabled"; }; + afe: audio-controller@11220000 { + compatible = "mediatek,mt2701-audio"; + reg = <0 0x11220000 0 0x2000>, + <0 0x112a0000 0 0x20000>; + interrupts = ; + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; + + clocks = <&infracfg CLK_INFRA_AUDIO>, + <&topckgen CLK_TOP_AUD_MUX1_SEL>, + <&topckgen CLK_TOP_AUD_MUX2_SEL>, + <&topckgen CLK_TOP_AUD_MUX1_DIV>, + <&topckgen CLK_TOP_AUD_MUX2_DIV>, + <&topckgen CLK_TOP_AUD_48K_TIMING>, + <&topckgen CLK_TOP_AUD_44K_TIMING>, + <&topckgen CLK_TOP_AUDPLL_MUX_SEL>, + <&topckgen CLK_TOP_APLL_SEL>, + <&topckgen CLK_TOP_AUD1PLL_98M>, + <&topckgen CLK_TOP_AUD2PLL_90M>, + <&topckgen CLK_TOP_HADDS2PLL_98M>, + <&topckgen CLK_TOP_HADDS2PLL_294M>, + <&topckgen CLK_TOP_AUDPLL>, + <&topckgen CLK_TOP_AUDPLL_D4>, + <&topckgen CLK_TOP_AUDPLL_D8>, + <&topckgen CLK_TOP_AUDPLL_D16>, + <&topckgen CLK_TOP_AUDPLL_D24>, + <&topckgen CLK_TOP_AUDINTBUS_SEL>, + <&clk26m>, + <&topckgen CLK_TOP_SYSPLL1_D4>, + <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K5_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K6_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K5_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K6_SRC_DIV>, + <&topckgen CLK_TOP_AUD_I2S1_MCLK>, + <&topckgen CLK_TOP_AUD_I2S2_MCLK>, + <&topckgen CLK_TOP_AUD_I2S3_MCLK>, + <&topckgen CLK_TOP_AUD_I2S4_MCLK>, + <&topckgen CLK_TOP_AUD_I2S5_MCLK>, + <&topckgen CLK_TOP_AUD_I2S6_MCLK>, + <&topckgen CLK_TOP_ASM_M_SEL>, + <&topckgen CLK_TOP_ASM_H_SEL>, + <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_UNIVPLL2_D2>, + <&topckgen CLK_TOP_SYSPLL_D5>; + + clock-names = "infra_sys_audio_clk", + "top_audio_mux1_sel", + "top_audio_mux2_sel", + "top_audio_mux1_div", + "top_audio_mux2_div", + "top_audio_48k_timing", + "top_audio_44k_timing", + "top_audpll_mux_sel", + "top_apll_sel", + "top_aud1_pll_98M", + "top_aud2_pll_90M", + "top_hadds2_pll_98M", + "top_hadds2_pll_294M", + "top_audpll", + "top_audpll_d4", + "top_audpll_d8", + "top_audpll_d16", + "top_audpll_d24", + "top_audintbus_sel", + "clk_26m", + "top_syspll1_d4", + "top_aud_k1_src_sel", + "top_aud_k2_src_sel", + "top_aud_k3_src_sel", + "top_aud_k4_src_sel", + "top_aud_k5_src_sel", + "top_aud_k6_src_sel", + "top_aud_k1_src_div", + "top_aud_k2_src_div", + "top_aud_k3_src_div", + "top_aud_k4_src_div", + "top_aud_k5_src_div", + "top_aud_k6_src_div", + "top_aud_i2s1_mclk", + "top_aud_i2s2_mclk", + "top_aud_i2s3_mclk", + "top_aud_i2s4_mclk", + "top_aud_i2s5_mclk", + "top_aud_i2s6_mclk", + "top_asm_m_sel", + "top_asm_h_sel", + "top_univpll2_d4", + "top_univpll2_d2", + "top_syspll_d5"; + }; + mmsys: syscon@14000000 { compatible = "mediatek,mt2701-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; -- cgit v1.2.3 From f44848b6f7ca8b8cbc3d04be3eb476b1ec531681 Mon Sep 17 00:00:00 2001 From: Vikas Manocha Date: Wed, 7 Jun 2017 13:55:25 +0200 Subject: ARM: dts: stm32: add stm32f769I & stm32f746 discovery board support Stm32f769I & stm32f746 are MCUs of stm32f7 family. Here are the major specs of the two boards: stm32f769I discovery board: - Cortex-M7 core @216MHz - 2MB mcu internal flash - 512KB internal sram - 16MB sdram memory - 64MB qspi flash memory - 4 inch wvga LCD-TFT Display stm32f746 discovery board: - Cortex-M7 core @216MHz - 1MB mcu internal flash - 320KB internal sram - 8MB sdram memory - 16MB qspi flash memory - 4.3 inch 480x272 LCD-TFT display Signed-off-by: Vikas Manocha Signed-off-by: Alexandre TORGUE --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/stm32f746-disco.dts | 74 +++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/stm32f746.dtsi | 13 ++++++ arch/arm/boot/dts/stm32f769-disco.dts | 74 +++++++++++++++++++++++++++++++++++ 4 files changed, 163 insertions(+) create mode 100644 arch/arm/boot/dts/stm32f746-disco.dts create mode 100644 arch/arm/boot/dts/stm32f769-disco.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9c5e1d944d1c..828165479ab0 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -790,6 +790,8 @@ dtb-$(CONFIG_ARCH_STI) += \ dtb-$(CONFIG_ARCH_STM32)+= \ stm32f429-disco.dtb \ stm32f469-disco.dtb \ + stm32f746-disco.dtb \ + stm32f769-disco.dtb \ stm32429i-eval.dtb \ stm32746g-eval.dtb \ stm32h743i-eval.dtb diff --git a/arch/arm/boot/dts/stm32f746-disco.dts b/arch/arm/boot/dts/stm32f746-disco.dts new file mode 100644 index 000000000000..18f656074437 --- /dev/null +++ b/arch/arm/boot/dts/stm32f746-disco.dts @@ -0,0 +1,74 @@ +/* + * Copyright 2017 - Vikas MANOCHA + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "stm32f746.dtsi" +#include + +/ { + model = "STMicroelectronics STM32F746-DISCO board"; + compatible = "st,stm32f746-disco", "st,stm32f746"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0xC0000000 0x800000>; + }; + + aliases { + serial0 = &usart1; + }; + +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_b>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index c2765ce12e2e..449f727c3476 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -326,6 +326,19 @@ bias-disable; }; }; + + usart1_pins_b: usart1@1 { + pins1 { + pinmux = ; + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; + bias-disable; + }; + }; }; crc: crc@40023000 { diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts new file mode 100644 index 000000000000..166728aeb166 --- /dev/null +++ b/arch/arm/boot/dts/stm32f769-disco.dts @@ -0,0 +1,74 @@ +/* + * Copyright 2017 - Vikas MANOCHA + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "stm32f746.dtsi" +#include + +/ { + model = "STMicroelectronics STM32F769-DISCO board"; + compatible = "st,stm32f769-disco", "st,stm32f7"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0xC0000000 0x1000000>; + }; + + aliases { + serial0 = &usart1; + }; + +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; -- cgit v1.2.3 From bcb49099cfb464cdfeb0d4c04a2c53ae823dea0f Mon Sep 17 00:00:00 2001 From: Yannick Fertre Date: Wed, 7 Jun 2017 14:58:10 +0200 Subject: ARM: dts: stm32: Add ltdc support on stm32f429 MCU Add LTDC (Lcd-tft Display Controller) support. Signed-off-by: Yannick Fertre Signed-off-by: Alexandre TORGUE --- arch/arm/boot/dts/stm32f429.dtsi | 46 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index b2a2b5c38caa..a7b4b94dd66c 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -549,7 +549,17 @@ reg = <0x40007000 0x400>; }; - pin-controller { + ltdc: display-controller@40016800 { + compatible = "st,stm32-ltdc"; + reg = <0x40016800 0x200>; + interrupts = <88>, <89>; + resets = <&rcc STM32F4_APB2_RESET(LTDC)>; + clocks = <&rcc 1 CLK_LCD>; + clock-names = "lcd"; + status = "disabled"; + }; + + pinctrl: pin-controller { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32f429-pinctrl"; @@ -764,6 +774,40 @@ slew-rate = <3>; }; }; + + ltdc_pins: ltdc@0 { + pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + slew-rate = <2>; + }; + }; }; rcc: rcc@40023810 { -- cgit v1.2.3 From 85d95f785500786a707c50804a86615205c1b941 Mon Sep 17 00:00:00 2001 From: Yannick Fertre Date: Wed, 7 Jun 2017 15:20:53 +0200 Subject: ARM: dts: stm32: Enable ltdc & simple panel on stm32f429-Eval board Enable ltdc & enable am-480272h3tmqw-t01h panel. Signed-off-by: Yannick Fertre Signed-off-by: Alexandre TORGUE --- arch/arm/boot/dts/stm32429i-eval.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index b6331146aa02..a6a300b5799a 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -124,6 +124,16 @@ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>; clock-names = "main_clk"; }; + + panel_rgb: panel-rgb { + compatible = "ampire,am-480272h3tmqw-t01h"; + status = "okay"; + port { + panel_in_rgb: endpoint { + remote-endpoint = <<dc_out_rgb>; + }; + }; + }; }; &adc { @@ -147,6 +157,19 @@ status = "okay"; }; +<dc { + status = "okay"; + pinctrl-0 = <<dc_pins>; + pinctrl-names = "default"; + dma-ranges; + + port { + ltdc_out_rgb: endpoint { + remote-endpoint = <&panel_in_rgb>; + }; + }; +}; + &mac { status = "okay"; pinctrl-0 = <ðernet_mii>; -- cgit v1.2.3 From e1679f09210fc2ed762747588c49f3b8909b9067 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Thu, 1 Jun 2017 21:39:04 +0200 Subject: ARM: sun5i: add a cryptographic engine node Add a node for the cryptographic engine that can be found on sun5i SoCs. This cryptographic engine is compatible with the Allwinner cryptographic accelerator driver. Signed-off-by: Antoine Tenart Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 0e29f1d98a9e..98cc00341b00 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -356,6 +356,15 @@ status = "disabled"; }; + crypto: crypto-engine@01c15000 { + compatible = "allwinner,sun5i-a13-crypto", + "allwinner,sun4i-a10-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = <54>; + clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; + clock-names = "ahb", "mod"; + }; + spi2: spi@01c17000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c17000 0x1000>; -- cgit v1.2.3 From 9bea19aac3226872af247f4d37d673fd15431941 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Thu, 1 Jun 2017 21:39:05 +0200 Subject: ARM: dts: sunxi: add SoC specific compatibles for the crypto nodes Add SoC specific compatibles for all sunXi crypto nodes, in addition to the one already used (allwinner,sun4i-a10-crypto). Signed-off-by: Antoine Tenart Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 3 ++- arch/arm/boot/dts/sun7i-a20.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index d0cede5aaeb5..aebc3f9dc7b6 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -816,7 +816,8 @@ }; crypto: crypto-engine@01c15000 { - compatible = "allwinner,sun4i-a10-crypto"; + compatible = "allwinner,sun6i-a31-crypto", + "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = ; clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index c03b59aaec82..96bee776e145 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -1019,7 +1019,8 @@ }; crypto: crypto-engine@01c15000 { - compatible = "allwinner,sun4i-a10-crypto"; + compatible = "allwinner,sun7i-a20-crypto", + "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = ; clocks = <&ahb_gates 5>, <&ss_clk>; -- cgit v1.2.3 From 21b29920933086b34f4a58692a079e9914115019 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 24 May 2017 19:17:23 +0800 Subject: ARM: sun8i: v3s: add device nodes for DE2 display pipeline Allwinner V3s SoC features a "Display Engine 2.0" with only one mixer and only one TCON connected to this mixer, which have RGB LCD output. Add device nodes for this display pipeline. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-v3s.dtsi | 83 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index a49ebef53c91..3a06dc5b3746 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -61,6 +61,12 @@ }; }; + de: display-engine { + compatible = "allwinner,sun8i-v3s-display-engine"; + allwinner,pipelines = <&mixer0>; + status = "disabled"; + }; + timer { compatible = "arm,armv7-timer"; interrupts = , @@ -95,6 +101,83 @@ #size-cells = <1>; ranges; + display_clocks: clock@1000000 { + compatible = "allwinner,sun8i-v3s-de2-clk"; + reg = <0x01000000 0x100000>; + clocks = <&ccu CLK_DE>, + <&ccu CLK_BUS_DE>; + clock-names = "mod", + "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mixer0: mixer@1100000 { + compatible = "allwinner,sun8i-v3s-de2-mixer"; + reg = <0x01100000 0x100000>; + clocks = <&display_clocks 0>, + <&display_clocks 6>; + clock-names = "bus", + "mod"; + resets = <&display_clocks 0>; + assigned-clocks = <&display_clocks 6>; + assigned-clock-rates = <150000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mixer0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_mixer0>; + }; + }; + }; + }; + + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun8i-v3s-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON0>, + <&ccu CLK_TCON0>; + clock-names = "ahb", + "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + resets = <&ccu RST_BUS_TCON0>; + reset-names = "lcd"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + + mmc0: mmc@01c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; -- cgit v1.2.3 From e89960c5ae51eac6a663be20dcfc2a58de1416f5 Mon Sep 17 00:00:00 2001 From: Yannick Fertre Date: Thu, 6 Apr 2017 14:19:00 +0200 Subject: ARM: dts: stm32: Add watchdog support for STM32F429 SoC Add watchdog into DT for stm32f429 family. Signed-off-by: Yannick FERTRE Signed-off-by: Alexandre TORGUE --- arch/arm/boot/dts/stm32f429.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index a7b4b94dd66c..936db6b60f9d 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -65,7 +65,7 @@ clock-frequency = <32768>; }; - clk-lsi { + clk_lsi: clk-lsi { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32000>; @@ -307,6 +307,13 @@ status = "disabled"; }; + iwdg: watchdog@40003000 { + compatible = "st,stm32-iwdg"; + reg = <0x40003000 0x400>; + clocks = <&clk_lsi>; + status = "disabled"; + }; + usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; -- cgit v1.2.3 From 7bffbd2d4273d5e8108cac3265d50d8e31f9d6a3 Mon Sep 17 00:00:00 2001 From: Yannick Fertre Date: Wed, 7 Jun 2017 15:39:40 +0200 Subject: ARM: dts: stm32: Add watchdog support for STM32F429 eval board This patch adds watchdog support for STM32x9I-Eval board. Signed-off-by: Yannick Fertre Signed-off-by: Alexandre TORGUE --- arch/arm/boot/dts/stm32429i-eval.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index a6a300b5799a..2e78e4e4addd 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -157,6 +157,11 @@ status = "okay"; }; +&iwdg { + status = "okay"; + timeout-sec = <32>; +}; + <dc { status = "okay"; pinctrl-0 = <<dc_pins>; -- cgit v1.2.3 From 5489d5dbb497ca3c6301f33792bcca1c064de98e Mon Sep 17 00:00:00 2001 From: Alexandre TORGUE Date: Wed, 7 Jun 2017 16:41:36 +0200 Subject: ARM: dts: stm32: Set gpio controller as interrupt controller on F4 and F7 This patch set each gpio controller as a interrupt controller. User who wants to use gpio as interrupt will have choice to use either "gpiolib" interface or "common" interrupt interface. Acked-by: Linus Walleij Signed-off-by: Alexandre TORGUE --- arch/arm/boot/dts/stm32f429.dtsi | 22 ++++++++++++++++++++++ arch/arm/boot/dts/stm32f746.dtsi | 22 ++++++++++++++++++++++ 2 files changed, 44 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 936db6b60f9d..53f83511c717 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -578,6 +578,8 @@ gpioa: gpio@40020000 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x0 0x400>; clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>; st,bank-name = "GPIOA"; @@ -586,6 +588,8 @@ gpiob: gpio@40020400 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x400 0x400>; clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>; st,bank-name = "GPIOB"; @@ -594,6 +598,8 @@ gpioc: gpio@40020800 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x800 0x400>; clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>; st,bank-name = "GPIOC"; @@ -602,6 +608,8 @@ gpiod: gpio@40020c00 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0xc00 0x400>; clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>; st,bank-name = "GPIOD"; @@ -610,6 +618,8 @@ gpioe: gpio@40021000 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x1000 0x400>; clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>; st,bank-name = "GPIOE"; @@ -618,6 +628,8 @@ gpiof: gpio@40021400 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x1400 0x400>; clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>; st,bank-name = "GPIOF"; @@ -626,6 +638,8 @@ gpiog: gpio@40021800 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x1800 0x400>; clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>; st,bank-name = "GPIOG"; @@ -634,6 +648,8 @@ gpioh: gpio@40021c00 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x1c00 0x400>; clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>; st,bank-name = "GPIOH"; @@ -642,6 +658,8 @@ gpioi: gpio@40022000 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x2000 0x400>; clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>; st,bank-name = "GPIOI"; @@ -650,6 +668,8 @@ gpioj: gpio@40022400 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x2400 0x400>; clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>; st,bank-name = "GPIOJ"; @@ -658,6 +678,8 @@ gpiok: gpio@40022800 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x2800 0x400>; clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>; st,bank-name = "GPIOK"; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 449f727c3476..d6b1b56f340c 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -229,6 +229,8 @@ gpioa: gpio@40020000 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x0 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; st,bank-name = "GPIOA"; @@ -237,6 +239,8 @@ gpiob: gpio@40020400 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x400 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; st,bank-name = "GPIOB"; @@ -245,6 +249,8 @@ gpioc: gpio@40020800 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x800 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; st,bank-name = "GPIOC"; @@ -253,6 +259,8 @@ gpiod: gpio@40020c00 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0xc00 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; st,bank-name = "GPIOD"; @@ -261,6 +269,8 @@ gpioe: gpio@40021000 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x1000 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; st,bank-name = "GPIOE"; @@ -269,6 +279,8 @@ gpiof: gpio@40021400 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x1400 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; st,bank-name = "GPIOF"; @@ -277,6 +289,8 @@ gpiog: gpio@40021800 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x1800 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; st,bank-name = "GPIOG"; @@ -285,6 +299,8 @@ gpioh: gpio@40021c00 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x1c00 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; st,bank-name = "GPIOH"; @@ -293,6 +309,8 @@ gpioi: gpio@40022000 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x2000 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; st,bank-name = "GPIOI"; @@ -301,6 +319,8 @@ gpioj: gpio@40022400 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x2400 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; st,bank-name = "GPIOJ"; @@ -309,6 +329,8 @@ gpiok: gpio@40022800 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x2800 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; st,bank-name = "GPIOK"; -- cgit v1.2.3 From aa8f42f7a10f749f8226ce75e770b36caca53cc4 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Wed, 7 Jun 2017 16:50:21 +0200 Subject: ARM: dts: stm32: Add missing reset-cells node in stm32f746 rcc node must include reset-cells node. Signed-off-by: Lionel Debieve Signed-off-by: Alexandre TORGUE --- arch/arm/boot/dts/stm32f746.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index d6b1b56f340c..4506eb97a4ab 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -371,6 +371,7 @@ }; rcc: rcc@40023800 { + #reset-cells = <1>; #clock-cells = <2>; compatible = "st,stm32f746-rcc", "st,stm32-rcc"; reg = <0x40023800 0x400>; -- cgit v1.2.3 From ba7f0df0895a62fc021dcbc9a59ec75b84c039b8 Mon Sep 17 00:00:00 2001 From: Hugues Fruchet Date: Fri, 5 May 2017 17:31:00 +0200 Subject: ARM: dts: stm32: Enable DCMI support on STM32F429 MCU Enable DCMI camera interface on STM32F429 MCU. Signed-off-by: Hugues Fruchet Signed-off-by: Alexandre TORGUE --- arch/arm/boot/dts/stm32f429.dtsi | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 53f83511c717..9f2138c8a8cc 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -837,6 +837,29 @@ slew-rate = <2>; }; }; + + dcmi_pins: dcmi@0 { + pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; }; rcc: rcc@40023810 { @@ -915,6 +938,20 @@ status = "disabled"; }; + dcmi: dcmi@50050000 { + compatible = "st,stm32-dcmi"; + reg = <0x50050000 0x400>; + interrupts = <78>; + resets = <&rcc STM32F4_AHB2_RESET(DCMI)>; + clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&dcmi_pins>; + dmas = <&dma2 1 1 0x414 0x3>; + dma-names = "tx"; + status = "disabled"; + }; + rng: rng@50060800 { compatible = "st,stm32-rng"; reg = <0x50060800 0x400>; -- cgit v1.2.3 From e8e16b7b29e916704c37e4fbbb9b6436b0cca51a Mon Sep 17 00:00:00 2001 From: Hugues Fruchet Date: Fri, 5 May 2017 17:31:00 +0200 Subject: ARM: dts: stm32: Enable DCMI camera interface on STM32F429-EVAL board Enable DCMI camera interface on STM32F429-EVAL board. Signed-off-by: Hugues Fruchet Signed-off-by: Alexandre TORGUE --- arch/arm/boot/dts/stm32429i-eval.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 2e78e4e4addd..60c2cb68d109 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -151,6 +151,15 @@ clock-frequency = <25000000>; }; +&dcmi { + status = "okay"; + + port { + dcmi_0: endpoint { + }; + }; +}; + &i2c1 { pinctrl-0 = <&i2c1_pins>; pinctrl-names = "default"; -- cgit v1.2.3 From c04b2e72af8d379b4d85f28e922bb1515d565891 Mon Sep 17 00:00:00 2001 From: Hugues Fruchet Date: Wed, 7 Jun 2017 17:39:11 +0200 Subject: ARM: dts: stm32: Enable STMPE1600 gpio expander of STM32F429-EVAL board Enable STMPE1600 gpio expander of STM32F429-EVAL board. Signed-off-by: Hugues Fruchet Signed-off-by: Alexandre TORGUE --- arch/arm/boot/dts/stm32429i-eval.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 60c2cb68d109..bc50f6be4d6a 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -164,6 +164,23 @@ pinctrl-0 = <&i2c1_pins>; pinctrl-names = "default"; status = "okay"; + + stmpe1600: stmpe1600@42 { + compatible = "st,stmpe1600"; + reg = <0x42>; + irq-gpio = <&gpioi 8 0>; + irq-trigger = <3>; + interrupts = <8 3>; + interrupt-parent = <&exti>; + interrupt-controller; + wakeup-source; + + stmpegpio: stmpe_gpio { + compatible = "st,stmpe-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; }; &iwdg { -- cgit v1.2.3 From 13dd385740627d5119c7918d46cecbe72e3b21c5 Mon Sep 17 00:00:00 2001 From: Hugues Fruchet Date: Fri, 5 May 2017 17:31:00 +0200 Subject: ARM: dts: stm32: Enable OV2640 camera support of STM32F429-EVAL board Enable OV2640 camera support of STM32F429-EVAL board. Signed-off-by: Hugues Fruchet Signed-off-by: Alexandre TORGUE --- arch/arm/boot/dts/stm32429i-eval.dts | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index bc50f6be4d6a..28f4a51a65e7 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -48,6 +48,7 @@ /dts-v1/; #include "stm32f429.dtsi" #include +#include / { model = "STMicroelectronics STM32429i-EVAL board"; @@ -66,6 +67,14 @@ serial0 = &usart1; }; + clocks { + clk_ext_camera: clk-ext-camera { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + soc { dma-ranges = <0xc0000000 0x0 0x10000000>; }; @@ -156,6 +165,11 @@ port { dcmi_0: endpoint { + remote-endpoint = <&ov2640_0>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; }; }; }; @@ -165,6 +179,22 @@ pinctrl-names = "default"; status = "okay"; + ov2640: camera@30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + resetb-gpios = <&stmpegpio 2 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&stmpegpio 0 GPIO_ACTIVE_LOW>; + clocks = <&clk_ext_camera>; + clock-names = "xvclk"; + status = "okay"; + + port { + ov2640_0: endpoint { + remote-endpoint = <&dcmi_0>; + }; + }; + }; + stmpe1600: stmpe1600@42 { compatible = "st,stmpe1600"; reg = <0x42>; -- cgit v1.2.3 From a68883f1e2fc03758feccf0b38ccb2dc06b4eec4 Mon Sep 17 00:00:00 2001 From: Cosar Dindar Date: Mon, 22 May 2017 16:34:00 +0200 Subject: ARM: dts: stm32: Add CRC support to stm32f429 Add CRC32 Crypto support to stm32f429. Signed-off-by: Cosar Dindar Signed-off-by: Alexandre TORGUE --- arch/arm/boot/dts/stm32f429.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 9f2138c8a8cc..a8113dc879cf 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -862,6 +862,13 @@ }; }; + crc: crc@40023000 { + compatible = "st,stm32f4-crc"; + reg = <0x40023000 0x400>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>; + status = "disabled"; + }; + rcc: rcc@40023810 { #reset-cells = <1>; #clock-cells = <2>; -- cgit v1.2.3 From 58518a0547a04f804531aeb59a5d92fbd1875ca7 Mon Sep 17 00:00:00 2001 From: Cosar Dindar Date: Mon, 22 May 2017 16:34:00 +0200 Subject: ARM: dts: stm32: enable CRC32 on stm32429-disco board Enable the CRC32 crypto on stm32429-disco board. Signed-off-by: Cosar Dindar Signed-off-by: Alexandre TORGUE --- arch/arm/boot/dts/stm32f429-disco.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 191fa50e34eb..ae47cde7952f 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -102,6 +102,10 @@ clock-frequency = <8000000>; }; +&crc { + status = "okay"; +}; + &rtc { assigned-clocks = <&rcc 1 CLK_RTC>; assigned-clock-parents = <&rcc 1 CLK_LSI>; -- cgit v1.2.3 From d6998234935e72521e26a8b7b8a85956cbfa3c7c Mon Sep 17 00:00:00 2001 From: Cosar Dindar Date: Mon, 22 May 2017 16:35:00 +0200 Subject: ARM: dts: stm32: enable CRC32 on stm32429i-eval board Enable the CRC32 crypto on stm32429i-eval board. Signed-off-by: Cosar Dindar Signed-off-by: Alexandre TORGUE --- arch/arm/boot/dts/stm32429i-eval.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 28f4a51a65e7..dcda0bbefe5b 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -160,6 +160,10 @@ clock-frequency = <25000000>; }; +&crc { + status = "okay"; +}; + &dcmi { status = "okay"; -- cgit v1.2.3 From 6ff0b90d746146f8270207551c0edbfe80986846 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 2 Jun 2017 20:13:45 +0200 Subject: ARM: dts: exynos: Use human-friendly symbols for interrupt flags in board sources Replace hard-coded values of interrupt flags with respective macros from header to increase code readability. Suggested-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250-monk.dts | 6 +++--- arch/arm/boot/dts/exynos3250-rinato.dts | 6 +++--- arch/arm/boot/dts/exynos4210-origen.dts | 2 +- arch/arm/boot/dts/exynos4210-trats.dts | 4 ++-- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 6 +++--- arch/arm/boot/dts/exynos4412-odroidx.dts | 2 +- arch/arm/boot/dts/exynos4412-trats2.dts | 8 ++++---- arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 ++-- arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi | 2 +- arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 ++-- 10 files changed, 22 insertions(+), 22 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index cccfe4b791d1..accee81da266 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -67,7 +67,7 @@ max77836: subpmic@25 { compatible = "maxim,max77836"; interrupt-parent = <&gpx1>; - interrupts = <5 0>; + interrupts = <5 IRQ_TYPE_NONE>; reg = <0x25>; wakeup-source; @@ -191,7 +191,7 @@ s2mps14_pmic@66 { compatible = "samsung,s2mps14-pmic"; interrupt-parent = <&gpx0>; - interrupts = <7 0>; + interrupts = <7 IRQ_TYPE_NONE>; reg = <0x66>; wakeup-source; @@ -414,7 +414,7 @@ fuelgauge@36 { compatible = "maxim,max77836-battery"; interrupt-parent = <&gpx1>; - interrupts = <2 8>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; reg = <0x36>; }; }; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index c9f191ca7b9c..118235b72e90 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -58,7 +58,7 @@ max77836: subpmic@25 { compatible = "maxim,max77836"; interrupt-parent = <&gpx1>; - interrupts = <5 0>; + interrupts = <5 IRQ_TYPE_NONE>; reg = <0x25>; wakeup-source; @@ -295,7 +295,7 @@ s2mps14_pmic@66 { compatible = "samsung,s2mps14-pmic"; interrupt-parent = <&gpx0>; - interrupts = <7 0>; + interrupts = <7 IRQ_TYPE_NONE>; reg = <0x66>; wakeup-source; @@ -626,7 +626,7 @@ fuelgauge@36 { compatible = "maxim,max77836-battery"; interrupt-parent = <&gpx1>; - interrupts = <2 8>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; reg = <0x36>; }; }; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 312650e2450f..084fcc5574ef 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -151,7 +151,7 @@ compatible = "maxim,max8997-pmic"; reg = <0x66>; interrupt-parent = <&gpx0>; - interrupts = <4 0>, <3 0>; + interrupts = <4 IRQ_TYPE_NONE>, <3 IRQ_TYPE_NONE>; max8997,pmic-buck1-dvs-voltage = <1350000>; max8997,pmic-buck2-dvs-voltage = <1100000>; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 1743ca850070..645feffb9239 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -281,7 +281,7 @@ compatible = "melfas,mms114"; reg = <0x48>; interrupt-parent = <&gpx0>; - interrupts = <4 2>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; x-size = <720>; y-size = <1280>; avdd-supply = <&tsp_reg>; @@ -302,7 +302,7 @@ reg = <0x66>; interrupt-parent = <&gpx0>; - interrupts = <7 0>; + interrupts = <7 IRQ_TYPE_NONE>; max8997,pmic-buck1-uses-gpio-dvs; max8997,pmic-buck2-uses-gpio-dvs; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 0f1ff792fe44..219d587c5a85 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -32,7 +32,7 @@ power_key { interrupt-parent = <&gpx1>; - interrupts = <3 0>; + interrupts = <3 IRQ_TYPE_NONE>; gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; linux,code = ; label = "power key"; @@ -266,7 +266,7 @@ max77686: pmic@09 { compatible = "maxim,max77686"; interrupt-parent = <&gpx3>; - interrupts = <2 0>; + interrupts = <2 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&max77686_irq>; reg = <0x09>; @@ -484,7 +484,7 @@ compatible = "maxim,max98090"; reg = <0x10>; interrupt-parent = <&gpx0>; - interrupts = <0 0>; + interrupts = <0 IRQ_TYPE_NONE>; clocks = <&i2s0 CLK_I2S_CDCLK>; clock-names = "mclk"; #sound-dai-cells = <0>; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 46b931eec228..97882267ef09 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -44,7 +44,7 @@ home_key { interrupt-parent = <&gpx2>; - interrupts = <2 0>; + interrupts = <2 IRQ_TYPE_NONE>; gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; linux,code = ; label = "home key"; diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index 82221a00444d..35e9b94b86b8 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -144,7 +144,7 @@ max77693@66 { compatible = "maxim,max77693"; interrupt-parent = <&gpx1>; - interrupts = <5 2>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; reg = <0x66>; regulators { @@ -224,7 +224,7 @@ compatible = "capella,cm36651"; reg = <0x18>; interrupt-parent = <&gpx0>; - interrupts = <2 2>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; vled-supply = <&ps_als_reg>; }; }; @@ -573,7 +573,7 @@ compatible = "melfas,mms114"; reg = <0x48>; interrupt-parent = <&gpm2>; - interrupts = <3 2>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; x-size = <720>; y-size = <1280>; avdd-supply = <&ldo23_reg>; @@ -611,7 +611,7 @@ max77686: max77686_pmic@09 { compatible = "maxim,max77686"; interrupt-parent = <&gpx0>; - interrupts = <7 0>; + interrupts = <7 IRQ_TYPE_NONE>; reg = <0x09>; #clock-cells = <1>; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 2cd65699a29c..f9a75bfd3f2b 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -603,7 +603,7 @@ max98090: codec@10 { compatible = "maxim,max98090"; reg = <0x10>; - interrupts = <2 0>; + interrupts = <2 IRQ_TYPE_NONE>; interrupt-parent = <&gpx0>; pinctrl-names = "default"; pinctrl-0 = <&max98090_irq>; @@ -944,7 +944,7 @@ cros_ec: cros-ec@0 { compatible = "google,cros-ec-spi"; interrupt-parent = <&gpx1>; - interrupts = <5 0>; + interrupts = <5 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&ec_spi_cs &ec_irq>; reg = <0>; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi index 9493923ec652..c0b85981c6bf 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi @@ -49,7 +49,7 @@ compatible = "maxim,max98090"; reg = <0x10>; interrupt-parent = <&gpx3>; - interrupts = <2 0>; + interrupts = <2 IRQ_TYPE_NONE>; clocks = <&i2s0 CLK_I2S_CDCLK>; clock-names = "mclk"; #sound-dai-cells = <0>; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index ecf1c916e8fc..953dc8677dc8 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -603,7 +603,7 @@ max98091: codec@10 { compatible = "maxim,max98091"; reg = <0x10>; - interrupts = <2 0>; + interrupts = <2 IRQ_TYPE_NONE>; interrupt-parent = <&gpx0>; pinctrl-names = "default"; pinctrl-0 = <&max98091_irq>; @@ -913,7 +913,7 @@ cros_ec: cros-ec@0 { compatible = "google,cros-ec-spi"; interrupt-parent = <&gpx1>; - interrupts = <5 0>; + interrupts = <5 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&ec_spi_cs &ec_irq>; reg = <0>; -- cgit v1.2.3 From c92a4fb249bf98670543b4c41307e1e71942d513 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 2 Jun 2017 20:13:46 +0200 Subject: ARM: dts: exynos: Use human-friendly symbols for GIC interrupt properties Replace hard-coded values of type of GIC interrupt and its flags with respective macros from header to increase code readability. Suggested-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5.dtsi | 84 +++++++++++++++++++-------------------- arch/arm/boot/dts/exynos5250.dtsi | 8 ++-- arch/arm/boot/dts/exynos5420.dtsi | 76 +++++++++++++++++------------------ arch/arm/boot/dts/exynos5440.dtsi | 2 +- 4 files changed, 85 insertions(+), 85 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index b74c5379ca26..66d22521c976 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -55,38 +55,38 @@ interrupt-controller; samsung,combiner-nr = <32>; reg = <0x10440000 0x1000>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, - <0 1 IRQ_TYPE_LEVEL_HIGH>, - <0 2 IRQ_TYPE_LEVEL_HIGH>, - <0 3 IRQ_TYPE_LEVEL_HIGH>, - <0 4 IRQ_TYPE_LEVEL_HIGH>, - <0 5 IRQ_TYPE_LEVEL_HIGH>, - <0 6 IRQ_TYPE_LEVEL_HIGH>, - <0 7 IRQ_TYPE_LEVEL_HIGH>, - <0 8 IRQ_TYPE_LEVEL_HIGH>, - <0 9 IRQ_TYPE_LEVEL_HIGH>, - <0 10 IRQ_TYPE_LEVEL_HIGH>, - <0 11 IRQ_TYPE_LEVEL_HIGH>, - <0 12 IRQ_TYPE_LEVEL_HIGH>, - <0 13 IRQ_TYPE_LEVEL_HIGH>, - <0 14 IRQ_TYPE_LEVEL_HIGH>, - <0 15 IRQ_TYPE_LEVEL_HIGH>, - <0 16 IRQ_TYPE_LEVEL_HIGH>, - <0 17 IRQ_TYPE_LEVEL_HIGH>, - <0 18 IRQ_TYPE_LEVEL_HIGH>, - <0 19 IRQ_TYPE_LEVEL_HIGH>, - <0 20 IRQ_TYPE_LEVEL_HIGH>, - <0 21 IRQ_TYPE_LEVEL_HIGH>, - <0 22 IRQ_TYPE_LEVEL_HIGH>, - <0 23 IRQ_TYPE_LEVEL_HIGH>, - <0 24 IRQ_TYPE_LEVEL_HIGH>, - <0 25 IRQ_TYPE_LEVEL_HIGH>, - <0 26 IRQ_TYPE_LEVEL_HIGH>, - <0 27 IRQ_TYPE_LEVEL_HIGH>, - <0 28 IRQ_TYPE_LEVEL_HIGH>, - <0 29 IRQ_TYPE_LEVEL_HIGH>, - <0 30 IRQ_TYPE_LEVEL_HIGH>, - <0 31 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; gic: interrupt-controller@10481000 { @@ -109,31 +109,31 @@ serial_0: serial@12C00000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C00000 0x100>; - interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; serial_1: serial@12C10000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C10000 0x100>; - interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; serial_2: serial@12C20000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C20000 0x100>; - interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; serial_3: serial@12C30000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C30000 0x100>; - interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; i2c_0: i2c@12C60000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C60000 0x100>; - interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; samsung,sysreg-phandle = <&sysreg_system_controller>; @@ -143,7 +143,7 @@ i2c_1: i2c@12C70000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C70000 0x100>; - interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; samsung,sysreg-phandle = <&sysreg_system_controller>; @@ -153,7 +153,7 @@ i2c_2: i2c@12C80000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C80000 0x100>; - interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; samsung,sysreg-phandle = <&sysreg_system_controller>; @@ -163,7 +163,7 @@ i2c_3: i2c@12C90000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C90000 0x100>; - interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; samsung,sysreg-phandle = <&sysreg_system_controller>; @@ -180,8 +180,8 @@ rtc: rtc@101E0000 { compatible = "samsung,s3c6410-rtc"; reg = <0x101E0000 0x100>; - interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>, - <0 44 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index fbdc1d53a2ce..8dbeb873e99c 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -153,10 +153,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; + interrupts = , + , + , + ; /* * Unfortunately we need this since some versions * of U-Boot on Exynos don't set the CNTFRQ register, diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index acd77b10b3df..02d2f898efa6 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -193,7 +193,7 @@ mfc: codec@11000000 { compatible = "samsung,mfc-v7"; reg = <0x11000000 0x10000>; - interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock CLK_MFC>; clock-names = "mfc"; power-domains = <&mfc_pd>; @@ -203,7 +203,7 @@ mmc_0: mmc@12200000 { compatible = "samsung,exynos5420-dw-mshc-smu"; - interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; reg = <0x12200000 0x2000>; @@ -215,7 +215,7 @@ mmc_1: mmc@12210000 { compatible = "samsung,exynos5420-dw-mshc-smu"; - interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; reg = <0x12210000 0x2000>; @@ -227,7 +227,7 @@ mmc_2: mmc@12220000 { compatible = "samsung,exynos5420-dw-mshc"; - interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; reg = <0x12220000 0x1000>; @@ -325,37 +325,37 @@ pinctrl_0: pinctrl@13400000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x13400000 0x1000>; - interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; wakeup-interrupt-controller { compatible = "samsung,exynos4210-wakeup-eint"; interrupt-parent = <&gic>; - interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; }; pinctrl_1: pinctrl@13410000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x13410000 0x1000>; - interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; pinctrl_2: pinctrl@14000000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x14000000 0x1000>; - interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; pinctrl_3: pinctrl@14010000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x14010000 0x1000>; - interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; pinctrl_4: pinctrl@03860000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x03860000 0x1000>; - interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; amba { @@ -368,7 +368,7 @@ adma: adma@03880000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x03880000 0x1000>; - interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock_audss EXYNOS_ADMA>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -379,7 +379,7 @@ pdma0: pdma@121A0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121A0000 0x1000>; - interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -390,7 +390,7 @@ pdma1: pdma@121B0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121B0000 0x1000>; - interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -401,7 +401,7 @@ mdma0: mdma@10800000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x10800000 0x1000>; - interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock CLK_MDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -412,7 +412,7 @@ mdma1: mdma@11C10000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x11C10000 0x1000>; - interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock CLK_MDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -484,7 +484,7 @@ spi_0: spi@12d20000 { compatible = "samsung,exynos4210-spi"; reg = <0x12d20000 0x100>; - interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; dmas = <&pdma0 5 &pdma0 4>; dma-names = "tx", "rx"; @@ -500,7 +500,7 @@ spi_1: spi@12d30000 { compatible = "samsung,exynos4210-spi"; reg = <0x12d30000 0x100>; - interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; dmas = <&pdma1 5 &pdma1 4>; dma-names = "tx", "rx"; @@ -516,7 +516,7 @@ spi_2: spi@12d40000 { compatible = "samsung,exynos4210-spi"; reg = <0x12d40000 0x100>; - interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; dmas = <&pdma0 7 &pdma0 6>; dma-names = "tx", "rx"; @@ -544,7 +544,7 @@ dsi@14500000 { compatible = "samsung,exynos5410-mipi-dsi"; reg = <0x14500000 0x10000>; - interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; phys = <&mipi_phy 1>; phy-names = "dsim"; clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; @@ -557,7 +557,7 @@ adc: adc@12D10000 { compatible = "samsung,exynos-adc-v2"; reg = <0x12D10000 0x100>; - interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock CLK_TSADC>; clock-names = "adc"; #io-channel-cells = <1>; @@ -569,7 +569,7 @@ hsi2c_8: i2c@12E00000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12E00000 0x1000>; - interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -582,7 +582,7 @@ hsi2c_9: i2c@12E10000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12E10000 0x1000>; - interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -595,7 +595,7 @@ hsi2c_10: i2c@12E20000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12E20000 0x1000>; - interrupts = <0 203 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -608,7 +608,7 @@ hdmi: hdmi@14530000 { compatible = "samsung,exynos5420-hdmi"; reg = <0x14530000 0x70000>; - interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, <&clock CLK_MOUT_HDMI>; @@ -640,7 +640,7 @@ mixer: mixer@14450000 { compatible = "samsung,exynos5420-mixer"; reg = <0x14450000 0x10000>; - interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>; clock-names = "mixer", "hdmi", "sclk_hdmi"; @@ -651,7 +651,7 @@ rotator: rotator@11C00000 { compatible = "samsung,exynos5250-rotator"; reg = <0x11C00000 0x64>; - interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock CLK_ROTATOR>; clock-names = "rotator"; iommus = <&sysmmu_rotator>; @@ -660,7 +660,7 @@ gsc_0: video-scaler@13e00000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e00000 0x1000>; - interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock CLK_GSCL0>; clock-names = "gscl"; power-domains = <&gsc_pd>; @@ -670,7 +670,7 @@ gsc_1: video-scaler@13e10000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e10000 0x1000>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock CLK_GSCL1>; clock-names = "gscl"; power-domains = <&gsc_pd>; @@ -680,7 +680,7 @@ jpeg_0: jpeg@11F50000 { compatible = "samsung,exynos5420-jpeg"; reg = <0x11F50000 0x1000>; - interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clock-names = "jpeg"; clocks = <&clock CLK_JPEG>; iommus = <&sysmmu_jpeg0>; @@ -689,7 +689,7 @@ jpeg_1: jpeg@11F60000 { compatible = "samsung,exynos5420-jpeg"; reg = <0x11F60000 0x1000>; - interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clock-names = "jpeg"; clocks = <&clock CLK_JPEG2>; iommus = <&sysmmu_jpeg1>; @@ -709,7 +709,7 @@ tmu_cpu0: tmu@10060000 { compatible = "samsung,exynos5420-tmu"; reg = <0x10060000 0x100>; - interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; #include "exynos5420-tmu-sensor-conf.dtsi" @@ -718,7 +718,7 @@ tmu_cpu1: tmu@10064000 { compatible = "samsung,exynos5420-tmu"; reg = <0x10064000 0x100>; - interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; #include "exynos5420-tmu-sensor-conf.dtsi" @@ -727,7 +727,7 @@ tmu_cpu2: tmu@10068000 { compatible = "samsung,exynos5420-tmu-ext-triminfo"; reg = <0x10068000 0x100>, <0x1006c000 0x4>; - interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; #include "exynos5420-tmu-sensor-conf.dtsi" @@ -736,7 +736,7 @@ tmu_cpu3: tmu@1006c000 { compatible = "samsung,exynos5420-tmu-ext-triminfo"; reg = <0x1006c000 0x100>, <0x100a0000 0x4>; - interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; #include "exynos5420-tmu-sensor-conf.dtsi" @@ -745,7 +745,7 @@ tmu_gpu: tmu@100a0000 { compatible = "samsung,exynos5420-tmu-ext-triminfo"; reg = <0x100a0000 0x100>, <0x10068000 0x4>; - interrupts = <0 215 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; #include "exynos5420-tmu-sensor-conf.dtsi" @@ -817,7 +817,7 @@ sysmmu_scaler1r: sysmmu@0x12890000 { compatible = "samsung,exynos-sysmmu"; reg = <0x12890000 0x1000>; - interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; #iommu-cells = <0>; @@ -826,7 +826,7 @@ sysmmu_scaler2r: sysmmu@0x128A0000 { compatible = "samsung,exynos-sysmmu"; reg = <0x128A0000 0x1000>; - interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; #iommu-cells = <0>; @@ -885,7 +885,7 @@ sysmmu_jpeg1: sysmmu@0x11F20000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11F20000 0x1000>; - interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; #iommu-cells = <0>; diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index a4ea018464fc..bc4954e69f7b 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -200,7 +200,7 @@ compatible = "snps,dwmac-3.70a", "snps,dwmac"; reg = <0x00230000 0x8000>; interrupt-parent = <&gic>; - interrupts = ; + interrupts = ; interrupt-names = "macirq"; phy-mode = "sgmii"; clocks = <&clock CLK_GMAC0>; -- cgit v1.2.3 From 99b3587debacd24b30ecfae5ae59ed7a5070528b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 31 May 2017 15:51:29 -0700 Subject: ARM: OMAP2+: Remove unused legacy code for opp We are now booting all mach-omap2 in device tree only mode. Any code that is only called in legacy boot mode where of_have_populated_dt() is not set is safe to remove now. Note that the volt_data is still being used. Reviewed-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Makefile | 1 - arch/arm/mach-omap2/opp.c | 104 ------------------------------------- arch/arm/mach-omap2/opp3xxx_data.c | 86 ------------------------------ arch/arm/mach-omap2/opp4xxx_data.c | 79 ---------------------------- 4 files changed, 270 deletions(-) delete mode 100644 arch/arm/mach-omap2/opp.c (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index c89757abb0ae..deb6c33a7bd0 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -69,7 +69,6 @@ obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o # OPP table initialization ifeq ($(CONFIG_PM_OPP),y) -obj-y += opp.o obj-$(CONFIG_ARCH_OMAP3) += opp3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += opp4xxx_data.o endif diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c deleted file mode 100644 index a358a07e18f2..000000000000 --- a/arch/arm/mach-omap2/opp.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * OMAP SoC specific OPP wrapper function - * - * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/ - * Nishanth Menon - * Kevin Hilman - * Copyright (C) 2010 Nokia Corporation. - * Eduardo Valentin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include -#include -#include -#include - -#include "omap_device.h" - -#include "omap_opp_data.h" - -/* Temp variable to allow multiple calls */ -static u8 __initdata omap_table_init; - -/** - * omap_init_opp_table() - Initialize opp table as per the CPU type - * @opp_def: opp default list for this silicon - * @opp_def_size: number of opp entries for this silicon - * - * Register the initial OPP table with the OPP library based on the CPU - * type. This is meant to be used only by SoC specific registration. - */ -int __init omap_init_opp_table(struct omap_opp_def *opp_def, - u32 opp_def_size) -{ - int i, r; - - if (of_have_populated_dt()) - return -EINVAL; - - if (!opp_def || !opp_def_size) { - pr_err("%s: invalid params!\n", __func__); - return -EINVAL; - } - - /* - * Initialize only if not already initialized even if the previous - * call failed, because, no reason we'd succeed again. - */ - if (omap_table_init) - return -EEXIST; - omap_table_init = 1; - - /* Lets now register with OPP library */ - for (i = 0; i < opp_def_size; i++, opp_def++) { - struct omap_hwmod *oh; - struct device *dev; - - if (!opp_def->hwmod_name) { - pr_err("%s: NULL name of omap_hwmod, failing [%d].\n", - __func__, i); - return -EINVAL; - } - - if (!strncmp(opp_def->hwmod_name, "mpu", 3)) { - /* - * All current OMAPs share voltage rail and - * clock source, so CPU0 is used to represent - * the MPU-SS. - */ - dev = get_cpu_device(0); - } else { - oh = omap_hwmod_lookup(opp_def->hwmod_name); - if (!oh || !oh->od) { - pr_debug("%s: no hwmod or odev for %s, [%d] cannot add OPPs.\n", - __func__, opp_def->hwmod_name, i); - continue; - } - dev = &oh->od->pdev->dev; - } - - r = dev_pm_opp_add(dev, opp_def->freq, opp_def->u_volt); - if (r) { - dev_err(dev, "%s: add OPP %ld failed for %s [%d] result=%d\n", - __func__, opp_def->freq, - opp_def->hwmod_name, i, r); - } else { - if (!opp_def->default_available) - r = dev_pm_opp_disable(dev, opp_def->freq); - if (r) - dev_err(dev, "%s: disable %ld failed for %s [%d] result=%d\n", - __func__, opp_def->freq, - opp_def->hwmod_name, i, r); - } - } - - return 0; -} diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c index fc67add76444..c2d459f5b0da 100644 --- a/arch/arm/mach-omap2/opp3xxx_data.c +++ b/arch/arm/mach-omap2/opp3xxx_data.c @@ -83,89 +83,3 @@ struct omap_volt_data omap36xx_vddcore_volt_data[] = { VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16), VOLT_DATA_DEFINE(0, 0, 0, 0), }; - -/* OPP data */ - -static struct omap_opp_def __initdata omap34xx_opp_def_list[] = { - /* MPU OPP1 */ - OPP_INITIALIZER("mpu", true, 125000000, OMAP3430_VDD_MPU_OPP1_UV), - /* MPU OPP2 */ - OPP_INITIALIZER("mpu", true, 250000000, OMAP3430_VDD_MPU_OPP2_UV), - /* MPU OPP3 */ - OPP_INITIALIZER("mpu", true, 500000000, OMAP3430_VDD_MPU_OPP3_UV), - /* MPU OPP4 */ - OPP_INITIALIZER("mpu", true, 550000000, OMAP3430_VDD_MPU_OPP4_UV), - /* MPU OPP5 */ - OPP_INITIALIZER("mpu", true, 600000000, OMAP3430_VDD_MPU_OPP5_UV), - - /* - * L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is - * almost the same than the one at 83MHz thus providing very little - * gain for the power point of view. In term of energy it will even - * increase the consumption due to the very negative performance - * impact that frequency will do to the MPU and the whole system in - * general. - */ - OPP_INITIALIZER("l3_main", false, 41500000, OMAP3430_VDD_CORE_OPP1_UV), - /* L3 OPP2 */ - OPP_INITIALIZER("l3_main", true, 83000000, OMAP3430_VDD_CORE_OPP2_UV), - /* L3 OPP3 */ - OPP_INITIALIZER("l3_main", true, 166000000, OMAP3430_VDD_CORE_OPP3_UV), - - /* DSP OPP1 */ - OPP_INITIALIZER("iva", true, 90000000, OMAP3430_VDD_MPU_OPP1_UV), - /* DSP OPP2 */ - OPP_INITIALIZER("iva", true, 180000000, OMAP3430_VDD_MPU_OPP2_UV), - /* DSP OPP3 */ - OPP_INITIALIZER("iva", true, 360000000, OMAP3430_VDD_MPU_OPP3_UV), - /* DSP OPP4 */ - OPP_INITIALIZER("iva", true, 400000000, OMAP3430_VDD_MPU_OPP4_UV), - /* DSP OPP5 */ - OPP_INITIALIZER("iva", true, 430000000, OMAP3430_VDD_MPU_OPP5_UV), -}; - -static struct omap_opp_def __initdata omap36xx_opp_def_list[] = { - /* MPU OPP1 - OPP50 */ - OPP_INITIALIZER("mpu", true, 300000000, OMAP3630_VDD_MPU_OPP50_UV), - /* MPU OPP2 - OPP100 */ - OPP_INITIALIZER("mpu", true, 600000000, OMAP3630_VDD_MPU_OPP100_UV), - /* MPU OPP3 - OPP-Turbo */ - OPP_INITIALIZER("mpu", false, 800000000, OMAP3630_VDD_MPU_OPP120_UV), - /* MPU OPP4 - OPP-SB */ - OPP_INITIALIZER("mpu", false, 1000000000, OMAP3630_VDD_MPU_OPP1G_UV), - - /* L3 OPP1 - OPP50 */ - OPP_INITIALIZER("l3_main", true, 100000000, OMAP3630_VDD_CORE_OPP50_UV), - /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */ - OPP_INITIALIZER("l3_main", true, 200000000, OMAP3630_VDD_CORE_OPP100_UV), - - /* DSP OPP1 - OPP50 */ - OPP_INITIALIZER("iva", true, 260000000, OMAP3630_VDD_MPU_OPP50_UV), - /* DSP OPP2 - OPP100 */ - OPP_INITIALIZER("iva", true, 520000000, OMAP3630_VDD_MPU_OPP100_UV), - /* DSP OPP3 - OPP-Turbo */ - OPP_INITIALIZER("iva", false, 660000000, OMAP3630_VDD_MPU_OPP120_UV), - /* DSP OPP4 - OPP-SB */ - OPP_INITIALIZER("iva", false, 800000000, OMAP3630_VDD_MPU_OPP1G_UV), -}; - -/** - * omap3_opp_init() - initialize omap3 opp table - */ -int __init omap3_opp_init(void) -{ - int r = -ENODEV; - - if (!cpu_is_omap34xx()) - return r; - - if (cpu_is_omap3630()) - r = omap_init_opp_table(omap36xx_opp_def_list, - ARRAY_SIZE(omap36xx_opp_def_list)); - else - r = omap_init_opp_table(omap34xx_opp_def_list, - ARRAY_SIZE(omap34xx_opp_def_list)); - - return r; -} -omap_device_initcall(omap3_opp_init); diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c index 1ef7a3e5ce4a..adea43ea1c60 100644 --- a/arch/arm/mach-omap2/opp4xxx_data.c +++ b/arch/arm/mach-omap2/opp4xxx_data.c @@ -63,29 +63,6 @@ struct omap_volt_data omap443x_vdd_core_volt_data[] = { VOLT_DATA_DEFINE(0, 0, 0, 0), }; - -static struct omap_opp_def __initdata omap443x_opp_def_list[] = { - /* MPU OPP1 - OPP50 */ - OPP_INITIALIZER("mpu", true, 300000000, OMAP4430_VDD_MPU_OPP50_UV), - /* MPU OPP2 - OPP100 */ - OPP_INITIALIZER("mpu", true, 600000000, OMAP4430_VDD_MPU_OPP100_UV), - /* MPU OPP3 - OPP-Turbo */ - OPP_INITIALIZER("mpu", true, 800000000, OMAP4430_VDD_MPU_OPPTURBO_UV), - /* MPU OPP4 - OPP-SB */ - OPP_INITIALIZER("mpu", true, 1008000000, OMAP4430_VDD_MPU_OPPNITRO_UV), - /* L3 OPP1 - OPP50 */ - OPP_INITIALIZER("l3_main_1", true, 100000000, OMAP4430_VDD_CORE_OPP50_UV), - /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */ - OPP_INITIALIZER("l3_main_1", true, 200000000, OMAP4430_VDD_CORE_OPP100_UV), - /* IVA OPP1 - OPP50 */ - OPP_INITIALIZER("iva", true, 133000000, OMAP4430_VDD_IVA_OPP50_UV), - /* IVA OPP2 - OPP100 */ - OPP_INITIALIZER("iva", true, 266100000, OMAP4430_VDD_IVA_OPP100_UV), - /* IVA OPP3 - OPP-Turbo */ - OPP_INITIALIZER("iva", false, 332000000, OMAP4430_VDD_IVA_OPPTURBO_UV), - /* TODO: add DSP, aess, fdif, gpu */ -}; - #define OMAP4460_VDD_MPU_OPP50_UV 1025000 #define OMAP4460_VDD_MPU_OPP100_UV 1200000 #define OMAP4460_VDD_MPU_OPPTURBO_UV 1313000 @@ -122,59 +99,3 @@ struct omap_volt_data omap446x_vdd_core_volt_data[] = { VOLT_DATA_DEFINE(OMAP4460_VDD_CORE_OPP100_OV_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100OV, 0xf9, 0x16), VOLT_DATA_DEFINE(0, 0, 0, 0), }; - -static struct omap_opp_def __initdata omap446x_opp_def_list[] = { - /* MPU OPP1 - OPP50 */ - OPP_INITIALIZER("mpu", true, 350000000, OMAP4460_VDD_MPU_OPP50_UV), - /* MPU OPP2 - OPP100 */ - OPP_INITIALIZER("mpu", true, 700000000, OMAP4460_VDD_MPU_OPP100_UV), - /* MPU OPP3 - OPP-Turbo */ - OPP_INITIALIZER("mpu", true, 920000000, OMAP4460_VDD_MPU_OPPTURBO_UV), - /* - * MPU OPP4 - OPP-Nitro + Disabled as the reference schematics - * recommends TPS623631 - confirm and enable the opp in board file - * XXX: May be we should enable these based on mpu capability and - * Exception board files disable it... - */ - OPP_INITIALIZER("mpu", false, 1200000000, OMAP4460_VDD_MPU_OPPNITRO_UV), - /* MPU OPP4 - OPP-Nitro SpeedBin */ - OPP_INITIALIZER("mpu", false, 1500000000, OMAP4460_VDD_MPU_OPPNITRO_UV), - /* L3 OPP1 - OPP50 */ - OPP_INITIALIZER("l3_main_1", true, 100000000, OMAP4460_VDD_CORE_OPP50_UV), - /* L3 OPP2 - OPP100 */ - OPP_INITIALIZER("l3_main_1", true, 200000000, OMAP4460_VDD_CORE_OPP100_UV), - /* IVA OPP1 - OPP50 */ - OPP_INITIALIZER("iva", true, 133000000, OMAP4460_VDD_IVA_OPP50_UV), - /* IVA OPP2 - OPP100 */ - OPP_INITIALIZER("iva", true, 266100000, OMAP4460_VDD_IVA_OPP100_UV), - /* - * IVA OPP3 - OPP-Turbo + Disabled as the reference schematics - * recommends Phoenix VCORE2 which can supply only 600mA - so the ones - * above this OPP frequency, even though OMAP is capable, should be - * enabled by board file which is sure of the chip power capability - */ - OPP_INITIALIZER("iva", false, 332000000, OMAP4460_VDD_IVA_OPPTURBO_UV), - /* IVA OPP4 - OPP-Nitro */ - OPP_INITIALIZER("iva", false, 430000000, OMAP4460_VDD_IVA_OPPNITRO_UV), - /* IVA OPP5 - OPP-Nitro SpeedBin*/ - OPP_INITIALIZER("iva", false, 500000000, OMAP4460_VDD_IVA_OPPNITRO_UV), - - /* TODO: add DSP, aess, fdif, gpu */ -}; - -/** - * omap4_opp_init() - initialize omap4 opp table - */ -int __init omap4_opp_init(void) -{ - int r = -ENODEV; - - if (cpu_is_omap443x()) - r = omap_init_opp_table(omap443x_opp_def_list, - ARRAY_SIZE(omap443x_opp_def_list)); - else if (cpu_is_omap446x()) - r = omap_init_opp_table(omap446x_opp_def_list, - ARRAY_SIZE(omap446x_opp_def_list)); - return r; -} -omap_device_initcall(omap4_opp_init); -- cgit v1.2.3 From 7bd6934477413753eacbcab8aeb2df7eb84f2867 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 31 May 2017 15:51:31 -0700 Subject: ARM: OMAP2+: Remove unused legacy code for PMU We are now booting all mach-omap2 in device tree only mode. Any code that is only called in legacy boot mode where of_have_populated_dt() is not set is safe to remove now. Reviewed-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Makefile | 3 -- arch/arm/mach-omap2/pmu.c | 97 -------------------------------------------- 2 files changed, 100 deletions(-) delete mode 100644 arch/arm/mach-omap2/pmu.c (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index deb6c33a7bd0..779fb1f680b3 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -219,9 +219,6 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o -# EMU peripherals -obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o - # OMAP2420 MSDI controller integration support ("MMC") obj-$(CONFIG_SOC_OMAP2420) += msdi.o diff --git a/arch/arm/mach-omap2/pmu.c b/arch/arm/mach-omap2/pmu.c deleted file mode 100644 index d2adfebd3b3f..000000000000 --- a/arch/arm/mach-omap2/pmu.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * OMAP2 ARM Performance Monitoring Unit (PMU) Support - * - * Copyright (C) 2012 Texas Instruments, Inc. - * - * Contacts: - * Jon Hunter - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ -#include - -#include - -#include "soc.h" -#include "omap_hwmod.h" -#include "omap_device.h" - -static char *omap2_pmu_oh_names[] = {"mpu"}; -static char *omap3_pmu_oh_names[] = {"mpu", "debugss"}; -static char *omap4430_pmu_oh_names[] = {"l3_main_3", "l3_instr", "debugss"}; -static struct platform_device *omap_pmu_dev; - -/** - * omap2_init_pmu - creates and registers PMU platform device - * @oh_num: Number of OMAP HWMODs required to create PMU device - * @oh_names: Array of OMAP HWMODS names required to create PMU device - * - * Uses OMAP HWMOD framework to create and register an ARM PMU device - * from a list of HWMOD names passed. Currently supports OMAP2, OMAP3 - * and OMAP4 devices. - */ -static int __init omap2_init_pmu(unsigned oh_num, char *oh_names[]) -{ - int i; - struct omap_hwmod *oh[3]; - char *dev_name = cpu_architecture() == CPU_ARCH_ARMv6 ? - "armv6-pmu" : "armv7-pmu"; - - if ((!oh_num) || (oh_num > 3)) - return -EINVAL; - - for (i = 0; i < oh_num; i++) { - oh[i] = omap_hwmod_lookup(oh_names[i]); - if (!oh[i]) { - pr_err("Could not look up %s hwmod\n", oh_names[i]); - return -ENODEV; - } - } - - omap_pmu_dev = omap_device_build_ss(dev_name, -1, oh, oh_num, NULL, 0); - WARN(IS_ERR(omap_pmu_dev), "Can't build omap_device for %s.\n", - dev_name); - - return PTR_ERR_OR_ZERO(omap_pmu_dev); -} - -static int __init omap_init_pmu(void) -{ - unsigned oh_num; - char **oh_names; - - /* XXX Remove this check when the CTI driver is available */ - if (cpu_is_omap443x()) { - pr_info("ARM PMU: not yet supported on OMAP4430 due to missing CTI driver\n"); - return 0; - } - - if (of_have_populated_dt()) - return 0; - - /* - * To create an ARM-PMU device the following HWMODs - * are required for the various OMAP2+ devices. - * - * OMAP24xx: mpu - * OMAP3xxx: mpu, debugss - * OMAP4430: l3_main_3, l3_instr, debugss - * OMAP4460/70: mpu, debugss - */ - if (cpu_is_omap443x()) { - oh_num = ARRAY_SIZE(omap4430_pmu_oh_names); - oh_names = omap4430_pmu_oh_names; - } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { - oh_num = ARRAY_SIZE(omap3_pmu_oh_names); - oh_names = omap3_pmu_oh_names; - } else { - oh_num = ARRAY_SIZE(omap2_pmu_oh_names); - oh_names = omap2_pmu_oh_names; - } - - return omap2_init_pmu(oh_num, oh_names); -} -omap_subsys_initcall(omap_init_pmu); -- cgit v1.2.3 From 6f3ab009a178098e834d9e060f03e1232bb449c1 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 31 May 2017 15:51:32 -0700 Subject: ARM: OMAP2+: Remove unused legacy code for device init We are now booting all mach-omap2 in device tree only mode. Any code that is only called in legacy boot mode where of_have_populated_dt() is not set is safe to remove now. Note that omap_init_sti() won't do anything so we can remove omap2_init_devices() as pointed out by Sebastian Reichel . Reviewed-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/devices.c | 175 ------------------------------------------ 1 file changed, 175 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 473951203104..93057fb65f44 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -36,130 +36,6 @@ #define L3_MODULES_MAX_LEN 12 #define L3_MODULES 3 -static int __init omap3_l3_init(void) -{ - struct omap_hwmod *oh; - struct platform_device *pdev; - char oh_name[L3_MODULES_MAX_LEN]; - - /* - * To avoid code running on other OMAPs in - * multi-omap builds - */ - if (!(cpu_is_omap34xx()) || of_have_populated_dt()) - return -ENODEV; - - snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main"); - - oh = omap_hwmod_lookup(oh_name); - - if (!oh) - pr_err("could not look up %s\n", oh_name); - - pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0); - - WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); - - return PTR_ERR_OR_ZERO(pdev); -} -omap_postcore_initcall(omap3_l3_init); - -static inline void omap_init_sti(void) {} - -#if IS_ENABLED(CONFIG_SPI_OMAP24XX) - -#include - -static int __init omap_mcspi_init(struct omap_hwmod *oh, void *unused) -{ - struct platform_device *pdev; - char *name = "omap2_mcspi"; - struct omap2_mcspi_platform_config *pdata; - static int spi_num; - struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr; - - pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); - if (!pdata) { - pr_err("Memory allocation for McSPI device failed\n"); - return -ENOMEM; - } - - pdata->num_cs = mcspi_attrib->num_chipselect; - switch (oh->class->rev) { - case OMAP2_MCSPI_REV: - case OMAP3_MCSPI_REV: - pdata->regs_offset = 0; - break; - case OMAP4_MCSPI_REV: - pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET; - break; - default: - pr_err("Invalid McSPI Revision value\n"); - kfree(pdata); - return -EINVAL; - } - - spi_num++; - pdev = omap_device_build(name, spi_num, oh, pdata, sizeof(*pdata)); - WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n", - name, oh->name); - kfree(pdata); - return 0; -} - -static void omap_init_mcspi(void) -{ - omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL); -} - -#else -static inline void omap_init_mcspi(void) {} -#endif - -/** - * omap_init_rng - bind the RNG hwmod to the RNG omap_device - * - * Bind the RNG hwmod to the RNG omap_device. No return value. - */ -static void __init omap_init_rng(void) -{ - struct omap_hwmod *oh; - struct platform_device *pdev; - - oh = omap_hwmod_lookup("rng"); - if (!oh) - return; - - pdev = omap_device_build("omap_rng", -1, oh, NULL, 0); - WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n"); -} - -static void __init omap_init_sham(void) -{ - struct omap_hwmod *oh; - struct platform_device *pdev; - - oh = omap_hwmod_lookup("sham"); - if (!oh) - return; - - pdev = omap_device_build("omap-sham", -1, oh, NULL, 0); - WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n"); -} - -static void __init omap_init_aes(void) -{ - struct omap_hwmod *oh; - struct platform_device *pdev; - - oh = omap_hwmod_lookup("aes"); - if (!oh) - return; - - pdev = omap_device_build("omap-aes", -1, oh, NULL, 0); - WARN(IS_ERR(pdev), "Can't build omap_device for omap-aes\n"); -} - /*-------------------------------------------------------------------------*/ #if IS_ENABLED(CONFIG_VIDEO_OMAP2_VOUT) @@ -185,54 +61,3 @@ int __init omap_init_vout(void) #else int __init omap_init_vout(void) { return 0; } #endif - -/*-------------------------------------------------------------------------*/ - -static int __init omap2_init_devices(void) -{ - /* Enable dummy states for those platforms without pinctrl support */ - if (!of_have_populated_dt()) - pinctrl_provide_dummies(); - - /* If dtb is there, the devices will be created dynamically */ - if (!of_have_populated_dt()) { - /* - * please keep these calls, and their implementations above, - * in alphabetical order so they're easier to sort through. - */ - omap_init_mcspi(); - omap_init_sham(); - omap_init_aes(); - omap_init_rng(); - } - omap_init_sti(); - - return 0; -} -omap_arch_initcall(omap2_init_devices); - -static int __init omap_gpmc_init(void) -{ - struct omap_hwmod *oh; - struct platform_device *pdev; - char *oh_name = "gpmc"; - - /* - * if the board boots up with a populated DT, do not - * manually add the device from this initcall - */ - if (of_have_populated_dt()) - return -ENODEV; - - oh = omap_hwmod_lookup(oh_name); - if (!oh) { - pr_err("Could not look up %s\n", oh_name); - return -ENODEV; - } - - pdev = omap_device_build("omap-gpmc", -1, oh, NULL, 0); - WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); - - return PTR_ERR_OR_ZERO(pdev); -} -omap_postcore_initcall(omap_gpmc_init); -- cgit v1.2.3 From 1a61a2a5a6476c9053a6c50265ded7f1387960fb Mon Sep 17 00:00:00 2001 From: Markus Elfring Date: Sat, 3 Jun 2017 17:24:27 +0200 Subject: ARM: OMAP2+: Delete an error message for a failed memory allocation in two functions Omit an extra message for a memory allocation failure in these functions. This issue was detected by using the Coccinelle software. Link: http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings-WSang_0.pdf Signed-off-by: Markus Elfring Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/hsmmc.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index cb754c46747e..be517b048762 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -153,7 +153,6 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL); if (!hc_name) { - pr_err("Cannot allocate memory for controller slot name\n"); kfree(hc_name); return -ENOMEM; } @@ -315,10 +314,8 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo, int res; mmc_data = kzalloc(sizeof(*mmc_data), GFP_KERNEL); - if (!mmc_data) { - pr_err("Cannot allocate memory for mmc device!\n"); + if (!mmc_data) return; - } res = omap_hsmmc_pdata_init(hsmmcinfo, mmc_data); if (res < 0) -- cgit v1.2.3 From 1dfb5b59d6571104eff6629a0e73a6af347a3226 Mon Sep 17 00:00:00 2001 From: Markus Elfring Date: Sat, 3 Jun 2017 19:02:24 +0200 Subject: ARM: OMAP2+: Improve a size determination in sr_dev_init() Replace the specification of a data structure by a pointer dereference as the parameter for the operator "sizeof" to make the corresponding size determination a bit safer according to the Linux coding style convention. Signed-off-by: Markus Elfring Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/sr_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c index d7cff2632d1e..01df4907c0e3 100644 --- a/arch/arm/mach-omap2/sr_device.c +++ b/arch/arm/mach-omap2/sr_device.c @@ -102,7 +102,7 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user) char *name = "smartreflex"; static int i; - sr_data = kzalloc(sizeof(struct omap_sr_data), GFP_KERNEL); + sr_data = kzalloc(sizeof(*sr_data), GFP_KERNEL); if (!sr_data) { pr_err("%s: Unable to allocate memory for %s sr_data\n", __func__, oh->name); -- cgit v1.2.3 From 6b72de4d331f058dbd8fa327f1e5d0a729583f56 Mon Sep 17 00:00:00 2001 From: Markus Elfring Date: Sat, 3 Jun 2017 19:09:07 +0200 Subject: ARM: OMAP2+: Use kcalloc() in sr_set_nvalues() * A multiplication for the size determination of a memory allocation indicated that an array data structure should be processed. Thus use the corresponding function "kcalloc". This issue was detected by using the Coccinelle software. * Replace the specification of a data structure by a pointer dereference to make the corresponding size determination a bit safer according to the Linux coding style convention. Signed-off-by: Markus Elfring Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/sr_device.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c index 01df4907c0e3..65775c6e8c27 100644 --- a/arch/arm/mach-omap2/sr_device.c +++ b/arch/arm/mach-omap2/sr_device.c @@ -44,9 +44,7 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data, while (volt_data[count].volt_nominal) count++; - nvalue_table = kzalloc(sizeof(struct omap_sr_nvalue_table)*count, - GFP_KERNEL); - + nvalue_table = kcalloc(count, sizeof(*nvalue_table), GFP_KERNEL); if (!nvalue_table) { pr_err("OMAP: SmartReflex: cannot allocate memory for n-value table\n"); return; -- cgit v1.2.3 From c76e4d2e50068ddd82fe18f86d05a33733877059 Mon Sep 17 00:00:00 2001 From: Markus Elfring Date: Sat, 3 Jun 2017 19:16:27 +0200 Subject: ARM: OMAP2+: SmartReflex: Delete an error message for a failed memory allocation in two functions Omit an extra message for a memory allocation failure in these functions. This issue was detected by using the Coccinelle software. Link: http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings-WSang_0.pdf Signed-off-by: Markus Elfring Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/sr_device.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c index 65775c6e8c27..eef6935e0403 100644 --- a/arch/arm/mach-omap2/sr_device.c +++ b/arch/arm/mach-omap2/sr_device.c @@ -45,10 +45,8 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data, count++; nvalue_table = kcalloc(count, sizeof(*nvalue_table), GFP_KERNEL); - if (!nvalue_table) { - pr_err("OMAP: SmartReflex: cannot allocate memory for n-value table\n"); + if (!nvalue_table) return; - } for (i = 0, j = 0; i < count; i++) { u32 v; @@ -101,11 +99,8 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user) static int i; sr_data = kzalloc(sizeof(*sr_data), GFP_KERNEL); - if (!sr_data) { - pr_err("%s: Unable to allocate memory for %s sr_data\n", - __func__, oh->name); + if (!sr_data) return -ENOMEM; - } sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr; if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) { -- cgit v1.2.3 From 48f6693790aa899c813a83f12be1d723849dc3a2 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 31 May 2017 15:51:33 -0700 Subject: ARM: OMAP2+: Remove unused legacy code for McBSP We are now booting all mach-omap2 in device tree only mode. Any code that is only called in legacy boot mode where of_have_populated_dt() is not set is safe to remove now. Acked-by: Peter Ujfalusi Reviewed-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/mcbsp.c | 70 --------------------------------------------- 1 file changed, 70 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index fc04be74e064..4acc0dae27e0 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -53,73 +53,3 @@ void __init omap3_mcbsp_init_pdata_callback( pdata->force_ick_on = omap3_mcbsp_force_ick_on; } - -static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused) -{ - int id, count = 1; - char *name = "omap-mcbsp"; - struct omap_hwmod *oh_device[2]; - struct omap_mcbsp_platform_data *pdata = NULL; - struct platform_device *pdev; - - sscanf(oh->name, "mcbsp%d", &id); - - pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL); - if (!pdata) { - pr_err("%s: No memory for mcbsp\n", __func__); - return -ENOMEM; - } - - pdata->reg_step = 4; - if (oh->class->rev < MCBSP_CONFIG_TYPE2) { - pdata->reg_size = 2; - } else { - pdata->reg_size = 4; - pdata->has_ccr = true; - } - - if (oh->class->rev == MCBSP_CONFIG_TYPE2) { - /* The FIFO has 128 locations */ - pdata->buffer_size = 0x80; - } else if (oh->class->rev == MCBSP_CONFIG_TYPE3) { - if (id == 2) - /* The FIFO has 1024 + 256 locations */ - pdata->buffer_size = 0x500; - else - /* The FIFO has 128 locations */ - pdata->buffer_size = 0x80; - } else if (oh->class->rev == MCBSP_CONFIG_TYPE4) { - /* The FIFO has 128 locations for all instances */ - pdata->buffer_size = 0x80; - } - - if (oh->class->rev >= MCBSP_CONFIG_TYPE3) - pdata->has_wakeup = true; - - oh_device[0] = oh; - - if (oh->dev_attr) { - oh_device[1] = omap_hwmod_lookup(( - (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone); - pdata->force_ick_on = omap3_mcbsp_force_ick_on; - count++; - } - pdev = omap_device_build_ss(name, id, oh_device, count, pdata, - sizeof(*pdata)); - kfree(pdata); - if (IS_ERR(pdev)) { - pr_err("%s: Can't build omap_device for %s:%s.\n", __func__, - name, oh->name); - return PTR_ERR(pdev); - } - return 0; -} - -static int __init omap2_mcbsp_init(void) -{ - if (!of_have_populated_dt()) - omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL); - - return 0; -} -omap_arch_initcall(omap2_mcbsp_init); -- cgit v1.2.3 From 58a641c827e2ef75b93bf799b05be28eb20cca23 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 31 May 2017 15:51:34 -0700 Subject: ARM: OMAP2+: Remove unused legacy code for io.c We are now booting all mach-omap2 in device tree only mode. Any code that is only called in legacy boot mode where of_have_populated_dt() is not set is safe to remove now. Reviewed-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/io.c | 59 ++++++++++++------------------------------------ 1 file changed, 14 insertions(+), 45 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 5aafb8449c40..1d739d1a0a65 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -493,67 +493,39 @@ void __init omap3_init_early(void) omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); - /* XXX: remove these once OMAP3 is DT only */ - if (!of_have_populated_dt()) { - omap2_set_globals_control( - OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE)); - omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); - omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), - NULL); - } omap2_control_base_init(); omap3xxx_check_revision(); omap3xxx_check_features(); omap2_prcm_base_init(); - /* XXX: remove these once OMAP3 is DT only */ - if (!of_have_populated_dt()) { - omap3xxx_prm_init(NULL); - omap3xxx_cm_init(NULL); - } omap3xxx_voltagedomains_init(); omap3xxx_powerdomains_init(); omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); omap_hwmod_init_postsetup(); - if (!of_have_populated_dt()) { - omap3_control_legacy_iomap_init(); - if (soc_is_am35xx()) - omap_clk_soc_init = am35xx_clk_legacy_init; - else if (cpu_is_omap3630()) - omap_clk_soc_init = omap36xx_clk_legacy_init; - else if (omap_rev() == OMAP3430_REV_ES1_0) - omap_clk_soc_init = omap3430es1_clk_legacy_init; - else - omap_clk_soc_init = omap3430_clk_legacy_init; - } } void __init omap3430_init_early(void) { omap3_init_early(); - if (of_have_populated_dt()) - omap_clk_soc_init = omap3430_dt_clk_init; + omap_clk_soc_init = omap3430_dt_clk_init; } void __init omap35xx_init_early(void) { omap3_init_early(); - if (of_have_populated_dt()) - omap_clk_soc_init = omap3430_dt_clk_init; + omap_clk_soc_init = omap3430_dt_clk_init; } void __init omap3630_init_early(void) { omap3_init_early(); - if (of_have_populated_dt()) - omap_clk_soc_init = omap3630_dt_clk_init; + omap_clk_soc_init = omap3630_dt_clk_init; } void __init am35xx_init_early(void) { omap3_init_early(); - if (of_have_populated_dt()) - omap_clk_soc_init = am35xx_dt_clk_init; + omap_clk_soc_init = am35xx_dt_clk_init; } void __init omap3_init_late(void) @@ -628,8 +600,7 @@ void __init ti816x_init_early(void) ti816x_clockdomains_init(); dm816x_hwmod_init(); omap_hwmod_init_postsetup(); - if (of_have_populated_dt()) - omap_clk_soc_init = dm816x_dt_clk_init; + omap_clk_soc_init = dm816x_dt_clk_init; } #endif @@ -785,21 +756,19 @@ int __init omap_clk_init(void) omap2_clk_setup_ll_ops(); - if (of_have_populated_dt()) { - ret = omap_control_init(); - if (ret) - return ret; + ret = omap_control_init(); + if (ret) + return ret; - ret = omap_prcm_init(); - if (ret) - return ret; + ret = omap_prcm_init(); + if (ret) + return ret; - of_clk_init(NULL); + of_clk_init(NULL); - ti_dt_clk_init_retry_clks(); + ti_dt_clk_init_retry_clks(); - ti_dt_clockdomains_setup(); - } + ti_dt_clockdomains_setup(); ret = omap_clk_soc_init(); -- cgit v1.2.3 From 2a26d31b1bae5d07b97fc05755053295da686ec7 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 31 May 2017 15:51:36 -0700 Subject: ARM: OMAP2+: Remove unused legacy code for PRM We are now booting all mach-omap2 in device tree only mode. Any code that is only called in legacy boot mode where of_have_populated_dt() is not set is safe to remove now. Reviewed-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/prm3xxx.c | 17 +++++------- arch/arm/mach-omap2/prm44xx.c | 59 ---------------------------------------- arch/arm/mach-omap2/prm_common.c | 9 ++---- 3 files changed, 10 insertions(+), 75 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c index 718981bb80cd..395cf43b5c5e 100644 --- a/arch/arm/mach-omap2/prm3xxx.c +++ b/arch/arm/mach-omap2/prm3xxx.c @@ -690,6 +690,8 @@ static const struct of_device_id omap3_prm_dt_match_table[] = { static int omap3xxx_prm_late_init(void) { + struct device_node *np; + int irq_num; int ret; if (!(prm_features & PRM_HAS_IO_WAKEUP)) @@ -702,16 +704,11 @@ static int omap3xxx_prm_late_init(void) omap3_prcm_irq_setup.reconfigure_io_chain = omap3430_pre_es3_1_reconfigure_io_chain; - if (of_have_populated_dt()) { - struct device_node *np; - int irq_num; - - np = of_find_matching_node(NULL, omap3_prm_dt_match_table); - if (np) { - irq_num = of_irq_get(np, 0); - if (irq_num >= 0) - omap3_prcm_irq_setup.irq = irq_num; - } + np = of_find_matching_node(NULL, omap3_prm_dt_match_table); + if (np) { + irq_num = of_irq_get(np, 0); + if (irq_num >= 0) + omap3_prcm_irq_setup.irq = irq_num; } omap3xxx_prm_enable_io_wakeup(); diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index 30768003f854..b045f974dc47 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -336,27 +336,6 @@ static void omap44xx_prm_reconfigure_io_chain(void) return; } -/** - * omap44xx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches - * - * Activates the I/O wakeup event latches and allows events logged by - * those latches to signal a wakeup event to the PRCM. For I/O wakeups - * to occur, WAKEUPENABLE bits must be set in the pad mux registers, and - * omap44xx_prm_reconfigure_io_chain() must be called. No return value. - */ -static void __init omap44xx_prm_enable_io_wakeup(void) -{ - s32 inst = omap4_prmst_get_prm_dev_inst(); - - if (inst == PRM_INSTANCE_UNKNOWN) - return; - - omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK, - OMAP4430_GLOBAL_WUEN_MASK, - inst, - omap4_prcm_irq_setup.pm_ctrl); -} - /** * omap44xx_prm_read_reset_sources - return the last SoC reset source * @@ -689,8 +668,6 @@ struct pwrdm_ops omap4_pwrdm_operations = { .pwrdm_has_voltdm = omap4_check_vcvp, }; -static int omap44xx_prm_late_init(void); - /* * XXX document */ @@ -698,7 +675,6 @@ static struct prm_ll_data omap44xx_prm_ll_data = { .read_reset_sources = &omap44xx_prm_read_reset_sources, .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old, .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old, - .late_init = &omap44xx_prm_late_init, .assert_hardreset = omap4_prminst_assert_hardreset, .deassert_hardreset = omap4_prminst_deassert_hardreset, .is_hardreset_asserted = omap4_prminst_is_hardreset_asserted, @@ -735,41 +711,6 @@ int __init omap44xx_prm_init(const struct omap_prcm_init_data *data) return prm_register(&omap44xx_prm_ll_data); } -static int omap44xx_prm_late_init(void) -{ - int irq_num; - - if (!(prm_features & PRM_HAS_IO_WAKEUP)) - return 0; - - /* OMAP4+ is DT only now */ - if (!of_have_populated_dt()) - return 0; - - irq_num = of_irq_get(prm_init_data->np, 0); - /* - * Already have OMAP4 IRQ num. For all other platforms, we need - * IRQ numbers from DT - */ - if (irq_num < 0 && !(prm_init_data->flags & PRM_IRQ_DEFAULT)) { - if (irq_num == -EPROBE_DEFER) - return irq_num; - - /* Have nothing to do */ - return 0; - } - - /* Once OMAP4 DT is filled as well */ - if (irq_num >= 0) { - omap4_prcm_irq_setup.irq = irq_num; - omap4_prcm_irq_setup.xlate_irq = NULL; - } - - omap44xx_prm_enable_io_wakeup(); - - return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup); -} - static void __exit omap44xx_prm_exit(void) { prm_unregister(&omap44xx_prm_ll_data); diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index 2b138b65129a..538980ee20d4 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -267,10 +267,9 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup) { int nr_regs; u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG]; - int offset, i; + int offset, i, irq; struct irq_chip_generic *gc; struct irq_chip_type *ct; - unsigned int irq; if (!irq_setup) return -EINVAL; @@ -344,10 +343,8 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup) prcm_irq_chips[i] = gc; } - if (of_have_populated_dt()) { - int irq = omap_prcm_event_to_irq("io"); - omap_pcs_legacy_init(irq, irq_setup->reconfigure_io_chain); - } + irq = omap_prcm_event_to_irq("io"); + omap_pcs_legacy_init(irq, irq_setup->reconfigure_io_chain); return 0; -- cgit v1.2.3 From 1aa8f0cb19e59a0def9925d401d628c1846c3270 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 31 May 2017 15:51:37 -0700 Subject: ARM: OMAP2+: Remove unused legacy code for interconnects We are now booting all mach-omap2 in device tree only mode. Any code that is only called in legacy boot mode where of_have_populated_dt() is not set is safe to remove now. Reviewed-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_device.c | 5 +---- arch/arm/mach-omap2/omap_hwmod.c | 23 ++++++++++------------- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 3 +-- 3 files changed, 12 insertions(+), 19 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index f989145480c8..ef9ffb8ac912 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -65,7 +65,7 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias, r = clk_get_sys(NULL, clk_name); - if (IS_ERR(r) && of_have_populated_dt()) { + if (IS_ERR(r)) { struct of_phandle_args clkspec; clkspec.np = of_find_node_by_name(NULL, clk_name); @@ -953,9 +953,6 @@ static int __init omap_device_late_init(void) { bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle); - WARN(!of_have_populated_dt(), - "legacy booting deprecated, please update to boot with .dts\n"); - return 0; } omap_late_initcall_sync(omap_device_late_init); diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 8bcea0d83fa0..0f7afdaf80d3 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -2334,24 +2334,21 @@ static int __init _init(struct omap_hwmod *oh, void *data) { int r, index; struct device_node *np = NULL; + struct device_node *bus; if (oh->_state != _HWMOD_STATE_REGISTERED) return 0; - if (of_have_populated_dt()) { - struct device_node *bus; - - bus = of_find_node_by_name(NULL, "ocp"); - if (!bus) - return -ENODEV; + bus = of_find_node_by_name(NULL, "ocp"); + if (!bus) + return -ENODEV; - r = of_dev_hwmod_lookup(bus, oh, &index, &np); - if (r) - pr_debug("omap_hwmod: %s missing dt data\n", oh->name); - else if (np && index) - pr_warn("omap_hwmod: %s using broken dt data from %s\n", - oh->name, np->name); - } + r = of_dev_hwmod_lookup(bus, oh, &index, &np); + if (r) + pr_debug("omap_hwmod: %s missing dt data\n", oh->name); + else if (np && index) + pr_warn("omap_hwmod: %s using broken dt data from %s\n", + oh->name, np->name); r = _init_mpu_rt_base(oh, NULL, index, np); if (r < 0) { diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 1c6ca4d5fa2d..c3276436b0ae 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -3204,8 +3204,7 @@ int __init omap3xxx_hwmod_init(void) * If DT information is missing, enable them only for GP devices. */ - if (of_have_populated_dt()) - bus = of_find_node_by_name(NULL, "ocp"); + bus = of_find_node_by_name(NULL, "ocp"); if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) { r = omap_hwmod_register_links(h_sham); -- cgit v1.2.3 From 279ebec8f4721d6d3eaacfa218110df508618e2c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 31 May 2017 15:51:38 -0700 Subject: ARM: OMAP2+: Remove unused legacy code for watchdog We are now booting all mach-omap2 in device tree only mode. Any code that is only called in legacy boot mode where of_have_populated_dt() is not set is safe to remove now. Reviewed-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/wd_timer.c | 28 ---------------------------- 1 file changed, 28 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c index ff0a68cf7439..0084b6c77cf1 100644 --- a/arch/arm/mach-omap2/wd_timer.c +++ b/arch/arm/mach-omap2/wd_timer.c @@ -102,31 +102,3 @@ int omap2_wd_timer_reset(struct omap_hwmod *oh) return (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : omap2_wd_timer_disable(oh); } - -static int __init omap_init_wdt(void) -{ - int id = -1; - struct platform_device *pdev; - struct omap_hwmod *oh; - char *oh_name = "wd_timer2"; - char *dev_name = "omap_wdt"; - struct omap_wd_timer_platform_data pdata; - - if (!cpu_class_is_omap2() || of_have_populated_dt()) - return 0; - - oh = omap_hwmod_lookup(oh_name); - if (!oh) { - pr_err("Could not look up wd_timer%d hwmod\n", id); - return -EINVAL; - } - - pdata.read_reset_sources = prm_read_reset_sources; - - pdev = omap_device_build(dev_name, id, oh, &pdata, - sizeof(struct omap_wd_timer_platform_data)); - WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n", - dev_name, oh->name); - return 0; -} -omap_subsys_initcall(omap_init_wdt); -- cgit v1.2.3 From 0e78b1218df37f1a1834dff853d967444e332bab Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 31 May 2017 15:51:39 -0700 Subject: ARM: OMAP2+: Remove unused legacy code for n8x0 We are now booting all mach-omap2 in device tree only mode. Any code that is only called in legacy boot mode where of_have_populated_dt() is not set is safe to remove now. Reviewed-by: Sebastian Reichel [tony@atomide.com: left out probe changes to avoid merge conflict] Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-n8x0.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 91272db09fa3..20f25539d572 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -53,14 +53,12 @@ static u32 board_caps; static void board_check_revision(void) { - if (of_have_populated_dt()) { - if (of_machine_is_compatible("nokia,n800")) - board_caps = NOKIA_N800; - else if (of_machine_is_compatible("nokia,n810")) - board_caps = NOKIA_N810; - else if (of_machine_is_compatible("nokia,n810-wimax")) - board_caps = NOKIA_N810_WIMAX; - } + if (of_machine_is_compatible("nokia,n800")) + board_caps = NOKIA_N800; + else if (of_machine_is_compatible("nokia,n810")) + board_caps = NOKIA_N810; + else if (of_machine_is_compatible("nokia,n810-wimax")) + board_caps = NOKIA_N810_WIMAX; if (!board_caps) pr_err("Unknown board\n"); -- cgit v1.2.3 From 1800e6dd2c99649efcfbd40c37288c163089df69 Mon Sep 17 00:00:00 2001 From: Yannick Fertre Date: Thu, 8 Jun 2017 11:56:16 +0200 Subject: ARM: configs: stm32: Add watchdog support in STM32 defconfig This patch adds STM32 watchdog support in stm32_defconfig file Signed-off-by: Yannick Fertre Signed-off-by: Alexandre TORGUE --- arch/arm/configs/stm32_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index a0975386a96c..0a9fdcbea32e 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -52,6 +52,7 @@ CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_STM32F4=y # CONFIG_HWMON is not set +CONFIG_WATCHDOG=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_USB_SUPPORT is not set -- cgit v1.2.3 From d81cd7d72f6441df759c3db7adc69f4ad8d54fc4 Mon Sep 17 00:00:00 2001 From: Hugues Fruchet Date: Fri, 5 May 2017 17:31:00 +0200 Subject: ARM: configs: stm32: STMPE1600 GPIO expander Enable STMPE1600 GPIO expander. Signed-off-by: Hugues Fruchet Signed-off-by: Alexandre TORGUE --- arch/arm/configs/stm32_defconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index 0a9fdcbea32e..90e5c46913a5 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -54,6 +54,8 @@ CONFIG_I2C_STM32F4=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y CONFIG_REGULATOR=y +CONFIG_GPIO_STMPE=y +CONFIG_MFD_STMPE=y CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_USB_SUPPORT is not set CONFIG_NEW_LEDS=y -- cgit v1.2.3 From 13132b3f44d3600983aceb7e9920b8ebb55a7cf8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 1 Jun 2017 12:27:00 +0200 Subject: ARM: dts: armadillo800eva: Split LCD mux and gpio Configuration of the lcd0 pinmux group and GPIO hog for the external GPIO mux are done using a single device node, causing the "output-high" property to be applied to both. This will fail for the pinmux group, but doesn't cause any harm, as the failure is ignored silently. However, after "pinctrl: sh-pfc: propagate errors on group config", the failure will become fatal, leading to a broken display: sh-pfc e6050000.pin-controller: pin_config_group_set op failed for group 102 sh-pfc e6050000.pin-controller: Error applying setting, reverse things back sh-pfc e6050000.pin-controller: failed to select default state Move the GPIO hog to its own node to fix this. Fixes: ffd2f9a5afb730b9 ("ARM: shmobile: armadillo800eva dts: Add pinctrl and gpio-hog for lcdc0") Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7740-armadillo800eva.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts index 7885075428bb..1788e186a512 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts @@ -266,7 +266,9 @@ lcd0_pins: lcd0 { groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync"; function = "lcd0"; + }; + lcd0_mux { /* DBGMD/LCDC0/FSIA MUX */ gpio-hog; gpios = <176 0>; -- cgit v1.2.3 From 2227e43930278a53054046f9746cba69a1379639 Mon Sep 17 00:00:00 2001 From: Christoffer Dall Date: Tue, 2 May 2017 15:17:59 +0200 Subject: KVM: arm: Handle VCPU device attributes in guest.c As we are about to support VCPU attributes to set the timer IRQ numbers in guest.c, move the static inlines for the VCPU attributes handlers from the header file to guest.c. Signed-off-by: Christoffer Dall Acked-by: Marc Zyngier --- arch/arm/include/asm/kvm_host.h | 22 +++++++-------------- arch/arm/kvm/guest.c | 42 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+), 15 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h index 00ad56ee6455..127e2dd2e21c 100644 --- a/arch/arm/include/asm/kvm_host.h +++ b/arch/arm/include/asm/kvm_host.h @@ -291,20 +291,12 @@ static inline void kvm_arm_init_debug(void) {} static inline void kvm_arm_setup_debug(struct kvm_vcpu *vcpu) {} static inline void kvm_arm_clear_debug(struct kvm_vcpu *vcpu) {} static inline void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu) {} -static inline int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, - struct kvm_device_attr *attr) -{ - return -ENXIO; -} -static inline int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, - struct kvm_device_attr *attr) -{ - return -ENXIO; -} -static inline int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, - struct kvm_device_attr *attr) -{ - return -ENXIO; -} + +int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr); +int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr); +int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr); #endif /* __ARM_KVM_HOST_H__ */ diff --git a/arch/arm/kvm/guest.c b/arch/arm/kvm/guest.c index fa6182a40941..acea05e9db4e 100644 --- a/arch/arm/kvm/guest.c +++ b/arch/arm/kvm/guest.c @@ -301,3 +301,45 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, { return -EINVAL; } + +int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr) +{ + int ret; + + switch (attr->group) { + default: + ret = -ENXIO; + break; + } + + return ret; +} + +int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr) +{ + int ret; + + switch (attr->group) { + default: + ret = -ENXIO; + break; + } + + return ret; +} + +int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr) +{ + int ret; + + switch (attr->group) { + default: + ret = -ENXIO; + break; + } + + return ret; +} -- cgit v1.2.3 From 85e69ad7f2cc6dd829987a70cf32785b1d8c8b27 Mon Sep 17 00:00:00 2001 From: Christoffer Dall Date: Tue, 2 May 2017 20:14:06 +0200 Subject: KVM: arm/arm64: Move timer IRQ default init to arch_timer.c We currently initialize the arch timer IRQ numbers from the reset code, presumably because we once intended to model multiple CPU or SoC types from within the kernel and have hard-coded reset values in the reset code. As we are moving towards userspace being in charge of more fine-grained CPU emulation and stitching together the pieces needed to emulate a particular type of CPU, we should no longer have a tight coupling between resetting a VCPU and setting IRQ numbers. Therefore, move the logic to define and use the default IRQ numbers to the timer code and set the IRQ number immediately when creating the VCPU. Signed-off-by: Christoffer Dall Reviewed-by: Marc Zyngier --- arch/arm/kvm/reset.c | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kvm/reset.c b/arch/arm/kvm/reset.c index 1da8b2d14550..5ed0c3ee33d6 100644 --- a/arch/arm/kvm/reset.c +++ b/arch/arm/kvm/reset.c @@ -37,16 +37,6 @@ static struct kvm_regs cortexa_regs_reset = { .usr_regs.ARM_cpsr = SVC_MODE | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT, }; -static const struct kvm_irq_level cortexa_ptimer_irq = { - { .irq = 30 }, - .level = 1, -}; - -static const struct kvm_irq_level cortexa_vtimer_irq = { - { .irq = 27 }, - .level = 1, -}; - /******************************************************************************* * Exported reset function @@ -62,16 +52,12 @@ static const struct kvm_irq_level cortexa_vtimer_irq = { int kvm_reset_vcpu(struct kvm_vcpu *vcpu) { struct kvm_regs *reset_regs; - const struct kvm_irq_level *cpu_vtimer_irq; - const struct kvm_irq_level *cpu_ptimer_irq; switch (vcpu->arch.target) { case KVM_ARM_TARGET_CORTEX_A7: case KVM_ARM_TARGET_CORTEX_A15: reset_regs = &cortexa_regs_reset; vcpu->arch.midr = read_cpuid_id(); - cpu_vtimer_irq = &cortexa_vtimer_irq; - cpu_ptimer_irq = &cortexa_ptimer_irq; break; default: return -ENODEV; @@ -84,5 +70,5 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) kvm_reset_coprocs(vcpu); /* Reset arch_timer context */ - return kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq, cpu_ptimer_irq); + return kvm_timer_vcpu_reset(vcpu); } -- cgit v1.2.3 From 99a1db7a2c9b2ecb9a801cee3f6a7a71945a2fca Mon Sep 17 00:00:00 2001 From: Christoffer Dall Date: Tue, 2 May 2017 20:19:15 +0200 Subject: KVM: arm/arm64: Allow setting the timer IRQ numbers from userspace First we define an ABI using the vcpu devices that lets userspace set the interrupt numbers for the various timers on both the 32-bit and 64-bit KVM/ARM implementations. Second, we add the definitions for the groups and attributes introduced by the above ABI. (We add the PMU define on the 32-bit side as well for symmetry and it may get used some day.) Third, we set up the arch-specific vcpu device operation handlers to call into the timer code for anything related to the KVM_ARM_VCPU_TIMER_CTRL group. Fourth, we implement support for getting and setting the timer interrupt numbers using the above defined ABI in the arch timer code. Fifth, we introduce error checking upon enabling the arch timer (which is called when first running a VCPU) to check that all VCPUs are configured to use the same PPI for the timer (as mandated by the architecture) and that the virtual and physical timers are not configured to use the same IRQ number. Signed-off-by: Christoffer Dall Reviewed-by: Marc Zyngier --- arch/arm/include/uapi/asm/kvm.h | 8 ++++++++ arch/arm/kvm/guest.c | 9 +++++++++ 2 files changed, 17 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h index 5e3c673fa3f4..5db2d4c6a55f 100644 --- a/arch/arm/include/uapi/asm/kvm.h +++ b/arch/arm/include/uapi/asm/kvm.h @@ -203,6 +203,14 @@ struct kvm_arch_memory_slot { #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff #define VGIC_LEVEL_INFO_LINE_LEVEL 0 +/* Device Control API on vcpu fd */ +#define KVM_ARM_VCPU_PMU_V3_CTRL 0 +#define KVM_ARM_VCPU_PMU_V3_IRQ 0 +#define KVM_ARM_VCPU_PMU_V3_INIT 1 +#define KVM_ARM_VCPU_TIMER_CTRL 1 +#define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 +#define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 + #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 #define KVM_DEV_ARM_ITS_SAVE_TABLES 1 #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 diff --git a/arch/arm/kvm/guest.c b/arch/arm/kvm/guest.c index acea05e9db4e..1e0784ebbfd6 100644 --- a/arch/arm/kvm/guest.c +++ b/arch/arm/kvm/guest.c @@ -308,6 +308,9 @@ int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, int ret; switch (attr->group) { + case KVM_ARM_VCPU_TIMER_CTRL: + ret = kvm_arm_timer_set_attr(vcpu, attr); + break; default: ret = -ENXIO; break; @@ -322,6 +325,9 @@ int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, int ret; switch (attr->group) { + case KVM_ARM_VCPU_TIMER_CTRL: + ret = kvm_arm_timer_get_attr(vcpu, attr); + break; default: ret = -ENXIO; break; @@ -336,6 +342,9 @@ int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, int ret; switch (attr->group) { + case KVM_ARM_VCPU_TIMER_CTRL: + ret = kvm_arm_timer_has_attr(vcpu, attr); + break; default: ret = -ENXIO; break; -- cgit v1.2.3 From bc03ce08396786c92d6591a81682c7da7accbfc8 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Mon, 29 May 2017 07:51:19 +0300 Subject: ARM: dts: at91: sama5d2_xplained: remove wrong memory node The size field of the memory node is wrong. Rely on the default value in sama5d2.dtsi that happens to be correct for the SAMA5D2 Xplained board. Signed-off-by: Baruch Siach Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index dbce6f7a73dd..2e2c3d1a1fa2 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -56,10 +56,6 @@ stdout-path = "serial0:115200n8"; }; - memory { - reg = <0x20000000 0x80000>; - }; - clocks { slow_xtal { clock-frequency = <32768>; -- cgit v1.2.3 From 9cc91f212111cdcbefa02dcdb7dd443f224bf52c Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 8 Jun 2017 10:53:10 +0200 Subject: xen: avoid type warning in xchg_xen_ulong The improved type-checking version of container_of() triggers a warning for xchg_xen_ulong, pointing out that 'xen_ulong_t' is unsigned, but atomic64_t contains a signed value: drivers/xen/events/events_2l.c: In function 'evtchn_2l_handle_events': drivers/xen/events/events_2l.c:187:1020: error: call to '__compiletime_assert_187' declared with attribute error: pointer type mismatch in container_of() This adds a cast to work around the warning. Cc: Ian Abbott Fixes: 85323a991d40 ("xen: arm: mandate EABI and use generic atomic operations.") Fixes: daa2ac80834d ("kernel.h: handle pointers to arrays better in container_of()") Signed-off-by: Arnd Bergmann Signed-off-by: Stefano Stabellini Reviewed-by: Stefano Stabellini Acked-by: Ian Abbott --- arch/arm/include/asm/xen/events.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/xen/events.h b/arch/arm/include/asm/xen/events.h index 71e473d05fcc..620dc75362e5 100644 --- a/arch/arm/include/asm/xen/events.h +++ b/arch/arm/include/asm/xen/events.h @@ -16,7 +16,7 @@ static inline int xen_irqs_disabled(struct pt_regs *regs) return raw_irqs_disabled_flags(regs->ARM_cpsr); } -#define xchg_xen_ulong(ptr, val) atomic64_xchg(container_of((ptr), \ +#define xchg_xen_ulong(ptr, val) atomic64_xchg(container_of((long long*)(ptr),\ atomic64_t, \ counter), (val)) -- cgit v1.2.3 From 71d1e5d71cec76e927a92354a7eb9d476e7054ad Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 6 Jun 2017 14:14:16 +0200 Subject: arm: ecard: use dev_groups and not dev_attrs for bus_type The dev_attrs field has long been "depreciated" and is finally being removed, so move the driver to use the "correct" dev_groups field instead for struct bus_type. Cc: Russell King Cc: Signed-off-by: Greg Kroah-Hartman --- arch/arm/mach-rpc/ecard.c | 40 +++++++++++++++++++++++----------------- 1 file changed, 23 insertions(+), 17 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-rpc/ecard.c b/arch/arm/mach-rpc/ecard.c index 6b279d037774..f75b8b562d57 100644 --- a/arch/arm/mach-rpc/ecard.c +++ b/arch/arm/mach-rpc/ecard.c @@ -761,19 +761,21 @@ static struct expansion_card *__init ecard_alloc_card(int type, int slot) return ec; } -static ssize_t ecard_show_irq(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t irq_show(struct device *dev, struct device_attribute *attr, char *buf) { struct expansion_card *ec = ECARD_DEV(dev); return sprintf(buf, "%u\n", ec->irq); } +static DEVICE_ATTR_RO(irq); -static ssize_t ecard_show_dma(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t dma_show(struct device *dev, struct device_attribute *attr, char *buf) { struct expansion_card *ec = ECARD_DEV(dev); return sprintf(buf, "%u\n", ec->dma); } +static DEVICE_ATTR_RO(dma); -static ssize_t ecard_show_resources(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t resource_show(struct device *dev, struct device_attribute *attr, char *buf) { struct expansion_card *ec = ECARD_DEV(dev); char *str = buf; @@ -787,35 +789,39 @@ static ssize_t ecard_show_resources(struct device *dev, struct device_attribute return str - buf; } +static DEVICE_ATTR_RO(resource_show) -static ssize_t ecard_show_vendor(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t vendor_show(struct device *dev, struct device_attribute *attr, char *buf) { struct expansion_card *ec = ECARD_DEV(dev); return sprintf(buf, "%u\n", ec->cid.manufacturer); } +static DEVICE_ATTR_RO(vendor); -static ssize_t ecard_show_device(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t device_show(struct device *dev, struct device_attribute *attr, char *buf) { struct expansion_card *ec = ECARD_DEV(dev); return sprintf(buf, "%u\n", ec->cid.product); } +static DEVICE_ATTR_RO(device); -static ssize_t ecard_show_type(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t type_show(struct device *dev, struct device_attribute *attr, char *buf) { struct expansion_card *ec = ECARD_DEV(dev); return sprintf(buf, "%s\n", ec->easi ? "EASI" : "IOC"); } - -static struct device_attribute ecard_dev_attrs[] = { - __ATTR(device, S_IRUGO, ecard_show_device, NULL), - __ATTR(dma, S_IRUGO, ecard_show_dma, NULL), - __ATTR(irq, S_IRUGO, ecard_show_irq, NULL), - __ATTR(resource, S_IRUGO, ecard_show_resources, NULL), - __ATTR(type, S_IRUGO, ecard_show_type, NULL), - __ATTR(vendor, S_IRUGO, ecard_show_vendor, NULL), - __ATTR_NULL, +static DEVICE_ATTR_RO(type); + +static struct attribute *ecard_dev_attrs[] = { + &dev_attr_device.attr, + &dev_attr_dma.attr, + &dev_attr_irq.attr, + &dev_attr_resource.attr, + &dev_attr_type.attr, + &dev_attr_vendor.attr, + NULL, }; - +ATTRIBUTE_GROUPS(ecard_dev); int ecard_request_resources(struct expansion_card *ec) { @@ -1120,7 +1126,7 @@ static int ecard_match(struct device *_dev, struct device_driver *_drv) struct bus_type ecard_bus_type = { .name = "ecard", - .dev_attrs = ecard_dev_attrs, + .dev_groups = ecard_dev_groups, .match = ecard_match, .probe = ecard_drv_probe, .remove = ecard_drv_remove, -- cgit v1.2.3 From 694ca10ca059812219a2841f3c385aca8f6a3b17 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 3 Jun 2017 22:44:27 +0800 Subject: ARM: sun8i: a83t: Add device node for R_PIO The A83T has 1 pingroup with 13 pins belonging to the R_PIO or special pin controller. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Acked-by: Linus Walleij --- arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 49aeb56970ba..bf63e3b77572 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -44,6 +44,8 @@ #include +#include + / { interrupt-parent = <&gic>; #address-cells = <1>; @@ -280,5 +282,18 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + r_pio: pinctrl@1f02c00 { + compatible = "allwinner,sun8i-a83t-r-pinctrl"; + reg = <0x01f02c00 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, + <&osc16Md512>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + }; }; }; -- cgit v1.2.3 From 13b23780cc514c28582edec1736b381465f08085 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 7 Jun 2017 09:16:00 +0200 Subject: ARM: dts: stm32: Add usart2_pins on stm32h743 Add usart2 pins definition in order to add usart2 support dedicated for console output on stm32h743i-disco board. Signed-off-by: Patrice Chotard Signed-off-by: Alexandre TORGUE --- arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi index fcc1e0640233..76bbd6575fae 100644 --- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi @@ -151,6 +151,19 @@ bias-disable; }; }; + + usart2_pins: usart2@0 { + pins1 { + pinmux = ; + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; + bias-disable; + }; + }; }; }; }; -- cgit v1.2.3 From a56678cd570405624a031f0c400305763ed308f2 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 7 Jun 2017 09:16:00 +0200 Subject: ARM: dts: stm32: Add usart2 support on stm32h743 This usart is used for console output on stm32h743i-disco board Signed-off-by: Patrice Chotard Signed-off-by: Alexandre TORGUE --- arch/arm/boot/dts/stm32h743.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 46856298ee16..36a99db0a3b4 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -68,6 +68,14 @@ }; + usart2: serial@40004400 { + compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + reg = <0x40004400 0x400>; + interrupts = <38>; + status = "disabled"; + clocks = <&timer_clk>; + }; + timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; -- cgit v1.2.3 From 437074645873d77e8958be4f7eeec66a69cf0077 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 7 Jun 2017 09:16:00 +0200 Subject: ARM: dts: stm32: Add stm32h743i-disco board Add basic support for stm32h743i-discovery board This board offers : _ 2MBytes Flash _ 1 x micro USB OTG port _ 1 x STLink connector (micro USB) _ 1 x micro SD card slot _ 1 x RJ45 connector _ 1 x RCA connector _ 2 x Audio jack connectors (in and out) _ 2 x speaker connectors (left and right) _ 1 x joystick _ 1 x DCMI connector (Digital camera interface) _ 1 x 4 inch DSI LCD (Display Serial Interface) _ Arduino Uno Connectors _ 2 x PIO connectors (PMOD and PMOD+) _ 1 x wakeup button _ 1 x reset button Signed-off-by: Patrice Chotard Signed-off-by: Alexandre TORGUE --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/stm32h743i-disco.dts | 73 ++++++++++++++++++++++++++++++++++ 2 files changed, 75 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/stm32h743i-disco.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 828165479ab0..7697691b70df 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -794,7 +794,8 @@ dtb-$(CONFIG_ARCH_STM32)+= \ stm32f769-disco.dtb \ stm32429i-eval.dtb \ stm32746g-eval.dtb \ - stm32h743i-eval.dtb + stm32h743i-eval.dtb \ + stm32h743i-disco.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ sun4i-a10-ba10-tvbox.dtb \ diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/stm32h743i-disco.dts new file mode 100644 index 000000000000..79e841d94079 --- /dev/null +++ b/arch/arm/boot/dts/stm32h743i-disco.dts @@ -0,0 +1,73 @@ +/* + * Copyright 2017 - Patrice Chotard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "stm32h743.dtsi" +#include "stm32h743-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32H743i-Discovery board"; + compatible = "st,stm32h743i-disco", "st,stm32h743"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0xd0000000 0x2000000>; + }; + + aliases { + serial0 = &usart2; + }; +}; + +&clk_hse { + clock-frequency = <125000000>; +}; + +&usart2 { + pinctrl-0 = <&usart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; -- cgit v1.2.3 From 73f9de0c7f5dd9eae6949135a7b316cb02365519 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Tue, 23 May 2017 15:34:40 +0200 Subject: ARM: dts: uniphier: Add generic compatible string for I2C EEPROM The at24 driver allows to register I2C EEPROM chips using different vendor and devices, but the I2C subsystem does not take the vendor into account when matching using the I2C table since it only has device entries. But when matching using an OF table, both the vendor and device has to be taken into account so the driver defines only a set of compatible strings using the "atmel" vendor as a generic fallback for compatible I2C devices. So add this generic fallback to the device node compatible string to make the device to match the driver using the OF device ID table. Signed-off-by: Javier Martinez Canillas Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-pro4-ace.dts | 2 +- arch/arm/boot/dts/uniphier-pro4-sanji.dts | 2 +- arch/arm/boot/dts/uniphier-pxs2-gentil.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/uniphier-pro4-ace.dts b/arch/arm/boot/dts/uniphier-pro4-ace.dts index e45bf4f418b9..11690b57931c 100644 --- a/arch/arm/boot/dts/uniphier-pro4-ace.dts +++ b/arch/arm/boot/dts/uniphier-pro4-ace.dts @@ -52,7 +52,7 @@ status = "okay"; eeprom@54 { - compatible = "st,24c64"; + compatible = "st,24c64", "atmel,24c64"; reg = <0x54>; pagesize = <32>; }; diff --git a/arch/arm/boot/dts/uniphier-pro4-sanji.dts b/arch/arm/boot/dts/uniphier-pro4-sanji.dts index 18836886bc31..2763cebcd76a 100644 --- a/arch/arm/boot/dts/uniphier-pro4-sanji.dts +++ b/arch/arm/boot/dts/uniphier-pro4-sanji.dts @@ -47,7 +47,7 @@ status = "okay"; eeprom@54 { - compatible = "st,24c64"; + compatible = "st,24c64", "atmel,24c64"; reg = <0x54>; pagesize = <32>; }; diff --git a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts index bb39bd171d1a..81560f75bfa7 100644 --- a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts +++ b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts @@ -44,7 +44,7 @@ status = "okay"; eeprom@54 { - compatible = "st,24c64"; + compatible = "st,24c64", "atmel,24c64"; reg = <0x54>; pagesize = <32>; }; -- cgit v1.2.3 From 2dda2de5a1e1684aa4d31d0c2db42f6446a76a86 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 4 Jun 2017 20:33:40 +0200 Subject: arm: meson: select the clock controller for Meson8 Select COMMON_CLK_MESON8B also for MACH_MESON8 since the Meson8b clock controller driver can also be used on Meson8 SoCs now that we have a separate compatible for it. Signed-off-by: Martin Blumenstingl Acked-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm/mach-meson/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index b6e3acc63e14..ee30511849ca 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -21,6 +21,7 @@ config MACH_MESON8 bool "Amlogic Meson8 SoCs support" default ARCH_MESON select MESON6_TIMER + select COMMON_CLK_MESON8B config MACH_MESON8B bool "Amlogic Meson8b SoCs support" -- cgit v1.2.3 From 2c323c43a3d619d67bffa57dc7480cfae4c53300 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 4 Jun 2017 20:33:41 +0200 Subject: ARM: dts: meson8: add and use the real clock controller This removes the dummy clk81 gate and replaces it with the actual clock controller's CLKID_CLK81. This will also allow us to pass the real clock IDs to all devices where the clock is controlled by clkc in the future. Signed-off-by: Martin Blumenstingl Acked-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 6993077331c7..9b0b3ddbb17e 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -43,6 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include #include /include/ "meson.dtsi" @@ -82,13 +83,6 @@ reg = <0x203>; }; }; - - clk81: clk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <141666666>; - }; - }; /* end of / */ &aobus { @@ -126,6 +120,12 @@ }; &cbus { + clkc: clock-controller@4000 { + #clock-cells = <1>; + compatible = "amlogic,meson8-clkc"; + reg = <0x8000 0x4>, <0x4000 0x460>; + }; + pinctrl_cbus: pinctrl@9880 { compatible = "amlogic,meson8-cbus-pinctrl"; reg = <0x9880 0x10>; @@ -172,20 +172,20 @@ }; ðmac { - clocks = <&clk81>; + clocks = <&clkc CLKID_CLK81>; clock-names = "stmmaceth"; }; &i2c_AO { - clocks = <&clk81>; + clocks = <&clkc CLKID_CLK81>; }; &i2c_A { - clocks = <&clk81>; + clocks = <&clkc CLKID_CLK81>; }; &i2c_B { - clocks = <&clk81>; + clocks = <&clkc CLKID_CLK81>; }; &L2 { @@ -195,21 +195,21 @@ }; &spifc { - clocks = <&clk81>; + clocks = <&clkc CLKID_CLK81>; }; &uart_AO { - clocks = <&clk81>; + clocks = <&clkc CLKID_CLK81>; }; &uart_A { - clocks = <&clk81>; + clocks = <&clkc CLKID_CLK81>; }; &uart_B { - clocks = <&clk81>; + clocks = <&clkc CLKID_CLK81>; }; &uart_C { - clocks = <&clk81>; + clocks = <&clkc CLKID_CLK81>; }; -- cgit v1.2.3 From 7a78ef92cdc5813cab2c3a8ca2334eaaedc6818c Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 9 Jun 2017 23:34:36 +0800 Subject: ARM: sun8i: h3: Enable EMAC with external PHY on Orange Pi Plus 2E The Orange Pi Plus 2E, unlike the Orange Pi PC and PC Plus which its schematics are based on, uses an external Realtek RTL8211E PHY in RGMII mode, with a GPIO enabling the regulator for I/O signalling power supplies. The PHY's main power supply is enabled by the main 5V power supply. Add the regulator and PHY nodes, and override the PHY phandle under the EMAC node, so that the EMAC works properly on this board. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts index 5851a47a3089..80026f3caafc 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts @@ -50,4 +50,30 @@ / { model = "Xunlong Orange Pi Plus 2E"; compatible = "xunlong,orangepi-plus2e", "allwinner,sun8i-h3"; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ + }; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; }; -- cgit v1.2.3 From 1b8b02f0d084a2d9a966d5ae004d49c8e76aa8cc Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sat, 10 Jun 2017 14:31:21 +0200 Subject: arm: ecard: fix dev_groups patch typo Commit 71d1e5d71cec ("arm: ecard: use dev_groups and not dev_attrs for bus_type") had a typo in the resource attribute definition. Fix that up. Reported-by: kbuild test robot Fixes: 71d1e5d71cec ("arm: ecard: use dev_groups and not dev_attrs for bus_type") Cc: Russell King Cc: Signed-off-by: Greg Kroah-Hartman gregkh@linuxfoundation.org --- arch/arm/mach-rpc/ecard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-rpc/ecard.c b/arch/arm/mach-rpc/ecard.c index f75b8b562d57..5966964222b5 100644 --- a/arch/arm/mach-rpc/ecard.c +++ b/arch/arm/mach-rpc/ecard.c @@ -789,7 +789,7 @@ static ssize_t resource_show(struct device *dev, struct device_attribute *attr, return str - buf; } -static DEVICE_ATTR_RO(resource_show) +static DEVICE_ATTR_RO(resource) static ssize_t vendor_show(struct device *dev, struct device_attribute *attr, char *buf) { -- cgit v1.2.3 From bd5f62605f48fe32b66ebf9071b1155bad33670d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 8 Jun 2017 16:40:39 +0200 Subject: ARM: defconfig: Cleanup from old Kconfig options Remove old, dead Kconfig options (in order appearing in this commit): - EXPERIMENTAL is gone since v3.9; - INET_LRO: commit 7bbf3cae65b6 ("ipv4: Remove inet_lro library"); - MTD_CONCAT: commit f53fdebcc3e1 ("mtd: drop MTD_CONCAT from Kconfig entirely"); - MTD_PARTITIONS: commit 6a8a98b22b10 ("mtd: kill CONFIG_MTD_PARTITIONS"); - MTD_CHAR: commit 660685d9d1b4 ("mtd: merge mtdchar module with mtdcore"); - NETDEV_1000 and NETDEV_10000: commit f860b0522f65 ("drivers/net: Kconfig and Makefile cleanup"); NET_ETHERNET should be replaced with just ETHERNET but that is separate change; - INOTIFY: commit 2dfc1cae4c42 ("inotify: remove inotify in kernel interface"); - MISC_DEVICES: commit 7c5763b8453a ("drivers: misc: Remove MISC_DEVICES config option"); - HID_SUPPORT: commit 1f41a6a99476 ("HID: Fix the generic Kconfig options"); - BT_L2CAP and BT_SCO: commit f1e91e1640d8 ("Bluetooth: Always compile SCO and L2CAP in Bluetooth Core"); - DEBUG_ERRORS: commit b025a3f836d1 ("ARM: 6876/1: Kconfig.debug: Remove unused CONFIG_DEBUG_ERRORS"); - USB_DEVICE_CLASS: commit 007bab91324e ("USB: remove CONFIG_USB_DEVICE_CLASS"); - RCU_CPU_STALL_DETECTOR: commit a00e0d714fbd ("rcu: Remove conditional compilation for RCU CPU stall warnings"); - SYSCTL_SYSCALL_CHECK: commit 7c60c48f58a7 ("sysctl: Improve the sysctl sanity checks"); - IP_NF_QUEUE: commit 3dd6664fac7e ("netfilter: remove unused "config IP_NF_QUEUE""); - IP_NF_TARGET_ULOG: commit d4da843e6fad ("netfilter: kill remnants of ulog targets"); - IP6_NF_QUEUE: commit d16cf20e2f2f ("netfilter: remove ip_queue support"); - IP6_NF_TARGET_LOG: commit 6939c33a757b ("netfilter: merge ipt_LOG and ip6_LOG into xt_LOG"); - USB_LED: commit a335aaf3125c ("usb: misc: remove outdated USB LED driver"); - MMC_UNSAFE_RESUME: commit 2501c9179dff ("mmc: core: Use MMC_UNSAFE_RESUME as default behavior"); - AUTOFS_FS: commit 561c5cf9236a ("staging: Remove autofs3"); - DISPLAY_SUPPORT: commit 5a6b5e02d673 ("fbdev: remove display subsystem"); - CFG80211_REG_DEBUG: commit c799ba6eab7a ("cfg80211: remove CFG80211_REG_DEBUG"); - VIDEO_OUTPUT_CONTROL: commit f167a64e9d67 ("video / output: Drop display output class support"); - USB_LIBUSUAL: commit f61870ee6f8c ("usb: remove libusual"); - CRYPTO_ZLIB: commit 110492183c4b ("crypto: compress - remove unused pcomp interface"); - BLK_DEV_UB: commit 68a5059ecf82 ("block: remove the deprecated ub driver"); Signed-off-by: Krzysztof Kozlowski [for vexpress] Acked-by: Liviu Dudau Acked-by: Arnd Bergmann --- arch/arm/configs/acs5k_defconfig | 8 -------- arch/arm/configs/acs5k_tiny_defconfig | 10 ---------- arch/arm/configs/am200epdkit_defconfig | 7 ------- arch/arm/configs/assabet_defconfig | 3 --- arch/arm/configs/axm55xx_defconfig | 1 - arch/arm/configs/badge4_defconfig | 5 ----- arch/arm/configs/cerfcube_defconfig | 4 ---- arch/arm/configs/cm_x2xx_defconfig | 13 ------------- arch/arm/configs/cm_x300_defconfig | 10 ---------- arch/arm/configs/cns3420vb_defconfig | 7 ------- arch/arm/configs/colibri_pxa270_defconfig | 13 ------------- arch/arm/configs/colibri_pxa300_defconfig | 9 --------- arch/arm/configs/collie_defconfig | 4 ---- arch/arm/configs/corgi_defconfig | 13 ------------- arch/arm/configs/dove_defconfig | 1 - arch/arm/configs/ebsa110_defconfig | 1 - arch/arm/configs/efm32_defconfig | 1 - arch/arm/configs/em_x270_defconfig | 13 ------------- arch/arm/configs/ep93xx_defconfig | 1 - arch/arm/configs/eseries_pxa_defconfig | 8 -------- arch/arm/configs/ezx_defconfig | 18 ------------------ arch/arm/configs/footbridge_defconfig | 1 - arch/arm/configs/h5000_defconfig | 6 ------ arch/arm/configs/hackkit_defconfig | 3 --- arch/arm/configs/imote2_defconfig | 16 ---------------- arch/arm/configs/imx_v4_v5_defconfig | 1 - arch/arm/configs/iop13xx_defconfig | 4 ---- arch/arm/configs/iop32x_defconfig | 5 ----- arch/arm/configs/iop33x_defconfig | 6 ------ arch/arm/configs/ixp4xx_defconfig | 9 --------- arch/arm/configs/jornada720_defconfig | 8 -------- arch/arm/configs/ks8695_defconfig | 7 ------- arch/arm/configs/lart_defconfig | 3 --- arch/arm/configs/lpc18xx_defconfig | 1 - arch/arm/configs/lpd270_defconfig | 5 ----- arch/arm/configs/lubbock_defconfig | 4 ---- arch/arm/configs/magician_defconfig | 15 --------------- arch/arm/configs/mainstone_defconfig | 4 ---- arch/arm/configs/mini2440_defconfig | 19 ------------------- arch/arm/configs/mmp2_defconfig | 9 --------- arch/arm/configs/moxart_defconfig | 1 - arch/arm/configs/mps2_defconfig | 1 - arch/arm/configs/mv78xx0_defconfig | 8 -------- arch/arm/configs/mxs_defconfig | 1 - arch/arm/configs/neponset_defconfig | 4 ---- arch/arm/configs/netwinder_defconfig | 3 --- arch/arm/configs/netx_defconfig | 6 ------ arch/arm/configs/nhk8815_defconfig | 1 - arch/arm/configs/nuc910_defconfig | 7 ------- arch/arm/configs/nuc950_defconfig | 7 ------- arch/arm/configs/nuc960_defconfig | 7 ------- arch/arm/configs/omap1_defconfig | 2 -- arch/arm/configs/orion5x_defconfig | 2 -- arch/arm/configs/palmz72_defconfig | 6 ------ arch/arm/configs/pcm027_defconfig | 8 -------- arch/arm/configs/pleb_defconfig | 3 --- arch/arm/configs/pxa168_defconfig | 9 --------- arch/arm/configs/pxa255-idp_defconfig | 4 ---- arch/arm/configs/pxa3xx_defconfig | 9 --------- arch/arm/configs/pxa910_defconfig | 9 --------- arch/arm/configs/pxa_defconfig | 2 -- arch/arm/configs/qcom_defconfig | 1 - arch/arm/configs/raumfeld_defconfig | 11 ----------- arch/arm/configs/realview_defconfig | 1 - arch/arm/configs/rpc_defconfig | 6 ------ arch/arm/configs/s3c2410_defconfig | 11 ----------- arch/arm/configs/s3c6400_defconfig | 6 ------ arch/arm/configs/s5pv210_defconfig | 7 ------- arch/arm/configs/sama5_defconfig | 1 - arch/arm/configs/shannon_defconfig | 3 --- arch/arm/configs/simpad_defconfig | 7 ------- arch/arm/configs/spear13xx_defconfig | 4 ---- arch/arm/configs/spear3xx_defconfig | 4 ---- arch/arm/configs/spear6xx_defconfig | 3 --- arch/arm/configs/spitz_defconfig | 13 ------------- arch/arm/configs/sunxi_defconfig | 1 - arch/arm/configs/tct_hammer_defconfig | 7 ------- arch/arm/configs/trizeps4_defconfig | 8 -------- arch/arm/configs/u300_defconfig | 1 - arch/arm/configs/vexpress_defconfig | 1 - arch/arm/configs/viper_defconfig | 9 --------- arch/arm/configs/xcep_defconfig | 8 -------- arch/arm/configs/zeus_defconfig | 10 ---------- arch/arm/configs/zx_defconfig | 2 -- 84 files changed, 501 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/acs5k_defconfig b/arch/arm/configs/acs5k_defconfig index 92b0f90d1515..d04ee19e5b75 100644 --- a/arch/arm/configs/acs5k_defconfig +++ b/arch/arm/configs/acs5k_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y @@ -30,13 +29,9 @@ CONFIG_UNIX=y CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y -# CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y @@ -49,8 +44,6 @@ CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_ARM_KS8695_ETHER=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set CONFIG_PRISM54=m # CONFIG_INPUT_MOUSEDEV_PSAUX is not set # CONFIG_INPUT_KEYBOARD is not set @@ -69,7 +62,6 @@ CONFIG_KS8695_WATCHDOG=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_PCF8563=y CONFIG_EXT2_FS=y -CONFIG_INOTIFY=y CONFIG_TMPFS=y CONFIG_JFFS2_FS=y CONFIG_JFFS2_SUMMARY=y diff --git a/arch/arm/configs/acs5k_tiny_defconfig b/arch/arm/configs/acs5k_tiny_defconfig index 2a27a147463f..25c593df41d1 100644 --- a/arch/arm/configs/acs5k_tiny_defconfig +++ b/arch/arm/configs/acs5k_tiny_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y @@ -25,13 +24,9 @@ CONFIG_INET=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y @@ -40,12 +35,9 @@ CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_PHYSMAP=y # CONFIG_BLK_DEV is not set -# CONFIG_MISC_DEVICES is not set CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_ARM_KS8695_ETHER=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set # CONFIG_INPUT_MOUSEDEV_PSAUX is not set # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set @@ -62,11 +54,9 @@ CONFIG_GPIO_PCA953X=y CONFIG_WATCHDOG=y CONFIG_KS8695_WATCHDOG=y # CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_PCF8563=y -CONFIG_INOTIFY=y CONFIG_TMPFS=y CONFIG_JFFS2_FS=y CONFIG_JFFS2_SUMMARY=y diff --git a/arch/arm/configs/am200epdkit_defconfig b/arch/arm/configs/am200epdkit_defconfig index 113a5d815060..8c9b6ea46188 100644 --- a/arch/arm/configs/am200epdkit_defconfig +++ b/arch/arm/configs/am200epdkit_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_LOCALVERSION="gum" # CONFIG_SWAP is not set CONFIG_SYSVIPC=y @@ -30,12 +29,9 @@ CONFIG_INET=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m @@ -43,7 +39,6 @@ CONFIG_BT_HCIUART=m CONFIG_BT_HCIUART_H4=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y @@ -88,7 +83,6 @@ CONFIG_USB_ETH=m CONFIG_MMC=y CONFIG_MMC_PXA=y # CONFIG_DNOTIFY is not set -CONFIG_INOTIFY=y CONFIG_VFAT_FS=y CONFIG_JFFS2_FS=y CONFIG_JFFS2_COMPRESSION_OPTIONS=y @@ -101,7 +95,6 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_PREEMPT is not set # CONFIG_DEBUG_BUGVERBOSE is not set CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_CRYPTO=y CONFIG_CRYPTO_CBC=m CONFIG_CRYPTO_ECB=m diff --git a/arch/arm/configs/assabet_defconfig b/arch/arm/configs/assabet_defconfig index ab19ff1a0b71..04c86ff558da 100644 --- a/arch/arm/configs/assabet_defconfig +++ b/arch/arm/configs/assabet_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y @@ -22,9 +21,7 @@ CONFIG_IRDA=m CONFIG_IRLAN=m CONFIG_SA1100_FIR=m CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y diff --git a/arch/arm/configs/axm55xx_defconfig b/arch/arm/configs/axm55xx_defconfig index d3260d7d5af1..8e17e7ed1f02 100644 --- a/arch/arm/configs/axm55xx_defconfig +++ b/arch/arm/configs/axm55xx_defconfig @@ -74,7 +74,6 @@ CONFIG_IP_PNP_BOOTP=y CONFIG_INET_AH=y CONFIG_INET_ESP=y CONFIG_INET_IPCOMP=y -# CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_NETWORK_PHY_TIMESTAMPING=y CONFIG_BRIDGE=y diff --git a/arch/arm/configs/badge4_defconfig b/arch/arm/configs/badge4_defconfig index 2a604aa3195b..5ae5b5228467 100644 --- a/arch/arm/configs/badge4_defconfig +++ b/arch/arm/configs/badge4_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_EXPERT=y CONFIG_MODULES=y @@ -23,14 +22,11 @@ CONFIG_IRCOMM=y CONFIG_IRDA_ULTRA=y CONFIG_SA1100_FIR=y CONFIG_BT=m -CONFIG_BT_L2CAP=m CONFIG_BT_HCIUART=m CONFIG_BT_HCIVHCI=m # CONFIG_FW_LOADER is not set CONFIG_MTD=y CONFIG_MTD_DEBUG=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y @@ -113,5 +109,4 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_BUGVERBOSE is not set CONFIG_DEBUG_INFO=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/cerfcube_defconfig b/arch/arm/configs/cerfcube_defconfig index 57a2a18690b1..3f910bbf1bfd 100644 --- a/arch/arm/configs/cerfcube_defconfig +++ b/arch/arm/configs/cerfcube_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 @@ -29,10 +28,8 @@ CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y # CONFIG_IPV6 is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=m CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y @@ -70,5 +67,4 @@ CONFIG_NLS_ISO8859_1=m CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/cm_x2xx_defconfig b/arch/arm/configs/cm_x2xx_defconfig index 3b32d5fd9326..fb45b4983d3c 100644 --- a/arch/arm/configs/cm_x2xx_defconfig +++ b/arch/arm/configs/cm_x2xx_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y CONFIG_IKCONFIG=y @@ -39,12 +38,9 @@ CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y -# CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m CONFIG_BT_RFCOMM=m CONFIG_BT_BNEP=m CONFIG_BT_HIDP=m @@ -53,7 +49,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_FW_LOADER=m CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y @@ -69,7 +64,6 @@ CONFIG_MTD_NAND_CM_X270=y CONFIG_MTD_NAND_PLATFORM=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y -# CONFIG_MISC_DEVICES is not set CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_ATA=m @@ -82,8 +76,6 @@ CONFIG_DM9000_DEBUGLEVEL=1 CONFIG_NET_PCI=y CONFIG_8139TOO=m # CONFIG_8139TOO_PIO is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set CONFIG_PPP=m CONFIG_PPP_MULTILINK=y CONFIG_PPP_FILTER=y @@ -144,7 +136,6 @@ CONFIG_HID_SAMSUNG=y CONFIG_HID_SONY=y CONFIG_HID_SUNPLUS=y CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_MON=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_STORAGE=y @@ -160,7 +151,6 @@ CONFIG_RTC_DRV_V3020=y CONFIG_RTC_DRV_PXA=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y -CONFIG_INOTIFY=y CONFIG_VFAT_FS=m # CONFIG_PROC_PAGE_MONITOR is not set CONFIG_TMPFS=y @@ -179,10 +169,7 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_DETECT_SOFTLOCKUP is not set # CONFIG_SCHED_DEBUG is not set # CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y # CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set diff --git a/arch/arm/configs/cm_x300_defconfig b/arch/arm/configs/cm_x300_defconfig index 7df040e91c1c..c0418e03d180 100644 --- a/arch/arm/configs/cm_x300_defconfig +++ b/arch/arm/configs/cm_x300_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_LOCALVERSION="-cm-x300" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y @@ -35,12 +34,9 @@ CONFIG_IP_PNP_RARP=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_BT=m -CONFIG_BT_L2CAP=y -CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m @@ -51,8 +47,6 @@ CONFIG_BT_HCIBTUSB=m CONFIG_LIB80211=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_PXA3xx=y @@ -66,8 +60,6 @@ CONFIG_NET_ETHERNET=y CONFIG_DM9000=y CONFIG_DM9000_DEBUGLEVEL=0 CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set # CONFIG_INPUT_MOUSEDEV_PSAUX is not set CONFIG_INPUT_EVDEV=y # CONFIG_KEYBOARD_ATKBD is not set @@ -129,7 +121,6 @@ CONFIG_HID_TOPSEED=y CONFIG_HID_THRUSTMASTER=y CONFIG_HID_ZEROPLUS=y CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_MON=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_STORAGE=y @@ -165,7 +156,6 @@ CONFIG_NLS_ISO8859_1=m CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y # CONFIG_SCHED_DEBUG is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y # CONFIG_FTRACE is not set CONFIG_DEBUG_USER=y CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/cns3420vb_defconfig b/arch/arm/configs/cns3420vb_defconfig index b1ff5cdba9a1..63a953d855a6 100644 --- a/arch/arm/configs/cns3420vb_defconfig +++ b/arch/arm/configs/cns3420vb_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set # CONFIG_SWAP is not set CONFIG_SYSVIPC=y @@ -31,9 +30,7 @@ CONFIG_CMDLINE="console=ttyS0,38400 mem=128M root=/dev/mmcblk0p1 ro rootwait" CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FIRMWARE_IN_KERNEL is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_AMDSTD=y @@ -41,7 +38,6 @@ CONFIG_MTD_PHYSMAP=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=20000 -# CONFIG_MISC_DEVICES is not set CONFIG_BLK_DEV_SD=y CONFIG_ATA=y # CONFIG_SATA_PMP is not set @@ -56,20 +52,17 @@ CONFIG_LEGACY_PTY_COUNT=16 # CONFIG_HW_RANDOM is not set # CONFIG_HWMON is not set # CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y -CONFIG_INOTIFY=y CONFIG_AUTOFS4_FS=y CONFIG_FSCACHE=y CONFIG_TMPFS=y # CONFIG_ENABLE_WARN_DEPRECATED is not set # CONFIG_ENABLE_MUST_CHECK is not set CONFIG_DEBUG_FS=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_ARM_UNWIND is not set CONFIG_CRC_CCITT=y diff --git a/arch/arm/configs/colibri_pxa270_defconfig b/arch/arm/configs/colibri_pxa270_defconfig index 3146ad055716..8995695fc118 100644 --- a/arch/arm/configs/colibri_pxa270_defconfig +++ b/arch/arm/configs/colibri_pxa270_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y @@ -32,10 +31,8 @@ CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y -# CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_NETFILTER=y -CONFIG_IP_NF_QUEUE=m CONFIG_VLAN_8021Q=m CONFIG_IRDA=m CONFIG_IRLAN=m @@ -45,8 +42,6 @@ CONFIG_IRDA_CACHE_LAST_LSAP=y CONFIG_IRDA_FAST_RR=y CONFIG_IRTTY_SIR=m CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m @@ -57,8 +52,6 @@ CONFIG_CFG80211=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_CONNECTOR=y CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y @@ -87,8 +80,6 @@ CONFIG_NETDEVICES=y CONFIG_PHYLIB=y CONFIG_NET_ETHERNET=y CONFIG_DM9000=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set CONFIG_HOSTAP=y CONFIG_HOSTAP_FIRMWARE=y CONFIG_HOSTAP_FIRMWARE_NVRAM=y @@ -123,7 +114,6 @@ CONFIG_FONT_8x16=y CONFIG_LOGO=y # CONFIG_USB_HID is not set CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_SERIAL=m CONFIG_USB_GADGET=m CONFIG_USB_GADGET_DUMMY_HCD=y @@ -132,7 +122,6 @@ CONFIG_NEW_LEDS=y CONFIG_RTC_CLASS=y # CONFIG_RTC_HCTOSYS is not set CONFIG_RTC_DRV_PCF8583=m -CONFIG_INOTIFY=y CONFIG_AUTOFS4_FS=y CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m @@ -160,9 +149,7 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y CONFIG_KEYS=y CONFIG_SECURITY=y diff --git a/arch/arm/configs/colibri_pxa300_defconfig b/arch/arm/configs/colibri_pxa300_defconfig index be02fe2b14cb..d282e8b0bf33 100644 --- a/arch/arm/configs/colibri_pxa300_defconfig +++ b/arch/arm/configs/colibri_pxa300_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set @@ -14,18 +13,14 @@ CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y CONFIG_SYN_COOKIES=y -# CONFIG_INET_LRO is not set CONFIG_IPV6=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_MISC_DEVICES is not set CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_SG=y CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_AX88796=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set @@ -45,7 +40,6 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y -# CONFIG_HID_SUPPORT is not set CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_MON=y @@ -54,16 +48,13 @@ CONFIG_MMC=y # CONFIG_MMC_BLOCK_BOUNCE is not set CONFIG_MMC_PXA=y CONFIG_EXT3_FS=y -CONFIG_INOTIFY=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y CONFIG_ROOT_NFS=y CONFIG_PRINTK_TIME=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_AES=y diff --git a/arch/arm/configs/collie_defconfig b/arch/arm/configs/collie_defconfig index a8f3c596c39c..d398ae53aba7 100644 --- a/arch/arm/configs/collie_defconfig +++ b/arch/arm/configs/collie_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 @@ -26,8 +25,6 @@ CONFIG_UNIX=y CONFIG_INET=y # CONFIG_IPV6 is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y @@ -91,5 +88,4 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_DETECT_SOFTLOCKUP is not set CONFIG_DEBUG_MUTEXES=y # CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_ERRORS=y CONFIG_CRC_CCITT=y diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig index 462533bd84c6..09e1672777c9 100644 --- a/arch/arm/configs/corgi_defconfig +++ b/arch/arm/configs/corgi_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 @@ -33,26 +32,22 @@ CONFIG_UNIX=y CONFIG_XFRM_USER=m CONFIG_INET=y CONFIG_SYN_COOKIES=y -# CONFIG_INET_LRO is not set CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m CONFIG_IPV6_TUNNEL=m CONFIG_NETFILTER=y -CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m @@ -69,8 +64,6 @@ CONFIG_IRNET=m CONFIG_IRCOMM=m CONFIG_PXA_FICP=m CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m @@ -90,9 +83,7 @@ CONFIG_BT_HCIBTUART=m CONFIG_BT_HCIVHCI=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_ROM=y CONFIG_MTD_COMPLEX_MAPPINGS=y @@ -209,7 +200,6 @@ CONFIG_USB_EMI26=m CONFIG_USB_RIO500=m CONFIG_USB_LEGOTOWER=m CONFIG_USB_LCD=m -CONFIG_USB_LED=m CONFIG_USB_CYTHERM=m CONFIG_USB_IDMOUSE=m CONFIG_USB_GADGET=y @@ -221,7 +211,6 @@ CONFIG_USB_G_SERIAL=m CONFIG_MMC=y CONFIG_MMC_PXA=y CONFIG_EXT2_FS=y -CONFIG_INOTIFY=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y @@ -243,9 +232,7 @@ CONFIG_NLS_UTF8=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_PREEMPT is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_FTRACE is not set -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_TEST=m diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig index 701677f9248c..a93cc2fcf791 100644 --- a/arch/arm/configs/dove_defconfig +++ b/arch/arm/configs/dove_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y diff --git a/arch/arm/configs/ebsa110_defconfig b/arch/arm/configs/ebsa110_defconfig index 14559dbb4c2c..731a22a55f4e 100644 --- a/arch/arm/configs/ebsa110_defconfig +++ b/arch/arm/configs/ebsa110_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 diff --git a/arch/arm/configs/efm32_defconfig b/arch/arm/configs/efm32_defconfig index c0dac0f0f804..860d27138e6f 100644 --- a/arch/arm/configs/efm32_defconfig +++ b/arch/arm/configs/efm32_defconfig @@ -38,7 +38,6 @@ CONFIG_INET=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set diff --git a/arch/arm/configs/em_x270_defconfig b/arch/arm/configs/em_x270_defconfig index 8e10df7ba1b4..30a67523f860 100644 --- a/arch/arm/configs/em_x270_defconfig +++ b/arch/arm/configs/em_x270_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y CONFIG_IKCONFIG=y @@ -34,12 +33,9 @@ CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y -# CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m CONFIG_BT_RFCOMM=m CONFIG_BT_BNEP=m CONFIG_BT_HIDP=m @@ -49,7 +45,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_FW_LOADER=m CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y @@ -63,7 +58,6 @@ CONFIG_MTD_NAND=y CONFIG_MTD_NAND_PLATFORM=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y -# CONFIG_MISC_DEVICES is not set CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y # CONFIG_SCSI_LOWLEVEL is not set @@ -71,8 +65,6 @@ CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_DM9000=y CONFIG_DM9000_DEBUGLEVEL=1 -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set CONFIG_PPP=m CONFIG_PPP_MULTILINK=y CONFIG_PPP_FILTER=y @@ -144,7 +136,6 @@ CONFIG_HID_SAMSUNG=y CONFIG_HID_SONY=y CONFIG_HID_SUNPLUS=y CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_MON=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_STORAGE=y @@ -160,7 +151,6 @@ CONFIG_RTC_DRV_V3020=y CONFIG_RTC_DRV_PXA=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y -CONFIG_INOTIFY=y CONFIG_VFAT_FS=m # CONFIG_PROC_PAGE_MONITOR is not set CONFIG_TMPFS=y @@ -180,10 +170,7 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_DETECT_SOFTLOCKUP is not set # CONFIG_SCHED_DEBUG is not set # CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y CONFIG_CRYPTO_ECB=m CONFIG_CRYPTO_MICHAEL_MIC=m diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig index 158dde87f5d0..78cd73d1c795 100644 --- a/arch/arm/configs/ep93xx_defconfig +++ b/arch/arm/configs/ep93xx_defconfig @@ -45,7 +45,6 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_SYN_COOKIES=y -# CONFIG_INET_LRO is not set CONFIG_IPV6=y # CONFIG_INET6_XFRM_MODE_TRANSPORT is not set # CONFIG_INET6_XFRM_MODE_TUNNEL is not set diff --git a/arch/arm/configs/eseries_pxa_defconfig b/arch/arm/configs/eseries_pxa_defconfig index d68ac67c201c..cd27d651463c 100644 --- a/arch/arm/configs/eseries_pxa_defconfig +++ b/arch/arm/configs/eseries_pxa_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -29,7 +28,6 @@ CONFIG_PM=y CONFIG_NET=y CONFIG_UNIX=y CONFIG_INET=y -# CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_IRDA=y CONFIG_IRLAN=m @@ -55,8 +53,6 @@ CONFIG_ATA=m # CONFIG_SATA_PMP is not set CONFIG_PATA_PCMCIA=m CONFIG_NETDEVICES=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set CONFIG_HERMES=m CONFIG_PCMCIA_HERMES=m CONFIG_NET_PCMCIA=y @@ -97,11 +93,9 @@ CONFIG_SND_PXA2XX_SOC=m CONFIG_SND_PXA2XX_SOC_E800=m # CONFIG_USB_SUPPORT is not set CONFIG_MMC=y -CONFIG_MMC_UNSAFE_RESUME=y CONFIG_MMC_TMIO=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=m -CONFIG_INOTIFY=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y CONFIG_NFS_FS=y @@ -111,8 +105,6 @@ CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y # CONFIG_ENABLE_WARN_DEPRECATED is not set # CONFIG_ENABLE_MUST_CHECK is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_CRYPTO_CBC=m CONFIG_CRYPTO_PCBC=m # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/arm/configs/ezx_defconfig b/arch/arm/configs/ezx_defconfig index d3f1768840e2..23660f3d0f7f 100644 --- a/arch/arm/configs/ezx_defconfig +++ b/arch/arm/configs/ezx_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_LOCALVERSION="-ezx200910312315" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y @@ -51,7 +50,6 @@ CONFIG_SYN_COOKIES=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set CONFIG_INET6_AH=m CONFIG_INET6_ESP=m @@ -109,7 +107,6 @@ CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m @@ -118,7 +115,6 @@ CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m @@ -133,7 +129,6 @@ CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -144,15 +139,12 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m CONFIG_BRIDGE=m CONFIG_BT=y -CONFIG_BT_L2CAP=y -CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=y CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=y @@ -174,7 +166,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_FW_LOADER=m CONFIG_CONNECTOR=m CONFIG_MTD=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y @@ -189,11 +180,8 @@ CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y -# CONFIG_MISC_DEVICES is not set CONFIG_NETDEVICES=y CONFIG_DUMMY=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set # CONFIG_WLAN is not set CONFIG_PPP=m CONFIG_PPP_MULTILINK=y @@ -282,14 +270,12 @@ CONFIG_SND_PXA2XX_SOC=y # CONFIG_USB_HID is not set CONFIG_HID_APPLE=m CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_OHCI_HCD=y CONFIG_USB_GADGET=y CONFIG_USB_PXA27X=y CONFIG_USB_ETH=m # CONFIG_USB_ETH_RNDIS is not set CONFIG_MMC=y -CONFIG_MMC_UNSAFE_RESUME=y CONFIG_SDIO_UART=m CONFIG_MMC_PXA=y CONFIG_MMC_SPI=y @@ -311,8 +297,6 @@ CONFIG_REISERFS_FS_XATTR=y CONFIG_REISERFS_FS_POSIX_ACL=y CONFIG_REISERFS_FS_SECURITY=y CONFIG_XFS_FS=m -CONFIG_INOTIFY=y -CONFIG_AUTOFS_FS=y CONFIG_AUTOFS4_FS=y CONFIG_FUSE_FS=m CONFIG_CUSE=m @@ -385,10 +369,8 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_SCHED_DEBUG is not set CONFIG_DEBUG_RT_MUTEXES=y CONFIG_PROVE_LOCKING=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_FTRACE is not set CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_TEST=m diff --git a/arch/arm/configs/footbridge_defconfig b/arch/arm/configs/footbridge_defconfig index 87e020f303ab..3a7938f244e5 100644 --- a/arch/arm/configs/footbridge_defconfig +++ b/arch/arm/configs/footbridge_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 diff --git a/arch/arm/configs/h5000_defconfig b/arch/arm/configs/h5000_defconfig index 37903e3f0efc..e90d1dfeb188 100644 --- a/arch/arm/configs/h5000_defconfig +++ b/arch/arm/configs/h5000_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y @@ -31,12 +30,10 @@ CONFIG_IP_PNP=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y @@ -53,14 +50,12 @@ CONFIG_LEGACY_PTY_COUNT=32 # CONFIG_HW_RANDOM is not set # CONFIG_HWMON is not set # CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set CONFIG_USB_GADGET=y CONFIG_USB_ETH=m # CONFIG_USB_ETH_RNDIS is not set CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_SA1100=y CONFIG_EXT2_FS=y -CONFIG_INOTIFY=y # CONFIG_PROC_PAGE_MONITOR is not set CONFIG_TMPFS=y CONFIG_JFFS2_FS=y @@ -70,7 +65,6 @@ CONFIG_PRINTK_TIME=y CONFIG_DEBUG_KERNEL=y # CONFIG_SCHED_DEBUG is not set # CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y # CONFIG_FTRACE is not set CONFIG_CRYPTO=y CONFIG_CRYPTO_HMAC=y diff --git a/arch/arm/configs/hackkit_defconfig b/arch/arm/configs/hackkit_defconfig index bed804729929..742d18cdabde 100644 --- a/arch/arm/configs/hackkit_defconfig +++ b/arch/arm/configs/hackkit_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y @@ -22,7 +21,6 @@ CONFIG_SYN_COOKIES=y CONFIG_MTD=y CONFIG_MTD_DEBUG=y CONFIG_MTD_DEBUG_VERBOSE=3 -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y @@ -44,6 +42,5 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y # CONFIG_CRC32 is not set diff --git a/arch/arm/configs/imote2_defconfig b/arch/arm/configs/imote2_defconfig index 7f479cdb3479..f204017c26b9 100644 --- a/arch/arm/configs/imote2_defconfig +++ b/arch/arm/configs/imote2_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 @@ -43,7 +42,6 @@ CONFIG_SYN_COOKIES=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set CONFIG_INET6_AH=m CONFIG_INET6_ESP=m @@ -101,7 +99,6 @@ CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m @@ -110,7 +107,6 @@ CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m @@ -125,7 +121,6 @@ CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -136,7 +131,6 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m @@ -154,7 +148,6 @@ CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_AFS_PARTS=y CONFIG_MTD_AR7_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y @@ -169,11 +162,8 @@ CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y -# CONFIG_MISC_DEVICES is not set CONFIG_NETDEVICES=y CONFIG_DUMMY=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set # CONFIG_WLAN is not set CONFIG_PPP=m CONFIG_PPP_MULTILINK=y @@ -258,14 +248,12 @@ CONFIG_SND_SOC=y CONFIG_SND_PXA2XX_SOC=y # CONFIG_USB_HID is not set CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_OHCI_HCD=y CONFIG_USB_GADGET=y CONFIG_USB_PXA27X=y CONFIG_USB_ETH=m # CONFIG_USB_ETH_RNDIS is not set CONFIG_MMC=y -CONFIG_MMC_UNSAFE_RESUME=y CONFIG_SDIO_UART=m CONFIG_MMC_PXA=y CONFIG_MMC_SPI=y @@ -282,8 +270,6 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_PXA=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=m -CONFIG_INOTIFY=y -CONFIG_AUTOFS_FS=y CONFIG_AUTOFS4_FS=y CONFIG_FUSE_FS=m CONFIG_CUSE=m @@ -356,10 +342,8 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_SCHED_DEBUG is not set CONFIG_DEBUG_RT_MUTEXES=y CONFIG_PROVE_LOCKING=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_FTRACE is not set CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_TEST=m diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig index 5f013c9fc1ed..ca0f13cafe38 100644 --- a/arch/arm/configs/imx_v4_v5_defconfig +++ b/arch/arm/configs/imx_v4_v5_defconfig @@ -45,7 +45,6 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_NETFILTER=y diff --git a/arch/arm/configs/iop13xx_defconfig b/arch/arm/configs/iop13xx_defconfig index 652b7bd9e544..a73b6a31a4ab 100644 --- a/arch/arm/configs/iop13xx_defconfig +++ b/arch/arm/configs/iop13xx_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y @@ -30,7 +29,6 @@ CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y CONFIG_IP_PNP_BOOTP=y -# CONFIG_INET_LRO is not set CONFIG_IPV6=y # CONFIG_INET6_XFRM_MODE_TRANSPORT is not set # CONFIG_INET6_XFRM_MODE_TUNNEL is not set @@ -38,7 +36,6 @@ CONFIG_IPV6=y # CONFIG_IPV6_SIT is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y CONFIG_MTD_REDBOOT_PARTS_READONLY=y @@ -79,7 +76,6 @@ CONFIG_DMADEVICES=y CONFIG_INTEL_IOP_ADMA=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y -CONFIG_INOTIFY=y CONFIG_TMPFS=y CONFIG_ECRYPT_FS=y CONFIG_JFFS2_FS=y diff --git a/arch/arm/configs/iop32x_defconfig b/arch/arm/configs/iop32x_defconfig index aa3af0a6b8f7..f63362b665eb 100644 --- a/arch/arm/configs/iop32x_defconfig +++ b/arch/arm/configs/iop32x_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 @@ -26,7 +25,6 @@ CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y CONFIG_IP_PNP_BOOTP=y -# CONFIG_INET_LRO is not set CONFIG_IPV6=y # CONFIG_INET6_XFRM_MODE_TRANSPORT is not set # CONFIG_INET6_XFRM_MODE_TUNNEL is not set @@ -34,11 +32,9 @@ CONFIG_IPV6=y # CONFIG_IPV6_SIT is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y CONFIG_MTD_REDBOOT_PARTS_READONLY=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y @@ -91,7 +87,6 @@ CONFIG_INTEL_IOP_ADMA=y CONFIG_NET_DMA=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y -CONFIG_INOTIFY=y CONFIG_TMPFS=y CONFIG_ECRYPT_FS=y CONFIG_JFFS2_FS=y diff --git a/arch/arm/configs/iop33x_defconfig b/arch/arm/configs/iop33x_defconfig index 713faeee8cf4..d22f832ccfd6 100644 --- a/arch/arm/configs/iop33x_defconfig +++ b/arch/arm/configs/iop33x_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 @@ -24,7 +23,6 @@ CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y CONFIG_IP_PNP_BOOTP=y -# CONFIG_INET_LRO is not set CONFIG_IPV6=y # CONFIG_INET6_XFRM_MODE_TRANSPORT is not set # CONFIG_INET6_XFRM_MODE_TUNNEL is not set @@ -32,11 +30,9 @@ CONFIG_IPV6=y # CONFIG_IPV6_SIT is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y CONFIG_MTD_REDBOOT_PARTS_READONLY=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y @@ -73,7 +69,6 @@ CONFIG_INTEL_IOP_ADMA=y CONFIG_NET_DMA=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y -CONFIG_INOTIFY=y CONFIG_TMPFS=y CONFIG_CRAMFS=y CONFIG_NFS_FS=y @@ -84,7 +79,6 @@ CONFIG_NFSD_V3=y CONFIG_PARTITION_ADVANCED=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_DEBUG_USER=y CONFIG_DEBUG_LL=y CONFIG_DEBUG_LL_UART_8250=y diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig index bb910d9df6c1..c8378da71913 100644 --- a/arch/arm/configs/ixp4xx_defconfig +++ b/arch/arm/configs/ixp4xx_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 @@ -50,7 +49,6 @@ CONFIG_IP_MROUTE=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y CONFIG_SYN_COOKIES=y -# CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_NETFILTER=y CONFIG_IP_VS=m @@ -63,13 +61,11 @@ CONFIG_IP_VS_LBLC=m CONFIG_IP_VS_LBLCR=m CONFIG_IP_VS_DH=m CONFIG_IP_VS_SH=m -CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m @@ -114,9 +110,7 @@ CONFIG_NET_ACT_POLICE=y CONFIG_NET_PKTGEN=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y @@ -170,7 +164,6 @@ CONFIG_SENSORS_W83781D=y CONFIG_WATCHDOG=y CONFIG_IXP4XX_WATCHDOG=y CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_UHCI_HCD=y @@ -192,7 +185,6 @@ CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_INOTIFY=y CONFIG_TMPFS=y CONFIG_JFFS2_FS=y CONFIG_NFS_FS=y @@ -201,6 +193,5 @@ CONFIG_ROOT_NFS=y CONFIG_PARTITION_ADVANCED=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y CONFIG_DEBUG_LL_UART_8250=y diff --git a/arch/arm/configs/jornada720_defconfig b/arch/arm/configs/jornada720_defconfig index 9056284139be..65d37ad6e6b8 100644 --- a/arch/arm/configs/jornada720_defconfig +++ b/arch/arm/configs/jornada720_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y @@ -19,7 +18,6 @@ CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_INET=y CONFIG_IP_MULTICAST=y -# CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_NETFILTER=y CONFIG_IRDA=m @@ -35,8 +33,6 @@ CONFIG_PATA_PCMCIA=y CONFIG_NETDEVICES=y CONFIG_DUMMY=y CONFIG_NET_ETHERNET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set CONFIG_NET_PCMCIA=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=640 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 @@ -58,12 +54,10 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -# CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_SA1100=y CONFIG_EXT2_FS=y -CONFIG_INOTIFY=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y # CONFIG_NETWORK_FILESYSTEMS is not set @@ -106,8 +100,6 @@ CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m CONFIG_NLS_UTF8=m CONFIG_DEBUG_KERNEL=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_FTRACE is not set -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/arm/configs/ks8695_defconfig b/arch/arm/configs/ks8695_defconfig index 47c488379f8f..b8b91d790e9b 100644 --- a/arch/arm/configs/ks8695_defconfig +++ b/arch/arm/configs/ks8695_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 @@ -28,14 +27,11 @@ CONFIG_UNIX=y CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y -# CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y @@ -46,8 +42,6 @@ CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_MII=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set CONFIG_PRISM54=m # CONFIG_INPUT_MOUSEDEV_PSAUX is not set # CONFIG_INPUT_KEYBOARD is not set @@ -58,7 +52,6 @@ CONFIG_SERIAL_KS8695_CONSOLE=y # CONFIG_HWMON is not set # CONFIG_VGA_CONSOLE is not set CONFIG_EXT2_FS=y -CONFIG_INOTIFY=y CONFIG_TMPFS=y CONFIG_JFFS2_FS=y CONFIG_JFFS2_SUMMARY=y diff --git a/arch/arm/configs/lart_defconfig b/arch/arm/configs/lart_defconfig index 8fc6fd09eb6d..b6ddb9884326 100644 --- a/arch/arm/configs/lart_defconfig +++ b/arch/arm/configs/lart_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y @@ -31,8 +30,6 @@ CONFIG_SA1100_FIR=m CONFIG_MTD=y CONFIG_MTD_DEBUG=y CONFIG_MTD_DEBUG_VERBOSE=1 -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_LART=y CONFIG_BLK_DEV_RAM=y diff --git a/arch/arm/configs/lpc18xx_defconfig b/arch/arm/configs/lpc18xx_defconfig index 2de1bf0e497e..23df2518203d 100644 --- a/arch/arm/configs/lpc18xx_defconfig +++ b/arch/arm/configs/lpc18xx_defconfig @@ -44,7 +44,6 @@ CONFIG_INET=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set diff --git a/arch/arm/configs/lpd270_defconfig b/arch/arm/configs/lpd270_defconfig index a9dd1e93b556..3a4d0e64cd6e 100644 --- a/arch/arm/configs/lpd270_defconfig +++ b/arch/arm/configs/lpd270_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SLAB=y @@ -21,9 +20,7 @@ CONFIG_IPV6=y # CONFIG_INET6_XFRM_MODE_BEET is not set # CONFIG_IPV6_SIT is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y @@ -50,7 +47,6 @@ CONFIG_SND=y # CONFIG_SND_SUPPORT_OLD_API is not set CONFIG_SND_PXA2XX_AC97=y CONFIG_EXT2_FS=y -CONFIG_INOTIFY=y CONFIG_MSDOS_FS=y CONFIG_JFFS2_FS=y CONFIG_NFS_FS=y @@ -60,5 +56,4 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_INFO=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/lubbock_defconfig b/arch/arm/configs/lubbock_defconfig index c4ba27458baa..4ce2da2e76fa 100644 --- a/arch/arm/configs/lubbock_defconfig +++ b/arch/arm/configs/lubbock_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_MODULES=y @@ -20,9 +19,7 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_BOOTP=y # CONFIG_IPV6 is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y @@ -52,5 +49,4 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_INFO=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig index a5b4920cd6d4..ec5674c229a3 100644 --- a/arch/arm/configs/magician_defconfig +++ b/arch/arm/configs/magician_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y @@ -35,7 +34,6 @@ CONFIG_IP_PNP=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_IRDA=m @@ -48,8 +46,6 @@ CONFIG_IRDA_DEBUG=y CONFIG_IRTTY_SIR=m CONFIG_PXA_FICP=m CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m @@ -60,17 +56,12 @@ CONFIG_BT_HCIBTUSB=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FIRMWARE_IN_KERNEL is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_PHYSMAP=y -# CONFIG_MISC_DEVICES is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set CONFIG_PPP=m CONFIG_PPP_ASYNC=m CONFIG_PPP_DEFLATE=m @@ -111,7 +102,6 @@ CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_PWM=y -CONFIG_DISPLAY_SUPPORT=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y @@ -125,9 +115,7 @@ CONFIG_SND_PCM_OSS=m # CONFIG_SND_USB is not set CONFIG_SND_SOC=m CONFIG_SND_PXA2XX_SOC=m -# CONFIG_HID_SUPPORT is not set CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_MON=m CONFIG_USB_OHCI_HCD=y CONFIG_USB_GADGET=y @@ -152,7 +140,6 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DEBUG=y CONFIG_RTC_DRV_PXA=y CONFIG_EXT2_FS=y -CONFIG_INOTIFY=y CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_TMPFS=y @@ -172,9 +159,7 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_SCHED_DEBUG is not set CONFIG_TIMER_STATS=y # CONFIG_DEBUG_PREEMPT is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y CONFIG_CRYPTO=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/arm/configs/mainstone_defconfig b/arch/arm/configs/mainstone_defconfig index e8d26b805be6..26499b697f9f 100644 --- a/arch/arm/configs/mainstone_defconfig +++ b/arch/arm/configs/mainstone_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_MODULES=y @@ -18,9 +17,7 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_BOOTP=y # CONFIG_IPV6 is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y @@ -50,5 +47,4 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_INFO=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig index 0b02e4f43c6a..f48bc89de871 100644 --- a/arch/arm/configs/mini2440_defconfig +++ b/arch/arm/configs/mini2440_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y @@ -49,7 +48,6 @@ CONFIG_SYN_COOKIES=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=m # CONFIG_IPV6 is not set CONFIG_NETFILTER=y @@ -58,8 +56,6 @@ CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y CONFIG_NET_PKTGEN=m CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m @@ -77,7 +73,6 @@ CONFIG_BT_HCIBPA10X=m CONFIG_BT_HCIBFUSB=m CONFIG_BT_HCIVHCI=m CONFIG_CFG80211=m -CONFIG_CFG80211_REG_DEBUG=y CONFIG_MAC80211=m CONFIG_MAC80211_MESH=y CONFIG_MAC80211_LEDS=y @@ -85,10 +80,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FIRMWARE_IN_KERNEL is not set CONFIG_CONNECTOR=m CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_FTL=y CONFIG_NFTL=y @@ -120,8 +112,6 @@ CONFIG_NETDEVICES=y CONFIG_TUN=m CONFIG_NET_ETHERNET=y CONFIG_DM9000=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set CONFIG_HOSTAP=m CONFIG_HOSTAP_FIRMWARE=y CONFIG_HOSTAP_FIRMWARE_NVRAM=y @@ -167,7 +157,6 @@ CONFIG_SENSORS_LM75=y CONFIG_THERMAL=m CONFIG_WATCHDOG=y CONFIG_S3C2410_WATCHDOG=y -CONFIG_VIDEO_OUTPUT_CONTROL=y CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_MODE_HELPERS=y @@ -179,7 +168,6 @@ CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_PWM=y -CONFIG_DISPLAY_SUPPORT=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y @@ -218,7 +206,6 @@ CONFIG_HID_SONY=y CONFIG_HID_SUNPLUS=y CONFIG_HID_TOPSEED=y CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_OHCI_HCD=y CONFIG_USB_ACM=m CONFIG_USB_WDM=m @@ -230,7 +217,6 @@ CONFIG_USB_STORAGE_SDDR09=m CONFIG_USB_STORAGE_SDDR55=m CONFIG_USB_STORAGE_JUMPSHOT=m CONFIG_USB_STORAGE_ALAUDA=m -CONFIG_USB_LIBUSUAL=y CONFIG_USB_SERIAL=m CONFIG_USB_SERIAL_CP210X=m CONFIG_USB_SERIAL_FTDI_SIO=m @@ -266,8 +252,6 @@ CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -CONFIG_INOTIFY=y -CONFIG_AUTOFS_FS=y CONFIG_AUTOFS4_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y @@ -336,8 +320,6 @@ CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y # CONFIG_SCHED_DEBUG is not set CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_DEBUG_USER=y CONFIG_KEYS=y CONFIG_CRYPTO_FIPS=y @@ -379,7 +361,6 @@ CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_TEA=m CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_ZLIB=m CONFIG_CRYPTO_LZO=m CONFIG_CRC_T10DIF=y CONFIG_LIBCRC32C=m diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig index f1cb95e58af0..1eeee7f11d91 100644 --- a/arch/arm/configs/mmp2_defconfig +++ b/arch/arm/configs/mmp2_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y @@ -23,7 +22,6 @@ CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_INET=y CONFIG_IP_PNP=y -# CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set @@ -34,12 +32,9 @@ CONFIG_MTD_NAND=y CONFIG_MTD_ONENAND=y CONFIG_MTD_ONENAND_GENERIC=y # CONFIG_BLK_DEV is not set -# CONFIG_MISC_DEVICES is not set CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_SMC91X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set # CONFIG_INPUT_MOUSEDEV_PSAUX is not set # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set @@ -60,13 +55,11 @@ CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_MAX8925=y # CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_MAX8925=y CONFIG_MMC=y # CONFIG_DNOTIFY is not set -CONFIG_INOTIFY=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_EXT2_FS=y @@ -87,12 +80,10 @@ CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_PREEMPT is not set CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_DYNAMIC_DEBUG is not set CONFIG_DEBUG_USER=y CONFIG_DEBUG_LL=y CONFIG_DEBUG_MMP_UART3=y CONFIG_EARLY_PRINTK=y -CONFIG_DEBUG_ERRORS=y # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRC_CCITT=y diff --git a/arch/arm/configs/moxart_defconfig b/arch/arm/configs/moxart_defconfig index b2ddd534867f..2da0d9ee2107 100644 --- a/arch/arm/configs/moxart_defconfig +++ b/arch/arm/configs/moxart_defconfig @@ -36,7 +36,6 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set diff --git a/arch/arm/configs/mps2_defconfig b/arch/arm/configs/mps2_defconfig index 19d119f5b77e..0bcdec7cc169 100644 --- a/arch/arm/configs/mps2_defconfig +++ b/arch/arm/configs/mps2_defconfig @@ -35,7 +35,6 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig index a0345e1ce172..752e2e74de5b 100644 --- a/arch/arm/configs/mv78xx0_defconfig +++ b/arch/arm/configs/mv78xx0_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y @@ -40,9 +39,7 @@ CONFIG_NET_PKTGEN=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FIRMWARE_IN_KERNEL is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y @@ -66,7 +63,6 @@ CONFIG_NET_ETHERNET=y CONFIG_MII=y CONFIG_NET_PCI=y CONFIG_MV643XX_ETH=y -# CONFIG_NETDEV_10000 is not set # CONFIG_INPUT_MOUSEDEV is not set CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_KEYBOARD is not set @@ -106,7 +102,6 @@ CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set CONFIG_EXT4_FS=m -CONFIG_INOTIFY=y CONFIG_ISO9660_FS=m CONFIG_JOLIET=y CONFIG_UDF_FS=m @@ -130,10 +125,7 @@ CONFIG_DEBUG_KERNEL=y CONFIG_SCHEDSTATS=y # CONFIG_DEBUG_BUGVERBOSE is not set CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y CONFIG_CRYPTO_CBC=m CONFIG_CRYPTO_ECB=m diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index 6e0f751be229..5eb4c4fc7a34 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig @@ -38,7 +38,6 @@ CONFIG_SYN_COOKIES=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_CAN=m diff --git a/arch/arm/configs/neponset_defconfig b/arch/arm/configs/neponset_defconfig index 460dca4a4f98..018a1092d0e7 100644 --- a/arch/arm/configs/neponset_defconfig +++ b/arch/arm/configs/neponset_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y @@ -25,8 +24,6 @@ CONFIG_UNIX=y CONFIG_INET=y # CONFIG_IPV6 is not set CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y @@ -84,5 +81,4 @@ CONFIG_NLS_ISO8859_1=m CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/netwinder_defconfig b/arch/arm/configs/netwinder_defconfig index f1395bbd436c..2e3b20ef0db1 100644 --- a/arch/arm/configs/netwinder_defconfig +++ b/arch/arm/configs/netwinder_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_ARCH_FOOTBRIDGE=y @@ -21,7 +20,6 @@ CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y # CONFIG_IPV6 is not set CONFIG_NETFILTER=y -CONFIG_IP_NF_QUEUE=y CONFIG_IP_NF_IPTABLES=y CONFIG_PARPORT=y CONFIG_PARPORT_PC=y @@ -65,7 +63,6 @@ CONFIG_SOUND_DMAP=y CONFIG_SOUND_YM3812=y CONFIG_SOUND_WAVEARTIST=y CONFIG_EXT2_FS=y -CONFIG_AUTOFS_FS=y CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_TMPFS=y diff --git a/arch/arm/configs/netx_defconfig b/arch/arm/configs/netx_defconfig index 9c0ad7993986..cc5c5f9ef720 100644 --- a/arch/arm/configs/netx_defconfig +++ b/arch/arm/configs/netx_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y @@ -34,12 +33,9 @@ CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m CONFIG_NETFILTER=y -CONFIG_IP_NF_QUEUE=m CONFIG_NET_PKTGEN=m CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y @@ -61,7 +57,6 @@ CONFIG_FB_ARMCLCD=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y CONFIG_RTC_CLASS=y -CONFIG_INOTIFY=y CONFIG_TMPFS=y CONFIG_JFFS2_FS=y CONFIG_NFS_FS=y @@ -70,7 +65,6 @@ CONFIG_NFS_V4=y CONFIG_ROOT_NFS=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_ERRORS=y CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_MD4=m CONFIG_CRYPTO_MICHAEL_MIC=m diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig index 7d2ad30d9e70..0ac44acd5bc4 100644 --- a/arch/arm/configs/nhk8815_defconfig +++ b/arch/arm/configs/nhk8815_defconfig @@ -32,7 +32,6 @@ CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_NET_IPIP=y CONFIG_IP_MROUTE=y -# CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_BT=m CONFIG_BT_RFCOMM=m diff --git a/arch/arm/configs/nuc910_defconfig b/arch/arm/configs/nuc910_defconfig index 10180cfde162..a72653645f9d 100644 --- a/arch/arm/configs/nuc910_defconfig +++ b/arch/arm/configs/nuc910_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y @@ -16,16 +15,12 @@ CONFIG_KEXEC=y CONFIG_FPE_NWFPE=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_PHYSMAP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_MISC_DEVICES is not set CONFIG_SCSI=y # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y @@ -42,7 +37,6 @@ CONFIG_SERIAL_8250_NR_UARTS=1 # CONFIG_HW_RANDOM is not set # CONFIG_HWMON is not set # CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set CONFIG_USB=y CONFIG_USB_MON=y CONFIG_USB_STORAGE=y @@ -56,5 +50,4 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_ENABLE_WARN_DEPRECATED is not set # CONFIG_ENABLE_MUST_CHECK is not set CONFIG_DEBUG_FS=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_CRC32 is not set diff --git a/arch/arm/configs/nuc950_defconfig b/arch/arm/configs/nuc950_defconfig index 27aa8731330b..614a0a28d0b4 100644 --- a/arch/arm/configs/nuc950_defconfig +++ b/arch/arm/configs/nuc950_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y @@ -22,16 +21,12 @@ CONFIG_BINFMT_AOUT=y CONFIG_BINFMT_MISC=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_PHYSMAP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_MISC_DEVICES is not set CONFIG_SCSI=y # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y @@ -59,7 +54,6 @@ CONFIG_FONT_8x16=y CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set # CONFIG_LOGO_LINUX_VGA16 is not set -# CONFIG_HID_SUPPORT is not set CONFIG_USB=y CONFIG_USB_MON=y CONFIG_USB_STORAGE=y @@ -73,4 +67,3 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_ENABLE_WARN_DEPRECATED is not set # CONFIG_ENABLE_MUST_CHECK is not set CONFIG_DEBUG_FS=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set diff --git a/arch/arm/configs/nuc960_defconfig b/arch/arm/configs/nuc960_defconfig index 56fd7ad0ff13..b84bbd216153 100644 --- a/arch/arm/configs/nuc960_defconfig +++ b/arch/arm/configs/nuc960_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y @@ -22,16 +21,12 @@ CONFIG_BINFMT_AOUT=y CONFIG_BINFMT_MISC=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_PHYSMAP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_MISC_DEVICES is not set CONFIG_SCSI=y # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y @@ -48,7 +43,6 @@ CONFIG_SERIAL_8250_NR_UARTS=1 # CONFIG_HW_RANDOM is not set # CONFIG_HWMON is not set # CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set CONFIG_USB=y CONFIG_USB_MON=y CONFIG_USB_STORAGE=y @@ -62,5 +56,4 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_ENABLE_WARN_DEPRECATED is not set # CONFIG_ENABLE_MUST_CHECK is not set CONFIG_DEBUG_FS=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_CRC32 is not set diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig index 6ffc9844542d..72f4bc83f467 100644 --- a/arch/arm/configs/omap1_defconfig +++ b/arch/arm/configs/omap1_defconfig @@ -72,7 +72,6 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set CONFIG_IPV6=y CONFIG_NETFILTER=y @@ -252,7 +251,6 @@ CONFIG_SECURITY=y CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_PCBC=y CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_ZLIB=y CONFIG_CRYPTO_LZO=y # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig index 27a70a7a50f6..e39ee282e6ca 100644 --- a/arch/arm/configs/orion5x_defconfig +++ b/arch/arm/configs/orion5x_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y @@ -64,7 +63,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FIRMWARE_IN_KERNEL is not set CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y diff --git a/arch/arm/configs/palmz72_defconfig b/arch/arm/configs/palmz72_defconfig index 83c135e19aba..e0a614272561 100644 --- a/arch/arm/configs/palmz72_defconfig +++ b/arch/arm/configs/palmz72_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 @@ -30,11 +29,9 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_LOOP=y -# CONFIG_MISC_DEVICES is not set # CONFIG_INPUT_MOUSEDEV_PSAUX is not set CONFIG_INPUT_EVDEV=y # CONFIG_KEYBOARD_ATKBD is not set @@ -56,12 +53,10 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y -CONFIG_DISPLAY_SUPPORT=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FONTS=y CONFIG_FONT_8x8=y -# CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set CONFIG_MMC=y CONFIG_MMC_DEBUG=y @@ -80,6 +75,5 @@ CONFIG_TMPFS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_866=y CONFIG_NLS_UTF8=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_DEBUG_USER=y CONFIG_CRC_T10DIF=y diff --git a/arch/arm/configs/pcm027_defconfig b/arch/arm/configs/pcm027_defconfig index b5624e325817..9c88a193490c 100644 --- a/arch/arm/configs/pcm027_defconfig +++ b/arch/arm/configs/pcm027_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y @@ -34,28 +33,22 @@ CONFIG_IP_PNP=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_PHYSMAP=y # CONFIG_BLK_DEV is not set -# CONFIG_MISC_DEVICES is not set CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y # CONFIG_SCSI_LOWLEVEL is not set CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_SMC91X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set # CONFIG_INPUT_MOUSEDEV_PSAUX is not set # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set @@ -74,7 +67,6 @@ CONFIG_SND=y CONFIG_SND_MIXER_OSS=y CONFIG_SND_PCM_OSS=y CONFIG_SND_PXA2XX_AC97=y -# CONFIG_HID_SUPPORT is not set CONFIG_USB=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/arch/arm/configs/pleb_defconfig b/arch/arm/configs/pleb_defconfig index cb08cc561da5..f0541b060cfa 100644 --- a/arch/arm/configs/pleb_defconfig +++ b/arch/arm/configs/pleb_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 @@ -24,11 +23,9 @@ CONFIG_INET=y CONFIG_SYN_COOKIES=y # CONFIG_IPV6 is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y diff --git a/arch/arm/configs/pxa168_defconfig b/arch/arm/configs/pxa168_defconfig index 74d7e0104f8d..e7c7b91b6de2 100644 --- a/arch/arm/configs/pxa168_defconfig +++ b/arch/arm/configs/pxa168_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y @@ -24,18 +23,14 @@ CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_INET=y CONFIG_IP_PNP=y -# CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_BLK_DEV is not set -# CONFIG_MISC_DEVICES is not set CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_SMC91X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set # CONFIG_INPUT_MOUSEDEV_PSAUX is not set # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set @@ -46,9 +41,7 @@ CONFIG_SERIAL_PXA_CONSOLE=y # CONFIG_HW_RANDOM is not set # CONFIG_HWMON is not set # CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set -CONFIG_INOTIFY=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_CRAMFS=y @@ -62,9 +55,7 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_PREEMPT is not set CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRC_CCITT=y diff --git a/arch/arm/configs/pxa255-idp_defconfig b/arch/arm/configs/pxa255-idp_defconfig index 088627ad875f..4a383afa5e87 100644 --- a/arch/arm/configs/pxa255-idp_defconfig +++ b/arch/arm/configs/pxa255-idp_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_MODULES=y @@ -18,8 +17,6 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y # CONFIG_IPV6 is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y @@ -54,5 +51,4 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_INFO=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/pxa3xx_defconfig b/arch/arm/configs/pxa3xx_defconfig index 5f337d7ceb5b..bfea6874b0a1 100644 --- a/arch/arm/configs/pxa3xx_defconfig +++ b/arch/arm/configs/pxa3xx_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=18 CONFIG_SYSFS_DEPRECATED_V2=y @@ -25,15 +24,12 @@ CONFIG_IP_PNP=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_PXA3xx=y @@ -43,12 +39,9 @@ CONFIG_MTD_ONENAND_VERIFY_WRITE=y CONFIG_MTD_ONENAND_GENERIC=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y -# CONFIG_MISC_DEVICES is not set CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_SMC91X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set # CONFIG_INPUT_MOUSEDEV_PSAUX is not set # CONFIG_KEYBOARD_ATKBD is not set CONFIG_KEYBOARD_GPIO=y @@ -92,7 +85,6 @@ CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_FONTS=y CONFIG_FONT_6x11=y CONFIG_LOGO=y -# CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set CONFIG_MMC=y CONFIG_MMC_PXA=y @@ -125,7 +117,6 @@ CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y # CONFIG_SCHED_DEBUG is not set CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_SPINLOCK_SLEEP=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_FTRACE is not set CONFIG_DEBUG_USER=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/arm/configs/pxa910_defconfig b/arch/arm/configs/pxa910_defconfig index 3bb7771d3c19..3aff71e6dae5 100644 --- a/arch/arm/configs/pxa910_defconfig +++ b/arch/arm/configs/pxa910_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y @@ -24,18 +23,14 @@ CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_INET=y CONFIG_IP_PNP=y -# CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_BLK_DEV is not set -# CONFIG_MISC_DEVICES is not set CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_SMC91X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set # CONFIG_INPUT_MOUSEDEV_PSAUX is not set # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set @@ -54,9 +49,7 @@ CONFIG_LOGO=y # CONFIG_HW_RANDOM is not set # CONFIG_HWMON is not set # CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set -CONFIG_INOTIFY=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_CRAMFS=y @@ -70,9 +63,7 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_PREEMPT is not set CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y CONFIG_DEBUG_MMP_UART2=y CONFIG_EARLY_PRINTK=y diff --git a/arch/arm/configs/pxa_defconfig b/arch/arm/configs/pxa_defconfig index 1318f61589dc..64e3a2a8cede 100644 --- a/arch/arm/configs/pxa_defconfig +++ b/arch/arm/configs/pxa_defconfig @@ -156,7 +156,6 @@ CONFIG_BT_HCIVHCI=m CONFIG_BT_MRVL=m CONFIG_BT_MRVL_SDIO=m CONFIG_CFG80211=m -CONFIG_CFG80211_REG_DEBUG=y CONFIG_MAC80211=m CONFIG_RFKILL=y CONFIG_RFKILL_INPUT=y @@ -592,7 +591,6 @@ CONFIG_USB_EMI26=m CONFIG_USB_RIO500=m CONFIG_USB_LEGOTOWER=m CONFIG_USB_LCD=m -CONFIG_USB_LED=m CONFIG_USB_CYTHERM=m CONFIG_USB_IDMOUSE=m CONFIG_USB_GPIO_VBUS=y diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig index 07666a7a9de5..f201d40635a9 100644 --- a/arch/arm/configs/qcom_defconfig +++ b/arch/arm/configs/qcom_defconfig @@ -52,7 +52,6 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_CFG80211=y CONFIG_RFKILL=y diff --git a/arch/arm/configs/raumfeld_defconfig b/arch/arm/configs/raumfeld_defconfig index 3d833aea545a..e3dc80ead465 100644 --- a/arch/arm/configs/raumfeld_defconfig +++ b/arch/arm/configs/raumfeld_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set # CONFIG_SWAP is not set CONFIG_MODULES=y @@ -24,16 +23,11 @@ CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y CONFIG_SYN_COOKIES=y -# CONFIG_INET_LRO is not set CONFIG_IPV6=y CONFIG_CFG80211=y -CONFIG_CFG80211_REG_DEBUG=y CONFIG_MAC80211=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_NFTL=y CONFIG_NFTL_RW=y @@ -50,8 +44,6 @@ CONFIG_CHR_DEV_SG=y CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_SMSC911X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set CONFIG_LIBERTAS=y CONFIG_LIBERTAS_SDIO=m CONFIG_USB_USBNET=y @@ -146,7 +138,6 @@ CONFIG_UIO=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XIP=y CONFIG_EXT3_FS=y -CONFIG_INOTIFY=y CONFIG_FSCACHE=y CONFIG_FSCACHE_STATS=y CONFIG_CACHEFILES=y @@ -199,9 +190,7 @@ CONFIG_NLS_UTF8=y CONFIG_PRINTK_TIME=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y # CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig index 9e77dc7b828f..2a6d69d896bd 100644 --- a/arch/arm/configs/realview_defconfig +++ b/arch/arm/configs/realview_defconfig @@ -35,7 +35,6 @@ CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y -# CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y diff --git a/arch/arm/configs/rpc_defconfig b/arch/arm/configs/rpc_defconfig index 89631795a915..3b82b64950d9 100644 --- a/arch/arm/configs/rpc_defconfig +++ b/arch/arm/configs/rpc_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 @@ -51,8 +50,6 @@ CONFIG_NET_ETHERNET=y CONFIG_ARM_ETHER1=y CONFIG_ARM_ETHER3=y CONFIG_ARM_ETHERH=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set CONFIG_PPP=m CONFIG_PPPOE=m CONFIG_INPUT_EVDEV=y @@ -81,13 +78,11 @@ CONFIG_SOUND=m CONFIG_SOUND_PRIME=m CONFIG_SOUND_OSS=m CONFIG_SOUND_VIDC=m -# CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_PCF8583=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y -CONFIG_INOTIFY=y CONFIG_AUTOFS4_FS=m CONFIG_ISO9660_FS=y CONFIG_JOLIET=y @@ -129,6 +124,5 @@ CONFIG_NLS_KOI8_R=m CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y CONFIG_DEBUG_LL_UART_8250=y diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig index 1e6c48dd7b11..6349fc988a0f 100644 --- a/arch/arm/configs/s3c2410_defconfig +++ b/arch/arm/configs/s3c2410_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_IKCONFIG=m CONFIG_IKCONFIG_PROC=y @@ -67,7 +66,6 @@ CONFIG_NET_IPIP=m CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m -# CONFIG_INET_LRO is not set CONFIG_TCP_CONG_ADVANCED=y CONFIG_TCP_CONG_HSTCP=m CONFIG_TCP_CONG_HYBLA=m @@ -139,7 +137,6 @@ CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m CONFIG_IP_VS=m CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m @@ -147,7 +144,6 @@ CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m @@ -161,7 +157,6 @@ CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -172,7 +167,6 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m @@ -201,7 +195,6 @@ CONFIG_MTD=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y @@ -216,7 +209,6 @@ CONFIG_PARPORT_AX88796=m CONFIG_PARPORT_1284=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=m -CONFIG_BLK_DEV_UB=m CONFIG_BLK_DEV_RAM=y CONFIG_ATA_OVER_ETH=m CONFIG_BLK_DEV_SD=y @@ -336,7 +328,6 @@ CONFIG_USB_STORAGE_ALAUDA=m CONFIG_USB_STORAGE_ONETOUCH=m CONFIG_USB_STORAGE_KARMA=m CONFIG_USB_STORAGE_CYPRESS_ATACB=m -CONFIG_USB_LIBUSUAL=y CONFIG_USB_MDC800=m CONFIG_USB_MICROTEK=m CONFIG_USB_USS720=m @@ -353,7 +344,6 @@ CONFIG_USB_SEVSEG=m CONFIG_USB_RIO500=m CONFIG_USB_LEGOTOWER=m CONFIG_USB_LCD=m -CONFIG_USB_LED=m CONFIG_USB_CYPRESS_CY7C63=m CONFIG_USB_CYTHERM=m CONFIG_USB_IDMOUSE=m @@ -456,7 +446,6 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_INFO=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_DEBUG_USER=y CONFIG_DEBUG_LL=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig index e0f66936ae02..ccc908f3aa3a 100644 --- a/arch/arm/configs/s3c6400_defconfig +++ b/arch/arm/configs/s3c6400_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y CONFIG_KALLSYMS_ALL=y @@ -68,7 +67,6 @@ CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_USB_SERIAL_PL2303=m CONFIG_MMC=y CONFIG_MMC_DEBUG=y -CONFIG_MMC_UNSAFE_RESUME=y CONFIG_SDIO_UART=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S3C=y @@ -78,7 +76,6 @@ CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -CONFIG_INOTIFY=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_CRAMFS=y @@ -90,8 +87,5 @@ CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_SPINLOCK_SLEEP=y CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/s5pv210_defconfig b/arch/arm/configs/s5pv210_defconfig index c51f0f02012b..38bee3209c0b 100644 --- a/arch/arm/configs/s5pv210_defconfig +++ b/arch/arm/configs/s5pv210_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y CONFIG_KALLSYMS_ALL=y @@ -21,7 +20,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 -# CONFIG_MISC_DEVICES is not set CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_SG=y @@ -35,10 +33,8 @@ CONFIG_SERIAL_SAMSUNG_CONSOLE=y CONFIG_HW_RANDOM=y # CONFIG_HWMON is not set # CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set CONFIG_EXT2_FS=y -CONFIG_INOTIFY=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y @@ -59,10 +55,7 @@ CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_SPINLOCK_SLEEP=y CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y CONFIG_EARLY_PRINTK=y CONFIG_DEBUG_S3C_UART=1 diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index 777c9e986425..1d0eb07db618 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -44,7 +44,6 @@ CONFIG_IP_PNP_RARP=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_INET6_XFRM_MODE_TRANSPORT is not set # CONFIG_INET6_XFRM_MODE_TUNNEL is not set diff --git a/arch/arm/configs/shannon_defconfig b/arch/arm/configs/shannon_defconfig index e52395629810..de33abdeb6fa 100644 --- a/arch/arm/configs/shannon_defconfig +++ b/arch/arm/configs/shannon_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y @@ -17,8 +16,6 @@ CONFIG_UNIX=y CONFIG_INET=y # CONFIG_IPV6 is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_AMDSTD=y diff --git a/arch/arm/configs/simpad_defconfig b/arch/arm/configs/simpad_defconfig index d3358155bf8a..28d99d8895f9 100644 --- a/arch/arm/configs/simpad_defconfig +++ b/arch/arm/configs/simpad_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_LOCALVERSION="oe1" CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 @@ -33,18 +32,13 @@ CONFIG_IRCOMM=m CONFIG_IRTTY_SIR=m CONFIG_SA1100_FIR=m CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y @@ -107,5 +101,4 @@ CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig index d271b263f35d..7b36eeb928bb 100644 --- a/arch/arm/configs/spear13xx_defconfig +++ b/arch/arm/configs/spear13xx_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BLK_DEV_INITRD=y @@ -32,7 +31,6 @@ CONFIG_NET_IPIP=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_OF_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_FSMC=y @@ -73,9 +71,7 @@ CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PL061=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y -# CONFIG_HID_SUPPORT is not set CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig index 7ff23a077f5d..2c5e8df33191 100644 --- a/arch/arm/configs/spear3xx_defconfig +++ b/arch/arm/configs/spear3xx_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BLK_DEV_INITRD=y @@ -17,7 +16,6 @@ CONFIG_NET=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_OF_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_FSMC=y @@ -56,9 +54,7 @@ CONFIG_WATCHDOG=y CONFIG_ARM_SP805_WATCHDOG=y CONFIG_FB=y CONFIG_FB_ARMCLCD=y -# CONFIG_HID_SUPPORT is not set CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_MMC=y diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig index 7822980d7d55..124c244d8df1 100644 --- a/arch/arm/configs/spear6xx_defconfig +++ b/arch/arm/configs/spear6xx_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BLK_DEV_INITRD=y @@ -14,7 +13,6 @@ CONFIG_NET=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_OF_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_FSMC=y @@ -49,7 +47,6 @@ CONFIG_GPIO_PL061=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y CONFIG_ARM_SP805_WATCHDOG=y -# CONFIG_HID_SUPPORT is not set CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig index d8c529332fb4..9ea82c118661 100644 --- a/arch/arm/configs/spitz_defconfig +++ b/arch/arm/configs/spitz_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 @@ -30,26 +29,22 @@ CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_INET=y CONFIG_SYN_COOKIES=y -# CONFIG_INET_LRO is not set CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m CONFIG_IPV6_TUNNEL=m CONFIG_NETFILTER=y -CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m @@ -66,8 +61,6 @@ CONFIG_IRNET=m CONFIG_IRCOMM=m CONFIG_PXA_FICP=m CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m @@ -87,9 +80,7 @@ CONFIG_BT_HCIBTUART=m CONFIG_BT_HCIVHCI=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_ROM=y CONFIG_MTD_COMPLEX_MAPPINGS=y @@ -203,7 +194,6 @@ CONFIG_USB_EMI26=m CONFIG_USB_RIO500=m CONFIG_USB_LEGOTOWER=m CONFIG_USB_LCD=m -CONFIG_USB_LED=m CONFIG_USB_CYTHERM=m CONFIG_USB_IDMOUSE=m CONFIG_USB_GADGET=m @@ -221,7 +211,6 @@ CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y @@ -243,9 +232,7 @@ CONFIG_NLS_UTF8=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_PREEMPT is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_FTRACE is not set -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_TEST=m diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig index 5cd5dd70bc83..0ec1d1ec130f 100644 --- a/arch/arm/configs/sunxi_defconfig +++ b/arch/arm/configs/sunxi_defconfig @@ -27,7 +27,6 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_CAN=y diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig index 7209a2caefcf..a3494dde2bfa 100644 --- a/arch/arm/configs/tct_hammer_defconfig +++ b/arch/arm/configs/tct_hammer_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set # CONFIG_SWAP is not set CONFIG_SYSVIPC=y @@ -26,8 +25,6 @@ CONFIG_UNIX=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_PREVENT_FIRMWARE_BUILD is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y @@ -36,7 +33,6 @@ CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_PHYSMAP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=10240 -# CONFIG_MISC_DEVICES is not set # CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set @@ -45,9 +41,7 @@ CONFIG_BLK_DEV_RAM_SIZE=10240 # CONFIG_HW_RANDOM is not set # CONFIG_HWMON is not set # CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_MON=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_GADGET=y @@ -64,6 +58,5 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_ENABLE_MUST_CHECK is not set CONFIG_DEBUG_KERNEL=y # CONFIG_DETECT_SOFTLOCKUP is not set -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y CONFIG_CRC_CCITT=y diff --git a/arch/arm/configs/trizeps4_defconfig b/arch/arm/configs/trizeps4_defconfig index 492f7f3eb4ac..2b5a224d2da1 100644 --- a/arch/arm/configs/trizeps4_defconfig +++ b/arch/arm/configs/trizeps4_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y @@ -38,7 +37,6 @@ CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y # CONFIG_IPV6 is not set CONFIG_NETFILTER=y -CONFIG_IP_NF_QUEUE=m CONFIG_VLAN_8021Q=m CONFIG_IRDA=m CONFIG_IRLAN=m @@ -49,8 +47,6 @@ CONFIG_IRDA_CACHE_LAST_LSAP=y CONFIG_IRDA_FAST_RR=y CONFIG_IRTTY_SIR=m CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m @@ -60,11 +56,9 @@ CONFIG_BT_HIDP=m CONFIG_CFG80211=y CONFIG_CONNECTOR=y CONFIG_MTD=y -CONFIG_MTD_CONCAT=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y CONFIG_MTD_REDBOOT_PARTS_READONLY=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y @@ -163,7 +157,6 @@ CONFIG_SND_PXA2XX_AC97=y CONFIG_SND_USB_AUDIO=m # CONFIG_USB_HID is not set CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_OHCI_HCD=y CONFIG_USB_STORAGE=m CONFIG_USB_SERIAL=m @@ -183,7 +176,6 @@ CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -CONFIG_INOTIFY=y CONFIG_AUTOFS4_FS=y CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig index aaa95ab606a8..36d77406e31b 100644 --- a/arch/arm/configs/u300_defconfig +++ b/arch/arm/configs/u300_defconfig @@ -49,7 +49,6 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_USB_SUPPORT is not set CONFIG_MMC=y -CONFIG_MMC_UNSAFE_RESUME=y # CONFIG_MMC_BLOCK_BOUNCE is not set CONFIG_MMC_ARMMMCI=y CONFIG_RTC_CLASS=y diff --git a/arch/arm/configs/vexpress_defconfig b/arch/arm/configs/vexpress_defconfig index 37fe607a4ede..0fa0ed577b15 100644 --- a/arch/arm/configs/vexpress_defconfig +++ b/arch/arm/configs/vexpress_defconfig @@ -46,7 +46,6 @@ CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y -# CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set CONFIG_NET_9P=y diff --git a/arch/arm/configs/viper_defconfig b/arch/arm/configs/viper_defconfig index 0d717a5eff29..44d4fa57ba0a 100644 --- a/arch/arm/configs/viper_defconfig +++ b/arch/arm/configs/viper_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=13 @@ -34,10 +33,8 @@ CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_SYN_COOKIES=y -# CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_BT=m -CONFIG_BT_L2CAP=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m @@ -49,7 +46,6 @@ CONFIG_FW_LOADER=m CONFIG_MTD=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=0 -CONFIG_MTD_CHAR=m CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y @@ -72,8 +68,6 @@ CONFIG_PATA_PCMCIA=m CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_SMC91X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set CONFIG_USB_PEGASUS=m CONFIG_USB_USBNET=m # CONFIG_USB_NET_CDC_SUBSET is not set @@ -148,7 +142,6 @@ CONFIG_EXT2_FS=m CONFIG_EXT3_FS=m # CONFIG_EXT3_FS_XATTR is not set # CONFIG_DNOTIFY is not set -CONFIG_INOTIFY=y CONFIG_VFAT_FS=m CONFIG_JFFS2_FS=y CONFIG_NFS_FS=y @@ -165,9 +158,7 @@ CONFIG_NLS_UTF8=m CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MUTEXES=y -CONFIG_SYSCTL_SYSCALL_CHECK=y # CONFIG_FTRACE is not set -CONFIG_DEBUG_ERRORS=y CONFIG_CRYPTO_ECB=m CONFIG_CRYPTO_ARC4=m CONFIG_CRC_T10DIF=m diff --git a/arch/arm/configs/xcep_defconfig b/arch/arm/configs/xcep_defconfig index 721832ffe2d7..2eda24635e65 100644 --- a/arch/arm/configs/xcep_defconfig +++ b/arch/arm/configs/xcep_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_LOCALVERSION=".xcep-itech" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y @@ -47,14 +46,10 @@ CONFIG_IP_PNP_BOOTP=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_FW_LOADER is not set -CONFIG_MTD_CONCAT=y CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_PXA2XX=y -# CONFIG_MISC_DEVICES is not set CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set # CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set @@ -71,7 +66,6 @@ CONFIG_HWMON=m CONFIG_SENSORS_ADM1021=m CONFIG_SENSORS_MAX6650=m # CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_SA1100=m @@ -90,8 +84,6 @@ CONFIG_STRIP_ASM_SYMS=y CONFIG_DEBUG_KERNEL=y # CONFIG_SCHED_DEBUG is not set # CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y # CONFIG_FTRACE is not set # CONFIG_ARM_UNWIND is not set # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/arm/configs/zeus_defconfig b/arch/arm/configs/zeus_defconfig index cd11da8b5123..8d4c0c926c34 100644 --- a/arch/arm/configs/zeus_defconfig +++ b/arch/arm/configs/zeus_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_TINY_RCU=y CONFIG_LOG_BUF_SHIFT=13 @@ -29,10 +28,8 @@ CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_SYN_COOKIES=y -# CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_BT=m -CONFIG_BT_L2CAP=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m @@ -46,7 +43,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_PARTS_READONLY=y -CONFIG_MTD_CHAR=m CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y @@ -70,8 +66,6 @@ CONFIG_PATA_PCMCIA=m CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_DM9000=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set CONFIG_HERMES=m CONFIG_PCMCIA_HERMES=m CONFIG_RT2X00=m @@ -130,7 +124,6 @@ CONFIG_SND_PXA2XX_AC97=m # CONFIG_SND_PCMCIA is not set CONFIG_SND_SOC=m CONFIG_SND_PXA2XX_SOC=m -# CONFIG_HID_SUPPORT is not set CONFIG_USB=m CONFIG_USB_OHCI_HCD=m CONFIG_USB_ACM=m @@ -164,7 +157,6 @@ CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set # CONFIG_DNOTIFY is not set -CONFIG_INOTIFY=y CONFIG_VFAT_FS=m CONFIG_TMPFS=y CONFIG_JFFS2_FS=y @@ -182,7 +174,5 @@ CONFIG_NLS_UTF8=m CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MUTEXES=y -CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_DEBUG_ERRORS=y # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRC_T10DIF=m diff --git a/arch/arm/configs/zx_defconfig b/arch/arm/configs/zx_defconfig index d6253a48a9fa..dfc061d87d2f 100644 --- a/arch/arm/configs/zx_defconfig +++ b/arch/arm/configs/zx_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y @@ -79,7 +78,6 @@ CONFIG_SERIAL_OF_PLATFORM=y # CONFIG_HWMON is not set # CONFIG_USB_SUPPORT is not set CONFIG_MMC=y -CONFIG_MMC_UNSAFE_RESUME=y CONFIG_MMC_BLOCK_MINORS=16 CONFIG_MMC_DW=y CONFIG_EXT2_FS=y -- cgit v1.2.3 From 2a7ae1c04983e5e1fd25baacce25562931893852 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 8 Jun 2017 16:41:36 +0200 Subject: ARM: defconfig: samsung: Re-order entries to match savedefconfig Re-order entries just like savedefconfig would do so it will be easier to review the changes before actual savedefconfig. Signed-off-by: Krzysztof Kozlowski Acked-by: Arnd Bergmann --- arch/arm/configs/exynos_defconfig | 4 ++-- arch/arm/configs/mini2440_defconfig | 47 ++++++++++++++++++------------------- arch/arm/configs/s3c2410_defconfig | 6 ++--- arch/arm/configs/s3c6400_defconfig | 2 +- arch/arm/configs/s5pv210_defconfig | 12 +++++----- 5 files changed, 35 insertions(+), 36 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 6dc661c4a2c1..267a2df9ff38 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -74,6 +74,7 @@ CONFIG_MWIFIEX=m CONFIG_MWIFIEX_SDIO=m CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_SAMSUNG=y CONFIG_KEYBOARD_CROS_EC=y # CONFIG_MOUSE_PS2 is not set CONFIG_MOUSE_CYAPA=y @@ -83,7 +84,6 @@ CONFIG_TOUCHSCREEN_MMS114=y CONFIG_INPUT_MISC=y CONFIG_INPUT_MAX77693_HAPTIC=y CONFIG_INPUT_MAX8997_HAPTIC=y -CONFIG_KEYBOARD_SAMSUNG=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_SAMSUNG=y @@ -158,6 +158,7 @@ CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m CONFIG_VIDEO_SAMSUNG_S5P_MFC=m CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m CONFIG_V4L_TEST_DRIVERS=y +CONFIG_VIDEO_VIVID=m CONFIG_DRM=y CONFIG_DRM_EXYNOS=y CONFIG_DRM_EXYNOS_FIMD=y @@ -274,4 +275,3 @@ CONFIG_CRYPTO_AES_ARM_BS=m CONFIG_CRC_CCITT=y CONFIG_FONTS=y CONFIG_FONT_7x14=y -CONFIG_VIDEO_VIVID=m diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig index f48bc89de871..e621032ab1f0 100644 --- a/arch/arm/configs/mini2440_defconfig +++ b/arch/arm/configs/mini2440_defconfig @@ -12,12 +12,18 @@ CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y CONFIG_ARCH_S3C24XX=y # CONFIG_CPU_S3C2410 is not set CONFIG_CPU_S3C2440=y +CONFIG_MACH_MINI2440=y CONFIG_S3C_ADC=y CONFIG_S3C24XX_PWM=y -CONFIG_MACH_MINI2440=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set CONFIG_KEXEC=y @@ -103,6 +109,7 @@ CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=65536 CONFIG_CDROM_PKTCDVD=m CONFIG_SENSORS_TSL2550=m +CONFIG_EEPROM_AT24=y CONFIG_SCSI=m # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=m @@ -112,6 +119,14 @@ CONFIG_NETDEVICES=y CONFIG_TUN=m CONFIG_NET_ETHERNET=y CONFIG_DM9000=y +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m CONFIG_HOSTAP=m CONFIG_HOSTAP_FIRMWARE=y CONFIG_HOSTAP_FIRMWARE_NVRAM=y @@ -119,14 +134,6 @@ CONFIG_LIBERTAS=m CONFIG_LIBERTAS_SDIO=m CONFIG_ZD1211RW=m CONFIG_ZD1211RW_DEBUG=y -CONFIG_PPP=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_MPPE=m CONFIG_INPUT_FF_MEMLESS=y CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVBUG=m @@ -135,9 +142,9 @@ CONFIG_KEYBOARD_GPIO=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_SERIO_RAW=y CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_LEGACY_PTY_COUNT=128 CONFIG_SERIAL_SAMSUNG=y CONFIG_SERIAL_SAMSUNG_CONSOLE=y -CONFIG_LEGACY_PTY_COUNT=128 CONFIG_IPMI_HANDLER=m CONFIG_IPMI_DEVICE_INTERFACE=m CONFIG_IPMI_SI=m @@ -148,7 +155,6 @@ CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_S3C2410=y CONFIG_I2C_SIMTEC=y -CONFIG_EEPROM_AT24=y CONFIG_SPI=y CONFIG_SPI_S3C24XX=y CONFIG_SPI_SPIDEV=y @@ -172,9 +178,6 @@ CONFIG_BACKLIGHT_PWM=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FONTS=y -CONFIG_FONT_8x8=y -CONFIG_FONT_MINI_4x6=y CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set # CONFIG_LOGO_LINUX_VGA16 is not set @@ -195,8 +198,6 @@ CONFIG_SND_USB_CAIAQ_INPUT=y CONFIG_SND_SOC=y CONFIG_SND_S3C24XX_SOC=y CONFIG_HIDRAW=y -CONFIG_HID_PID=y -CONFIG_USB_HIDDEV=y CONFIG_HID_GYRATION=y CONFIG_HID_NTRIG=y CONFIG_HID_PANTHERLORD=y @@ -205,6 +206,8 @@ CONFIG_HID_SAMSUNG=y CONFIG_HID_SONY=y CONFIG_HID_SUNPLUS=y CONFIG_HID_TOPSEED=y +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y CONFIG_USB=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_ACM=m @@ -267,13 +270,6 @@ CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_BSD_DISKLABEL=y -CONFIG_MINIX_SUBPARTITION=y -CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_UNIXWARE_DISKLABEL=y -CONFIG_LDM_PARTITION=y -CONFIG_EFI_PARTITION=y CONFIG_NLS_DEFAULT="cp437" CONFIG_NLS_CODEPAGE_437=m CONFIG_NLS_CODEPAGE_737=m @@ -313,13 +309,13 @@ CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m CONFIG_NLS_UTF8=m +CONFIG_DEBUG_INFO=y # CONFIG_ENABLE_WARN_DEPRECATED is not set # CONFIG_ENABLE_MUST_CHECK is not set CONFIG_STRIP_ASM_SYMS=y CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y # CONFIG_SCHED_DEBUG is not set -CONFIG_DEBUG_INFO=y CONFIG_DEBUG_USER=y CONFIG_KEYS=y CONFIG_CRYPTO_FIPS=y @@ -364,3 +360,6 @@ CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=m CONFIG_CRC_T10DIF=y CONFIG_LIBCRC32C=m +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_MINI_4x6=y diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig index 6349fc988a0f..dc3469d9da26 100644 --- a/arch/arm/configs/s3c2410_defconfig +++ b/arch/arm/configs/s3c2410_defconfig @@ -12,7 +12,6 @@ CONFIG_BSD_DISKLABEL=y CONFIG_SOLARIS_X86_PARTITION=y CONFIG_ARCH_S3C24XX=y CONFIG_S3C_BOOT_ERROR_RESET=y -CONFIG_S3C_ADC=y CONFIG_S3C24XX_PWM=y CONFIG_CPU_S3C2412=y CONFIG_CPU_S3C2416=y @@ -45,6 +44,7 @@ CONFIG_MACH_RX1950=y CONFIG_SMDK2440_CPU2442=y CONFIG_MACH_SMDK2443=y # CONFIG_ARM_THUMB is not set +CONFIG_S3C_ADC=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="root=/dev/hda1 ro init=/bin/bash console=ttySAC0" @@ -211,6 +211,7 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_ATA_OVER_ETH=m +CONFIG_EEPROM_AT24=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=m CONFIG_BLK_DEV_SR=y @@ -277,7 +278,6 @@ CONFIG_HW_RANDOM=y CONFIG_I2C_CHARDEV=m CONFIG_I2C_S3C2410=y CONFIG_I2C_SIMTEC=y -CONFIG_EEPROM_AT24=y CONFIG_SPI=y CONFIG_SPI_GPIO=m CONFIG_SPI_S3C24XX=m @@ -442,10 +442,10 @@ CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m CONFIG_NLS_UTF8=m +CONFIG_DEBUG_INFO=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_INFO=y CONFIG_DEBUG_USER=y CONFIG_DEBUG_LL=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig index ccc908f3aa3a..97e377a4c118 100644 --- a/arch/arm/configs/s3c6400_defconfig +++ b/arch/arm/configs/s3c6400_defconfig @@ -80,12 +80,12 @@ CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_CRAMFS=y CONFIG_ROMFS_FS=y +CONFIG_DEBUG_INFO=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_SPINLOCK_SLEEP=y -CONFIG_DEBUG_INFO=y CONFIG_DEBUG_USER=y CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/s5pv210_defconfig b/arch/arm/configs/s5pv210_defconfig index 38bee3209c0b..4e0138993626 100644 --- a/arch/arm/configs/s5pv210_defconfig +++ b/arch/arm/configs/s5pv210_defconfig @@ -1,15 +1,18 @@ +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y CONFIG_KALLSYMS_ALL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +CONFIG_BSD_DISKLABEL=y +CONFIG_SOLARIS_X86_PARTITION=y CONFIG_ARCH_S5PV210=y CONFIG_S3C_LOWLEVEL_UART_PORT=1 CONFIG_S3C_DEV_FB=y CONFIG_S5PV210_SETUP_FB_24BPP=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y CONFIG_VMSPLIT_2G=y CONFIG_PREEMPT=y CONFIG_AEABI=y @@ -41,12 +44,10 @@ CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_CRAMFS=y CONFIG_ROMFS_FS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_BSD_DISKLABEL=y -CONFIG_SOLARIS_X86_PARTITION=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y +CONFIG_DEBUG_INFO=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_PREEMPT is not set @@ -54,7 +55,6 @@ CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_SPINLOCK_SLEEP=y -CONFIG_DEBUG_INFO=y CONFIG_DEBUG_USER=y CONFIG_DEBUG_LL=y CONFIG_EARLY_PRINTK=y -- cgit v1.2.3 From c5f6fc414968d35acadd48f2402d8dae86be1784 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 8 Jun 2017 16:41:38 +0200 Subject: ARM: mini2440_defconfig: Bring back lost (but wanted) options The config was not updated for some time so it needs updates to get the same options as wanted initially: - SERIAL_DEV_BUS is now needed for BT_HCIUART_LL; - USB_GADGET_S3C2410 was replaced by USB_S3C2410; - S3C24XX_DMAC is now needed for MMC_S3C; Signed-off-by: Krzysztof Kozlowski Acked-by: Arnd Bergmann --- arch/arm/configs/mini2440_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig index e621032ab1f0..45ce98d5392d 100644 --- a/arch/arm/configs/mini2440_defconfig +++ b/arch/arm/configs/mini2440_defconfig @@ -145,6 +145,7 @@ CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_LEGACY_PTY_COUNT=128 CONFIG_SERIAL_SAMSUNG=y CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=m CONFIG_IPMI_HANDLER=m CONFIG_IPMI_DEVICE_INTERFACE=m CONFIG_IPMI_SI=m @@ -225,7 +226,7 @@ CONFIG_USB_SERIAL_CP210X=m CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_USB_SERIAL_SPCP8X5=m CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_S3C2410=y +CONFIG_USB_S3C2410=y CONFIG_USB_ZERO=m CONFIG_USB_ETH=m CONFIG_USB_GADGETFS=m @@ -248,6 +249,7 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_INTF_DEV_UIE_EMUL=y CONFIG_RTC_DRV_S3C=y CONFIG_DMADEVICES=y +CONFIG_S3C24XX_DMAC=y CONFIG_EXT2_FS=m CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y -- cgit v1.2.3 From dd48d06b379289a4e7bef7ba573a0190a945ef91 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 8 Jun 2017 16:41:40 +0200 Subject: ARM: tct_hammer_defconfig: Bring back lost (but wanted) options The config was not updated for some time so it needs updates to get the same options as wanted initially: - SYSFS_DEPRECATED is now needed for SYSFS_DEPRECATED_V2; - USB_GADGET_S3C2410 was replaced by USB_S3C2410; Signed-off-by: Krzysztof Kozlowski Acked-by: Arnd Bergmann --- arch/arm/configs/tct_hammer_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig index a3494dde2bfa..71a2e0fb70f5 100644 --- a/arch/arm/configs/tct_hammer_defconfig +++ b/arch/arm/configs/tct_hammer_defconfig @@ -2,6 +2,7 @@ # CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y @@ -45,7 +46,7 @@ CONFIG_USB=y CONFIG_USB_MON=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_S3C2410=y +CONFIG_USB_S3C2410=y CONFIG_USB_ETH=m CONFIG_EXT2_FS=y # CONFIG_DNOTIFY is not set -- cgit v1.2.3 From 930e4386274dd13eb4c79ffc9f7715abb46c56d4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 8 Jun 2017 16:41:43 +0200 Subject: ARM: s3c2410_defconfig: Bring back lost (but wanted) options The config was not updated for some time so it needs updates to get the same options as wanted initially: - IP_NF_TARGET_LOG was replaced by NETFILTER_XT_TARGET_LOG; - NF_NAT was replaced by IP_NF_NAT; - SERIAL_DEV_BUS is now needed for BT_HCIUART_LL; - TPS65010 is now needed for MACH_OSIRIS_DVS; - DMADEVICES and S3C24XX_DMAC are now needed for MMC_S3C; Signed-off-by: Krzysztof Kozlowski Acked-by: Arnd Bergmann --- arch/arm/configs/s3c2410_defconfig | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig index dc3469d9da26..aacc788f5d55 100644 --- a/arch/arm/configs/s3c2410_defconfig +++ b/arch/arm/configs/s3c2410_defconfig @@ -100,6 +100,7 @@ CONFIG_NF_CT_NETLINK=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m @@ -143,8 +144,7 @@ CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_NF_NAT=m +CONFIG_IP_NF_NAT=m CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m @@ -272,6 +272,7 @@ CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_SAMSUNG=y CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=m CONFIG_PRINTER=y CONFIG_PPDEV=y CONFIG_HW_RANDOM=y @@ -289,6 +290,7 @@ CONFIG_SENSORS_LM85=m CONFIG_WATCHDOG=y CONFIG_S3C2410_WATCHDOG=y CONFIG_MFD_SM501=y +CONFIG_TPS65010=y CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_MODE_HELPERS=y @@ -372,6 +374,8 @@ CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_S3C=y +CONFIG_DMADEVICES=y +CONFIG_S3C24XX_DMAC=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y -- cgit v1.2.3 From 61d26c612d07c75bef9d737d8da890243671ee2b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 8 Jun 2017 16:41:45 +0200 Subject: ARM: s3c6400_defconfig: Bring back lost (but wanted) options The config was not updated for some time so it needs updates to get the same options as wanted initially: - SYSFS_DEPRECATED is now needed for SYSFS_DEPRECATED_V2; - PWM is now needed for BACKLIGHT_PWM; - DEBUG_SPINLOCK_SLEEP was replaced by DEBUG_ATOMIC_SLEEP; Signed-off-by: Krzysztof Kozlowski Acked-by: Arnd Bergmann --- arch/arm/configs/s3c6400_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig index 97e377a4c118..8979e343d255 100644 --- a/arch/arm/configs/s3c6400_defconfig +++ b/arch/arm/configs/s3c6400_defconfig @@ -1,3 +1,4 @@ +CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y CONFIG_KALLSYMS_ALL=y @@ -72,6 +73,7 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S3C=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_S3C=y +CONFIG_PWM=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_POSIX_ACL=y @@ -86,6 +88,6 @@ CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_SPINLOCK_SLEEP=y +CONFIG_DEBUG_ATOMIC_SLEEP=y CONFIG_DEBUG_USER=y CONFIG_DEBUG_LL=y -- cgit v1.2.3 From fdf5f61b692c5c9b4f8c7f6b4f1fd18f47635633 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 8 Jun 2017 16:41:48 +0200 Subject: ARM: s5pv210_defconfig: Bring back lost (but wanted) options The config was not updated for some time so it needs updates to get the same options as wanted initially: - SYSFS_DEPRECATED is now needed for SYSFS_DEPRECATED_V2; - DEBUG_SPINLOCK_SLEEP was replaced by DEBUG_ATOMIC_SLEEP; - Use proper DEBUG_S3C_UART1 for UART1; Signed-off-by: Krzysztof Kozlowski Acked-by: Arnd Bergmann --- arch/arm/configs/s5pv210_defconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/s5pv210_defconfig b/arch/arm/configs/s5pv210_defconfig index 4e0138993626..ddf7f75ba8d9 100644 --- a/arch/arm/configs/s5pv210_defconfig +++ b/arch/arm/configs/s5pv210_defconfig @@ -1,5 +1,6 @@ CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y CONFIG_KALLSYMS_ALL=y @@ -54,9 +55,9 @@ CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_SPINLOCK_SLEEP=y +CONFIG_DEBUG_ATOMIC_SLEEP=y CONFIG_DEBUG_USER=y CONFIG_DEBUG_LL=y +CONFIG_DEBUG_S3C_UART1=y CONFIG_EARLY_PRINTK=y -CONFIG_DEBUG_S3C_UART=1 CONFIG_CRC_CCITT=y -- cgit v1.2.3 From e5094f9c569e78e15e828139a56015a2f7a59f04 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 8 Jun 2017 16:41:50 +0200 Subject: ARM: exynos_defconfig: Save defconfig Generate new defconfig to get rid of obsolete Kconfig entries: - RFKILL_REGULATOR is gone; - COMMON_CLK_MAX77802 was merged into COMMON_CLK_MAX77686; Signed-off-by: Krzysztof Kozlowski Acked-by: Arnd Bergmann --- arch/arm/configs/exynos_defconfig | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 267a2df9ff38..0c914b76fe14 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -49,7 +49,6 @@ CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y CONFIG_CFG80211=y -CONFIG_RFKILL_REGULATOR=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_DMA_CMA=y @@ -221,7 +220,6 @@ CONFIG_DMADEVICES=y CONFIG_PL330_DMA=y CONFIG_CROS_EC_CHARDEV=y CONFIG_COMMON_CLK_MAX77686=y -CONFIG_COMMON_CLK_MAX77802=y CONFIG_COMMON_CLK_S2MPS11=y CONFIG_PM_DEVFREQ=y CONFIG_DEVFREQ_GOV_PERFORMANCE=y -- cgit v1.2.3 From 68d1719fbac0edeff9888531fc8bb1988caa5335 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 8 Jun 2017 16:41:52 +0200 Subject: ARM: s3c2410_defconfig: Save defconfig Generate new defconfig to get rid of obsolete Kconfig entries: - S3C_BOOT_ERROR_RESET, SMDK2440_CPU2442 are gone; - ARM_THUMB is changed to yes (selected by default); - BINFMT_AOUT cannot be selected anymore; - rest of entries is being removed by default values; Signed-off-by: Krzysztof Kozlowski Acked-by: Arnd Bergmann --- arch/arm/configs/s3c2410_defconfig | 13 ------------- 1 file changed, 13 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig index aacc788f5d55..2afb359f3168 100644 --- a/arch/arm/configs/s3c2410_defconfig +++ b/arch/arm/configs/s3c2410_defconfig @@ -11,8 +11,6 @@ CONFIG_PARTITION_ADVANCED=y CONFIG_BSD_DISKLABEL=y CONFIG_SOLARIS_X86_PARTITION=y CONFIG_ARCH_S3C24XX=y -CONFIG_S3C_BOOT_ERROR_RESET=y -CONFIG_S3C24XX_PWM=y CONFIG_CPU_S3C2412=y CONFIG_CPU_S3C2416=y CONFIG_CPU_S3C2440=y @@ -41,16 +39,13 @@ CONFIG_MACH_RX3715=y CONFIG_ARCH_S3C2440=y CONFIG_MACH_NEO1973_GTA02=y CONFIG_MACH_RX1950=y -CONFIG_SMDK2440_CPU2442=y CONFIG_MACH_SMDK2443=y -# CONFIG_ARM_THUMB is not set CONFIG_S3C_ADC=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="root=/dev/hda1 ro init=/bin/bash console=ttySAC0" CONFIG_FPE_NWFPE=y CONFIG_FPE_NWFPE_XP=y -CONFIG_BINFMT_AOUT=y CONFIG_APM_EMULATION=m CONFIG_NET=y CONFIG_PACKET=y @@ -84,9 +79,6 @@ CONFIG_IPV6_TUNNEL=m CONFIG_NETFILTER=y CONFIG_NF_CONNTRACK=m CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CT_PROTO_DCCP=y -CONFIG_NF_CT_PROTO_SCTP=y -CONFIG_NF_CT_PROTO_UDPLITE=y CONFIG_NF_CONNTRACK_AMANDA=m CONFIG_NF_CONNTRACK_FTP=m CONFIG_NF_CONNTRACK_H323=m @@ -179,7 +171,6 @@ CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_HIDP=m CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_LL=y CONFIG_BT_HCIBCM203X=m @@ -382,8 +373,6 @@ CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT4_FS=m -CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m CONFIG_ISO9660_FS=y @@ -401,7 +390,6 @@ CONFIG_CRAMFS=y CONFIG_SQUASHFS=m CONFIG_ROMFS_FS=y CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_ROOT_NFS=y CONFIG_NFSD=m @@ -452,4 +440,3 @@ CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_USER=y CONFIG_DEBUG_LL=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -- cgit v1.2.3 From a13a047520c0f9b958255c61f1004a72a5acfd7b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 8 Jun 2017 16:41:55 +0200 Subject: ARM: mini2440_defconfig: Save defconfig Generate new defconfig to get rid of obsolete Kconfig entries: - NET_ETHERNET, SND_S3C24XX_SOC are gone; - CRYPTO_FIPS is changed to no (cannot be part of module); - BINFMT_AOUT cannot be selected anymore; - rest of entries is being removed by default values; Signed-off-by: Krzysztof Kozlowski Acked-by: Arnd Bergmann --- arch/arm/configs/mini2440_defconfig | 21 --------------------- 1 file changed, 21 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig index 45ce98d5392d..cf7dcb2c86e6 100644 --- a/arch/arm/configs/mini2440_defconfig +++ b/arch/arm/configs/mini2440_defconfig @@ -2,8 +2,6 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_RELAY=y -CONFIG_UTS_NS=y -CONFIG_IPC_NS=y CONFIG_BLK_DEV_INITRD=y # CONFIG_COMPAT_BRK is not set CONFIG_MODULES=y @@ -25,12 +23,9 @@ CONFIG_MACH_MINI2440=y CONFIG_S3C_ADC=y CONFIG_S3C24XX_PWM=y CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set CONFIG_KEXEC=y CONFIG_CPU_IDLE=y -CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m -CONFIG_PM=y CONFIG_APM_EMULATION=y CONFIG_NET=y CONFIG_PACKET=y @@ -71,7 +66,6 @@ CONFIG_BT_HIDP=m CONFIG_BT_HCIBTUSB=m CONFIG_BT_HCIBTSDIO=m CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_LL=y CONFIG_BT_HCIBCM203X=m @@ -117,7 +111,6 @@ CONFIG_CHR_DEV_SG=m # CONFIG_SCSI_LOWLEVEL is not set CONFIG_NETDEVICES=y CONFIG_TUN=m -CONFIG_NET_ETHERNET=y CONFIG_DM9000=y CONFIG_PPP=m CONFIG_PPP_BSDCOMP=m @@ -141,7 +134,6 @@ CONFIG_INPUT_EVBUG=m CONFIG_KEYBOARD_GPIO=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_SERIO_RAW=y -CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_LEGACY_PTY_COUNT=128 CONFIG_SERIAL_SAMSUNG=y CONFIG_SERIAL_SAMSUNG_CONSOLE=y @@ -175,7 +167,6 @@ CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_PWM=y -# CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y @@ -197,7 +188,6 @@ CONFIG_SND_USB_AUDIO=m CONFIG_SND_USB_CAIAQ=m CONFIG_SND_USB_CAIAQ_INPUT=y CONFIG_SND_SOC=y -CONFIG_SND_S3C24XX_SOC=y CONFIG_HIDRAW=y CONFIG_HID_GYRATION=y CONFIG_HID_NTRIG=y @@ -238,7 +228,6 @@ CONFIG_SDIO_UART=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SPI=y CONFIG_MMC_S3C=y -CONFIG_LEDS_CLASS=y CONFIG_LEDS_S3C24XX=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_TRIGGER_TIMER=y @@ -262,13 +251,11 @@ CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y -CONFIG_CONFIGFS_FS=m CONFIG_JFFS2_FS=y CONFIG_CRAMFS=y CONFIG_ROMFS_FS=y CONFIG_ROMFS_BACKED_BY_BOTH=y CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y CONFIG_ROOT_NFS=y @@ -319,14 +306,9 @@ CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y # CONFIG_SCHED_DEBUG is not set CONFIG_DEBUG_USER=y -CONFIG_KEYS=y -CONFIG_CRYPTO_FIPS=y -CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_AUTHENC=m CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_CCM=m -CONFIG_CRYPTO_GCM=m CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_LRW=m @@ -340,11 +322,9 @@ CONFIG_CRYPTO_RMD128=m CONFIG_CRYPTO_RMD160=m CONFIG_CRYPTO_RMD256=m CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_ANUBIS=m CONFIG_CRYPTO_ARC4=y CONFIG_CRYPTO_BLOWFISH=m @@ -360,7 +340,6 @@ CONFIG_CRYPTO_TEA=m CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=m -CONFIG_CRC_T10DIF=y CONFIG_LIBCRC32C=m CONFIG_FONTS=y CONFIG_FONT_8x8=y -- cgit v1.2.3 From c2a3f4cca563a845fdc030f9f84f413fd8610684 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 8 Jun 2017 16:41:58 +0200 Subject: ARM: s3c6400_defconfig: Save defconfig Generate new defconfig to get rid of obsolete Kconfig entries: - S3C_BOOT_ERROR_RESET, SND_S3C24XX_SOC and SND_SOC_SMDK_WM9713 are gone; - rest of entries is being removed by default values; Signed-off-by: Krzysztof Kozlowski Acked-by: Arnd Bergmann --- arch/arm/configs/s3c6400_defconfig | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig index 8979e343d255..507d7ad7523a 100644 --- a/arch/arm/configs/s3c6400_defconfig +++ b/arch/arm/configs/s3c6400_defconfig @@ -8,7 +8,6 @@ CONFIG_MODULE_UNLOAD=y CONFIG_ARCH_MULTI_V6=y # CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_S3C64XX=y -CONFIG_S3C_BOOT_ERROR_RESET=y CONFIG_MACH_SMDK6400=y CONFIG_MACH_ANW6410=y CONFIG_MACH_MINI6410=y @@ -19,11 +18,9 @@ CONFIG_MACH_HMT=y CONFIG_MACH_SMARTQ5=y CONFIG_MACH_SMARTQ7=y CONFIG_MACH_WLF_CRAGG_6410=y -CONFIG_CPU_32v6K=y CONFIG_AEABI=y CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/linuxrc initrd=0x51000000,6M ramdisk_size=6144" CONFIG_VFP=y -CONFIG_PM=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_NAND=y @@ -48,14 +45,11 @@ CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_LTV350QV=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y -# CONFIG_VGA_CONSOLE is not set CONFIG_SOUND=y CONFIG_SND=m CONFIG_SND_MIXER_OSS=m CONFIG_SND_PCM_OSS=m CONFIG_SND_SOC=m -CONFIG_SND_S3C24XX_SOC=m -CONFIG_SND_SOC_SMDK_WM9713=m CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_OHCI_HCD=y -- cgit v1.2.3 From e4025945886b81f27e336c4d6038cff62b0d9153 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 8 Jun 2017 16:42:00 +0200 Subject: ARM: s5pv210_defconfig: Save defconfig Generate new defconfig to get rid of obsolete Kconfig entries: - S3C_LOWLEVEL_UART_PORT and S3C_DEV_FB are invalid for S5P; - S5PV210_SETUP_FB_24BPP is gone; - rest of entries is being removed by default values; Signed-off-by: Krzysztof Kozlowski Acked-by: Arnd Bergmann --- arch/arm/configs/s5pv210_defconfig | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/s5pv210_defconfig b/arch/arm/configs/s5pv210_defconfig index ddf7f75ba8d9..09b5a7386414 100644 --- a/arch/arm/configs/s5pv210_defconfig +++ b/arch/arm/configs/s5pv210_defconfig @@ -11,9 +11,6 @@ CONFIG_PARTITION_ADVANCED=y CONFIG_BSD_DISKLABEL=y CONFIG_SOLARIS_X86_PARTITION=y CONFIG_ARCH_S5PV210=y -CONFIG_S3C_LOWLEVEL_UART_PORT=1 -CONFIG_S3C_DEV_FB=y -CONFIG_S5PV210_SETUP_FB_24BPP=y CONFIG_VMSPLIT_2G=y CONFIG_PREEMPT=y CONFIG_AEABI=y @@ -36,7 +33,6 @@ CONFIG_SERIAL_SAMSUNG=y CONFIG_SERIAL_SAMSUNG_CONSOLE=y CONFIG_HW_RANDOM=y # CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set # CONFIG_USB_SUPPORT is not set CONFIG_EXT2_FS=y CONFIG_MSDOS_FS=y -- cgit v1.2.3 From 794b77738c0dede15441209a56044fd67c48a200 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 8 Jun 2017 16:42:03 +0200 Subject: ARM: tct_hammer_defconfig: Save defconfig Generate new defconfig to get rid of obsolete Kconfig entries: - BUGVERBOSE was changed into DEBUG_BUGVERBOSE and will be enabled by default (it is useful); - DETECT_SOFTLOCKUP was changed into LOCKUP_DETECTOR; - rest of entries is being removed by default values; Signed-off-by: Krzysztof Kozlowski Acked-by: Arnd Bergmann --- arch/arm/configs/tct_hammer_defconfig | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig index 71a2e0fb70f5..d0a9e5dd9135 100644 --- a/arch/arm/configs/tct_hammer_defconfig +++ b/arch/arm/configs/tct_hammer_defconfig @@ -7,7 +7,6 @@ CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set -# CONFIG_BUGVERBOSE is not set # CONFIG_ELF_CORE is not set # CONFIG_SHMEM is not set CONFIG_SLOB=y @@ -34,14 +33,12 @@ CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_PHYSMAP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=10240 -# CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_SERIO is not set # CONFIG_VT_CONSOLE is not set # CONFIG_HW_RANDOM is not set # CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set CONFIG_USB=y CONFIG_USB_MON=y CONFIG_USB_OHCI_HCD=y @@ -57,7 +54,5 @@ CONFIG_JFFS2_FS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y # CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DETECT_SOFTLOCKUP is not set CONFIG_DEBUG_LL=y CONFIG_CRC_CCITT=y -- cgit v1.2.3 From 6f0b0c03fb97596ca313435df8e5d3fc52e8d00c Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 2 May 2017 10:03:01 +0200 Subject: ARM: dts: omap4-droid4: Add isl29030 ALS/proximity sensor The Droid 4 has a isl29030 to measure ambient light (e.g. for automatically adapting display brightness) and proximity. Signed-off-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-droid4-xt894.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts index 13f8d8640208..935af4e8b33c 100644 --- a/arch/arm/boot/dts/omap4-droid4-xt894.dts +++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts @@ -348,6 +348,17 @@ interrupt-names = "irq", "wakeup"; wakeup-source; }; + + isl29030@44 { + compatible = "isil,isl29030"; + reg = <0x44>; + + pinctrl-names = "default"; + pinctrl-0 = <&als_proximity_pins>; + + interrupt-parent = <&gpio6>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; /* gpio177 */ + }; }; &omap4_pmx_core { @@ -395,6 +406,12 @@ >; }; + als_proximity_pins: pinmux_als_proximity_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x18c, PIN_INPUT_PULLUP | MUX_MODE3) + >; + }; + usb_ulpi_pins: pinmux_usb_ulpi_pins { pinctrl-single,pins = < OMAP4_IOPAD(0x196, MUX_MODE7) -- cgit v1.2.3 From d809f2cca354d88ccc19aad1ecbe54704448615e Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Thu, 8 Jun 2017 23:16:08 +0200 Subject: ARM: dts: omap4-droid4: Fix WLAN compatible Motorola Droid 4 uses a WL1285C, so use proper compatible value. To avoid regressions while support for the new compatible value is added to the Linux kernel, the old compatible value is preserved as fallback. Signed-off-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-droid4-xt894.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts index 935af4e8b33c..10ca1c174995 100644 --- a/arch/arm/boot/dts/omap4-droid4-xt894.dts +++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts @@ -301,7 +301,7 @@ #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { - compatible = "ti,wl1283"; + compatible = "ti,wl1285", "ti,wl1283"; reg = <2>; interrupt-parent = <&gpio4>; interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; /* gpio100 */ -- cgit v1.2.3 From 164a1a90a4ae54911f02a1b4fc6ea7148edf07cb Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Mon, 5 Jun 2017 17:18:46 +0930 Subject: arm: aspeed: Add clock-names property to timer node The merging of a number of clocksource drivers into fttmr010 means we require clock-names to be specified in the Aspeed timer node, else the clocksource fails to probe and boot hangs. Signed-off-by: Andrew Jeffery Signed-off-by: Daniel Lezcano --- arch/arm/boot/dts/aspeed-g4.dtsi | 1 + arch/arm/boot/dts/aspeed-g5.dtsi | 1 + 2 files changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 8c6bc29eb7f6..3e74929d3289 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -893,6 +893,7 @@ //interrupts = <16 17 18 35 36 37 38 39>; interrupts = <16>; clocks = <&clk_apb>; + clock-names = "PCLK"; }; wdt1: wdt@1e785000 { diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index a0bea4a6ec77..1e6c701da853 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -1000,6 +1000,7 @@ //interrupts = <16 17 18 35 36 37 38 39>; interrupts = <16>; clocks = <&clk_apb>; + clock-names = "PCLK"; }; -- cgit v1.2.3 From ec14ba1ec537d530208c3ba3b3738349d386850f Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 18 May 2017 22:17:04 +0200 Subject: clocksource/drivers/fttmr010: Merge Moxa into FTTMR010 This merges the Moxa Art timer driver into the Faraday FTTMR010 driver and replaces all Kconfig symbols to use the Faraday driver instead. We are now so similar that the drivers can be merged by just adding a few lines to the Faraday timer. Differences: - The Faraday driver explicitly sets the counter to count upwards for the clocksource, removing the need for the clocksource core to invert the value. - The Faraday driver also handles sched_clock() On the Aspeed, the counter can only count downwards, so support the timers in downward-counting mode as well, and flag the Aspeed to use this mode. This mode was tested on the Gemini so I have high hopes that it'll work fine on the Aspeed as well. After this we have one driver for all three SoCs and a generic Faraday FTTMR010 timer driver, which is nice. Cc: Joel Stanley Cc: Jonas Jensen Signed-off-by: Linus Walleij Reviewed-by: Joel Stanley Tested-by: Joel Stanley Signed-off-by: Daniel Lezcano --- arch/arm/mach-aspeed/Kconfig | 2 +- arch/arm/mach-moxart/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig index f3f8c5c658db..2d5570e6e186 100644 --- a/arch/arm/mach-aspeed/Kconfig +++ b/arch/arm/mach-aspeed/Kconfig @@ -4,7 +4,7 @@ menuconfig ARCH_ASPEED select SRAM select WATCHDOG select ASPEED_WATCHDOG - select MOXART_TIMER + select FTTMR010_TIMER select MFD_SYSCON select PINCTRL help diff --git a/arch/arm/mach-moxart/Kconfig b/arch/arm/mach-moxart/Kconfig index 70db2abf6163..a4a91f9a3301 100644 --- a/arch/arm/mach-moxart/Kconfig +++ b/arch/arm/mach-moxart/Kconfig @@ -4,7 +4,7 @@ menuconfig ARCH_MOXART select CPU_FA526 select ARM_DMA_MEM_BUFFERABLE select FARADAY_FTINTC010 - select MOXART_TIMER + select FTTMR010_TIMER select GPIOLIB select PHYLIB if NETDEVICES help -- cgit v1.2.3 From b879d674e03fccb42b0e79f21b2105ad6a824229 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 23 May 2017 21:20:54 +0200 Subject: ARM: dts: r7s72100: Add support for GR-Peach Add device tree source for Renesas GR-Peach board. GR-Peach is an RZ/A1H based board with 10MB of on-chip SRAM and 8MB QSPI flash storage. Add support for the board, and create a 2MB partition to use as rootfs. Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r7s72100-gr-peach.dts | 66 +++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+) create mode 100644 arch/arm/boot/dts/r7s72100-gr-peach.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9c5e1d944d1c..9d64197f3e91 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -701,6 +701,7 @@ dtb-$(CONFIG_ARCH_REALVIEW) += \ dtb-$(CONFIG_ARCH_RENESAS) += \ emev2-kzm9d.dtb \ r7s72100-genmai.dtb \ + r7s72100-gr-peach.dtb \ r7s72100-rskrza1.dtb \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts new file mode 100644 index 000000000000..a1b2aef984f6 --- /dev/null +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts @@ -0,0 +1,66 @@ +/* + * Device Tree Source for the GR-Peach board + * + * Copyright (C) 2017 Jacopo Mondi + * Copyright (C) 2016 Renesas Electronics + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r7s72100.dtsi" + +/ { + model = "GR-Peach"; + compatible = "renesas,gr-peach", "renesas,r7s72100"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/mtdblock0"; + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x00a00000>; + + }; + + lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; + + flash@18000000 { + compatible = "mtd-rom"; + probe-type = "map_rom"; + reg = <0x18000000 0x00800000>; + bank-width = <4>; + device-width = <1>; + + #address-cells = <1>; + #size-cells = <1>; + + rootfs@600000 { + label = "rootfs"; + reg = <0x00600000 0x00200000>; + }; + }; +}; + +&extal_clk { + clock-frequency = <13333000>; +}; + +&usb_x1_clk { + clock-frequency = <48000000>; +}; + +&scif2 { + status = "okay"; +}; -- cgit v1.2.3 From 8cae359049a88b75217b1c93774cfe3c3e610304 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Fri, 19 May 2017 15:07:04 +0200 Subject: ARM: dts: gose: add composite video input Adds VIN, decoder and connector. Signed-off-by: Ulrich Hecht Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7793-gose.dts | 59 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index 30f083528468..76e3aca2029e 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -275,6 +275,16 @@ }; }; + composite-in { + compatible = "composite-video-connector"; + + port { + composite_con_in: endpoint { + remote-endpoint = <&adv7180_in>; + }; + }; + }; + x2_clk: x2-clock { compatible = "fixed-clock"; #clock-cells = <0>; @@ -411,6 +421,11 @@ groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; function = "vin0"; }; + + vin1_pins: vin1 { + groups = "vin1_data8", "vin1_clk"; + function = "vin1"; + }; }; ðer { @@ -542,6 +557,32 @@ reg = <0x12>; }; + composite-in@20 { + compatible = "adi,adv7180cp"; + reg = <0x20>; + remote = <&vin1>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7180_in: endpoint { + remote-endpoint = <&composite_con_in>; + }; + }; + + port@3 { + reg = <3>; + adv7180_out: endpoint { + bus-width = <8>; + remote-endpoint = <&vin1ep>; + }; + }; + }; + }; + hdmi@39 { compatible = "adi,adv7511w"; reg = <0x39>; @@ -670,3 +711,21 @@ }; }; }; + +/* composite video input */ +&vin1 { + pinctrl-0 = <&vin1_pins>; + pinctrl-names = "default"; + + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + vin1ep: endpoint { + remote-endpoint = <&adv7180_out>; + bus-width = <8>; + }; + }; +}; -- cgit v1.2.3 From aabf13bac0046a1add4a3c39881ffb0abe692542 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 6 Jun 2017 16:10:17 +0100 Subject: ARM: dts: iwg20m: Add iWave RZG1M Qseven SOM Add support for iWave RZG1M Qseven System On Module. http://www.iwavesystems.com/rz-g1m-qseven-module.html Signed-off-by: Biju Das Reviewed-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7743-iwg20m.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi new file mode 100644 index 000000000000..001ca9144f4b --- /dev/null +++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi @@ -0,0 +1,29 @@ +/* + * Device Tree Source for the iWave-RZG1M-20M Qseven SOM + * + * Copyright (C) 2017 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include "r8a7743.dtsi" + +/ { + compatible = "iwave,g20m", "renesas,r8a7743"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x20000000>; + }; + + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x20000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; -- cgit v1.2.3 From ad2c0558d0494b420cadd6e887ddab2cd4e27e48 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 6 Jun 2017 16:10:18 +0100 Subject: ARM: dts: iwg20d-q7: Add support for iWave G20D-Q7 board based on RZ/G1M Add support for iWave RainboW-G20D-Qseven board based on RZ/G1M. Signed-off-by: Biju Das Reviewed-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7743-iwg20d-q7.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9d64197f3e91..77d7e2db2513 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -705,6 +705,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r7s72100-rskrza1.dtb \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ + r8a7743-iwg20d-q7.dtb \ r8a7743-sk-rzg1m.dtb \ r8a7745-sk-rzg1e.dtb \ r8a7778-bockw.dtb \ diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts new file mode 100644 index 000000000000..9b54783cc2a5 --- /dev/null +++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts @@ -0,0 +1,25 @@ +/* + * Device Tree Source for the iWave-RZG1M Qseven carrier board + * + * Copyright (C) 2017 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7743-iwg20m.dtsi" + +/ { + model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1M"; + compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"; + + aliases { + serial0 = &scif0; + }; +}; + +&scif0 { + status = "okay"; +}; -- cgit v1.2.3 From f7d569c1e6a6fa731fc34083a9f0191b7360eeb1 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 9 Jun 2017 17:50:40 +0200 Subject: ARM: dts: r8a779x: Fix PCI bus dtc warnings The bogus 'device_type = "pci"' confuses dtc, causing lots of totally unrelated warnings. After fixing that, real warnings like arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_device_reg): Node /pci@ee090000/usb@0,1 PCI unit address format error, expected "1,0" are left. Correct the unit-addresses and reg properties of the subnodes to fix these. Signed-off-by: Rob Herring [geert: Improve description] Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 16 ++++++---------- arch/arm/boot/dts/r8a7791.dtsi | 16 ++++++---------- arch/arm/boot/dts/r8a7794.dtsi | 16 ++++++---------- 3 files changed, 18 insertions(+), 30 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 416956a42c93..2805a8608d4b 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1602,16 +1602,14 @@ 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - usb@0,1 { + usb@1,0 { reg = <0x800 0 0 0 0>; - device_type = "pci"; phys = <&usb0 0>; phy-names = "usb"; }; - usb@0,2 { + usb@2,0 { reg = <0x1000 0 0 0 0>; - device_type = "pci"; phys = <&usb0 0>; phy-names = "usb"; }; @@ -1658,16 +1656,14 @@ 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - usb@0,1 { - reg = <0x800 0 0 0 0>; - device_type = "pci"; + usb@1,0 { + reg = <0x20800 0 0 0 0>; phys = <&usb2 0>; phy-names = "usb"; }; - usb@0,2 { - reg = <0x1000 0 0 0 0>; - device_type = "pci"; + usb@2,0 { + reg = <0x21000 0 0 0 0>; phys = <&usb2 0>; phy-names = "usb"; }; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index b730c889a404..bd93f699ad84 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1613,16 +1613,14 @@ 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - usb@0,1 { + usb@1,0 { reg = <0x800 0 0 0 0>; - device_type = "pci"; phys = <&usb0 0>; phy-names = "usb"; }; - usb@0,2 { + usb@2,0 { reg = <0x1000 0 0 0 0>; - device_type = "pci"; phys = <&usb0 0>; phy-names = "usb"; }; @@ -1648,16 +1646,14 @@ 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - usb@0,1 { - reg = <0x800 0 0 0 0>; - device_type = "pci"; + usb@1,0 { + reg = <0x10800 0 0 0 0>; phys = <&usb2 0>; phy-names = "usb"; }; - usb@0,2 { - reg = <0x1000 0 0 0 0>; - device_type = "pci"; + usb@2,0 { + reg = <0x11000 0 0 0 0>; phys = <&usb2 0>; phy-names = "usb"; }; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index a19b884fb258..7d9a81d970d8 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -820,16 +820,14 @@ 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - usb@0,1 { + usb@1,0 { reg = <0x800 0 0 0 0>; - device_type = "pci"; phys = <&usb0 0>; phy-names = "usb"; }; - usb@0,2 { + usb@2,0 { reg = <0x1000 0 0 0 0>; - device_type = "pci"; phys = <&usb0 0>; phy-names = "usb"; }; @@ -855,16 +853,14 @@ 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - usb@0,1 { - reg = <0x800 0 0 0 0>; - device_type = "pci"; + usb@1,0 { + reg = <0x10800 0 0 0 0>; phys = <&usb2 0>; phy-names = "usb"; }; - usb@0,2 { - reg = <0x1000 0 0 0 0>; - device_type = "pci"; + usb@2,0 { + reg = <0x11000 0 0 0 0>; phys = <&usb2 0>; phy-names = "usb"; }; -- cgit v1.2.3 From c8ceb5ac1ac0aa9bd7c2be9c094f58672bd5669a Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 7 Jun 2017 16:27:25 -0500 Subject: ARM: dts: omap44xx-clocks: Set IVA DPLL and its output clock rates The IVA DPLL is not an essential DPLL for the functionality of a bootloader and is usually not configured (e.g. older u-boots configure it only if CONFIG_SYS_CLOCKS_ENABLE_ALL is enabled and u-boots newer than 2014.01 do not even have an option), and this results in incorrect operating frequencies when trying to use a DSP or IVAHD, whose root clocks are derived from this DPLL. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The reset values of the dividers M4 & M5 (functional clocks for DSP and IVAHD respectively) are identical to each other, but are different at each OPP. The reset values also do not match a specific OPP. So, the derived output clocks from the IVA DPLL have to be initialized as well to avoid initializing these divider outputs to incorrect frequencies. The clock rates are chosen based on the OPP100 values as defined in the OMAP4430 ES2.x Public TRM vAP, section "3.6.3.8.7 DPLL_IVA Preferred Settings". The DPLL locked frequency is 1862.4 MHz (value for DPLL_IVA_X2_CLK), so the dpll_iva_ck clock rate used is half of this value. Signed-off-by: Suman Anna Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap44xx-clocks.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi index 9573b37fbaa7..9cb205b87835 100644 --- a/arch/arm/boot/dts/omap44xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi @@ -357,6 +357,8 @@ compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; + assigned-clocks = <&dpll_iva_ck>; + assigned-clock-rates = <931200000>; }; dpll_iva_x2_ck: dpll_iva_x2_ck { @@ -374,6 +376,8 @@ reg = <0x01b8>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_iva_m4x2_ck>; + assigned-clock-rates = <465600000>; }; dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc { @@ -385,6 +389,8 @@ reg = <0x01bc>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_iva_m5x2_ck>; + assigned-clock-rates = <266100000>; }; dpll_mpu_ck: dpll_mpu_ck@160 { -- cgit v1.2.3 From b58104f0a66c70b4bee271881d4496dfdec194c2 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 7 Jun 2017 16:27:26 -0500 Subject: ARM: dts: omap54xx-clocks: Set IVA DPLL and its output clock rates The IVA DPLL is not an essential DPLL for the functionality of a bootloader and is usually not configured (e.g. older u-boots configure it only if CONFIG_SYS_CLOCKS_ENABLE_ALL is enabled and u-boots newer than 2014.01 do not even have an option), and this results in incorrect operating frequencies when trying to use a DSP or IVAHD, whose root clocks are derived from this DPLL. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The reset values of the dividers H11 & H12 (functional clocks for DSP and IVAHD respectively) are identical to each other, but are different at each OPP. The reset values also do not match a specific OPP. So, the derived output clocks from the IVA DPLL have to be initialized as well to avoid initializing these divider outputs to incorrect frequencies. The clock rates are chosen based on the OPP_NOM values as defined in the OMAP5432 SR2.0 Data Manual Book vK, section 5.2.3.5 "DPLL_IVA Preferred Settings". The recommended maximum DPLL locked frequency is 2330 MHz for OPP_NOM (value for DPLL_IVA_X2_CLK), so the dpll_iva_ck clock rate used is half of this value. The value 465.92 MHz is used instead of 465.9 MHz for dpll_iva_h11x2_ck so that proper divider value can be calculated. Signed-off-by: Suman Anna Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap54xx-clocks.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi index 4899c2359d0a..529193442620 100644 --- a/arch/arm/boot/dts/omap54xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi @@ -315,6 +315,8 @@ compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; + assigned-clocks = <&dpll_iva_ck>; + assigned-clock-rates = <1165000000>; }; dpll_iva_x2_ck: dpll_iva_x2_ck { @@ -330,6 +332,8 @@ ti,max-div = <63>; reg = <0x01b8>; ti,index-starts-at-one; + assigned-clocks = <&dpll_iva_h11x2_ck>; + assigned-clock-rates = <465920000>; }; dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc { @@ -339,6 +343,8 @@ ti,max-div = <63>; reg = <0x01bc>; ti,index-starts-at-one; + assigned-clocks = <&dpll_iva_h12x2_ck>; + assigned-clock-rates = <388300000>; }; mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { -- cgit v1.2.3 From 39879c7d963ef6392235b2cc107c2d6dd25aa55d Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 7 Jun 2017 16:27:27 -0500 Subject: ARM: dts: dra7xx-clocks: Source IPU1 functional clock from CORE DPLL The IPU1 functional clock is actually the output of a mux clock, ipu1_gfclk_mux. The mux clock is sourced by default from the DPLL_ABE_X2_CLK, and this results in a rather odd clock frequency (361 MHz) for the IPU1 functional clock on platforms where ABE_DPLL is configured properly. Reconfigure the mux clock to be sourced from CORE_IPU_ISS_BOOST_CLK (dpll_core_h22x2_ck), so that both the IPU1 and IPU2 are running from the same clock and clocked at the same nominal frequency of 425 MHz. This also ensures that IPU1 functional clock is always configured properly and becomes independent of the state of the ABE DPLL on all boards. Signed-off-by: Suman Anna Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 3330738e4c6e..cfaf27215901 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -791,6 +791,8 @@ clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>; ti,bit-shift = <24>; reg = <0x0520>; + assigned-clocks = <&ipu1_gfclk_mux>; + assigned-clock-parents = <&dpll_core_h22x2_ck>; }; mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 { -- cgit v1.2.3 From 268f6644aa0c2d73bfcebf0e3f0ffc9fc82f82cd Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 7 Jun 2017 16:27:28 -0500 Subject: ARM: dts: dra7xx-clocks: Set DSP DPLL and its output clock rates The DSP DPLL is a new DPLL compared to previous OMAP generations and supplies the root clocks for the DSP processors, as well as a mux input source for EVE sub-system (on applicable SoCs). This DPLL is currently not configured by older bootloaders. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the DSP DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL and be independent of the bootloader version. Newer u-boots (from 2017.01 onwards) reuse and can update these properties to choose an appropriate one-time fixed OPP configuration. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The DSP DPLL provides two output clocks, DSP_GFCLK and EVE_GCLK. The desired rate for DSP_GFCLK is 600 MHz (same as DSP DPLL CLKOUT frequency), and is currently auto set due to the desired M2 divider value being the same as reset value for the locked frequency of 600 MHz. The EVE_GCLK however is required to be 400 MHz, so set the dpll_dsp_m3x2_ck's rate explicitly so that the divider is set properly. The dpll_dsp_m2_ck rate is also set explicitly to not rely on any implicit matching divider reset values to the locked DPLL frequency. The OPP_NOM clock frequencies are defined in the AM572x SR2.0 Data Sheet vB, section 5.5.2 "Voltage And Core Clock Specifications". The clock rates are chosen based on these OPP_NOM values and defined as per a DRA7xx PLL spec document. The DPLL locked frequency is 1200 MHz, so the dpll_dsp_ck clock rate used is half of this value. Signed-off-by: Suman Anna Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index cfaf27215901..8a82490035d9 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -338,6 +338,8 @@ compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; + assigned-clocks = <&dpll_dsp_ck>; + assigned-clock-rates = <600000000>; }; dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 { @@ -349,6 +351,8 @@ reg = <0x0244>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_dsp_m2_ck>; + assigned-clock-rates = <600000000>; }; iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { @@ -659,6 +663,8 @@ reg = <0x0248>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_dsp_m3x2_ck>; + assigned-clock-rates = <400000000>; }; dpll_gmac_x2_ck: dpll_gmac_x2_ck { -- cgit v1.2.3 From 32a04832a120b8ddc6b8752d30ba4be00fa23b74 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 7 Jun 2017 16:27:29 -0500 Subject: ARM: dts: dra7xx-clocks: Set IVA DPLL and its output clock rates The IVA DPLL in DRA7xx provides the output clocks for only the IVAHD subsystem in DRA7xx as compared to previous OMAP generations when it provided the clocks for both DSP and IVAHD subsystems. This DPLL is currently not configured by older bootloaders. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL and be independent of the bootloader version. Newer u-boots (from 2017.01 onwards) reuse and can update these properties to choose an appropriate one-time fixed OPP configuration. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The reset value of the divider M2 (that supplies the IVA_GFLCK, the functional clock for the IVAHD subsystem) does not match a specific OPP. So, the derived output clock from this IVA DPLL has to be initialized as well to avoid initializing these divider outputs to an incorrect frequencies. The OPP_NOM clock frequencies are defined in the AM572x SR2.0 Data Sheet vB, section 5.5.2 "Voltage And Core Clock Specifications". The clock rates are chosen based on these OPP_NOM values and defined as per a DRA7xx PLL spec document. The DPLL locked frequency is 2300 MHz, so the dpll_iva_ck clock rate used is half of this value. The value for the divider clock, dpll_iva_m2_ck, has to be set to 388.333334 MHz or more for the divider clk logic to compute the appropriate divider value for OPP_NOM. Signed-off-by: Suman Anna Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 8a82490035d9..76e2b7478141 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -376,6 +376,8 @@ compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; + assigned-clocks = <&dpll_iva_ck>; + assigned-clock-rates = <1165000000>; }; dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 { @@ -387,6 +389,8 @@ reg = <0x01b0>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_iva_m2_ck>; + assigned-clock-rates = <388333334>; }; iva_dclk: iva_dclk { -- cgit v1.2.3 From fcd104b50fd0a8b638ab01b2e17252d16868aa49 Mon Sep 17 00:00:00 2001 From: Subhajit Paul Date: Wed, 7 Jun 2017 16:27:30 -0500 Subject: ARM: dts: dra7xx-clocks: Use DPLL_GPU for GPU clocks The GPU has two functional clocks - GPU_CORE_GCLK and GPU_HYD_GCLK. Both of these are mux clocks and are derived from the DPLL_CORE H14 output clock CORE_GPU_CLK by default. These clocks can also be be derived from DPLL_PER or DPLL_GPU. The GPU DPLL provides the output clocks primarily for the GPU. Configuring the GPU for different OPP clock frequencies is easier to achieve when using the DPLL_GPU rather than the other two DPLLs due to: 1. minimal affect on any other output clocks from these DPLLs 2. may require an impossible post-divider values on existing DPLLs without affecting other clocks. So, switch the GPU functional clocks to be sourced from GPU DPLL by default. This is done using the DT standard properties "assigned-clocks" and "assigned-clock-parents". Newer u-boots (from 2017.01 onwards) reuse and can update these properties to choose an appropriate one-time fixed OPP configuration as all the required ABB/AVS setup is performed within the bootloader. Note that there is no DVFS supported for any of the non-MPU domains. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. This patch also sets the initial values for the DPLL_GPU outputs. These values are chosen based on the OPP_NOM values defined as per recommendation from design team. The DPLL locked frequency is kept at 1277 MHz, so that the value for the divider clock, dpll_gpu_m2_ck, can be set to 425.67 MHz for OPP_NOM. Signed-off-by: Subhajit Paul [s-anna@ti.com: revise patch description] Signed-off-by: Suman Anna Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 76e2b7478141..cf229dfabf61 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -414,6 +414,8 @@ compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>; reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; + assigned-clocks = <&dpll_gpu_ck>; + assigned-clock-rates = <1277000000>; }; dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 { @@ -425,6 +427,8 @@ reg = <0x02e8>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_gpu_m2_ck>; + assigned-clock-rates = <425666667>; }; dpll_core_m2_ck: dpll_core_m2_ck@130 { @@ -1760,6 +1764,8 @@ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; ti,bit-shift = <24>; reg = <0x1220>; + assigned-clocks = <&gpu_core_gclk_mux>; + assigned-clock-parents = <&dpll_gpu_m2_ck>; }; gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 { @@ -1768,6 +1774,8 @@ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; ti,bit-shift = <26>; reg = <0x1220>; + assigned-clocks = <&gpu_hyd_gclk_mux>; + assigned-clock-parents = <&dpll_gpu_m2_ck>; }; l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 { -- cgit v1.2.3 From c3d28e537999bc7c7d39ca09d11252137e1fee02 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 1 Jun 2017 07:26:37 -0700 Subject: ARM: dts: omap4-droid4: Configure CPCAP battery driver Configure CPCAP battery driver. Cc: devicetree@vger.kernel.org Cc: Marcel Partap Cc: Michael Scott Reviewed-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi index f5aeb3959afd..1eb5da1dc8f0 100644 --- a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi +++ b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi @@ -26,6 +26,22 @@ #io-channel-cells = <1>; }; + cpcap_battery: battery { + compatible = "motorola,cpcap-battery"; + interrupts-extended = < + &cpcap 6 0 &cpcap 5 0 &cpcap 3 0 + &cpcap 20 0 &cpcap 54 0 + >; + interrupt-names = + "eol", "lowbph", "lowbpl", + "chrgcurr1", "battdetb"; + io-channels = <&cpcap_adc 0 &cpcap_adc 1 + &cpcap_adc 5 &cpcap_adc 6>; + io-channel-names = "battdetb", "battp", + "chg_isense", "batti"; + power-supplies = <&cpcap_charger>; + }; + cpcap_charger: charger { compatible = "motorola,mapphone-cpcap-charger"; interrupts-extended = < -- cgit v1.2.3 From 36c2cb1830e0799f7f35c1429404c842daa8996d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 14 Apr 2017 23:42:28 +0200 Subject: ARM: dts: BCM5301X: Add CPU thermal sensor and zone MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This uses CPU thermal sensor available on every Northstar chipset to monitor temperature. We don't have any cooling or throttling so only a critical trip was added. Signed-off-by: Rafał Miłecki Acked-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index acee36a61004..ffcbe49c8f39 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -349,6 +349,12 @@ "sata2"; }; + thermal: thermal@1800c2c0 { + compatible = "brcm,ns-thermal"; + reg = <0x1800c2c0 0x10>; + #thermal-sensor-cells = <0>; + }; + srab: srab@18007000 { compatible = "brcm,bcm5301x-srab"; reg = <0x18007000 0x1000>; @@ -412,4 +418,24 @@ status = "disabled"; }; }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + coefficients = <(-556) 418000>; + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; }; -- cgit v1.2.3 From 23f1eca6d59b5a341f63d9e96bb80734d29436c8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Wed, 19 Apr 2017 23:54:25 +0200 Subject: ARM: dts: BCM5301X: Specify MDIO bus in the DT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Northstar devices have MDIO bus that may contain various PHYs attached. A common example is USB 3.0 PHY (that doesn't have an MDIO driver yet). Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index ffcbe49c8f39..98647d22b291 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -320,6 +320,14 @@ }; }; + mdio: mdio@18003000 { + compatible = "brcm,iproc-mdio"; + reg = <0x18003000 0x8>; + #size-cells = <1>; + #address-cells = <0>; + status = "disabled"; + }; + i2c0: i2c@18009000 { compatible = "brcm,iproc-i2c"; reg = <0x18009000 0x50>; -- cgit v1.2.3 From f1494a85e205f6b74ae04d49c446e792b0460301 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 18 Apr 2017 16:32:34 -0700 Subject: ARM: dts: Cygnus: Add BCM11360's V3D device This loads the VC4 driver on the 911360_entphn platform (with the corresponding series sent to dri-devel), which is supported by master of the Mesa tree. Signed-off-by: Eric Anholt Acked-by: Scott Branden Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 13 +++++++++++++ arch/arm/boot/dts/bcm911360_entphn.dts | 8 ++++++++ 2 files changed, 21 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 9644fddb5e3c..5adbf74d2d70 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -386,6 +386,19 @@ status = "disabled"; }; + v3d: v3d@180a2000 { + compatible = "brcm,cygnus-v3d"; + reg = <0x180a2000 0x1000>; + clocks = <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>; + clock-names = "v3d_clk"; + interrupts = ; + status = "disabled"; + }; + + vc4: gpu { + compatible = "brcm,cygnus-vc4"; + }; + adc: adc@180a6000 { compatible = "brcm,iproc-static-adc"; #io-channel-cells = <1>; diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts index 8b3800f46288..037621c13290 100644 --- a/arch/arm/boot/dts/bcm911360_entphn.dts +++ b/arch/arm/boot/dts/bcm911360_entphn.dts @@ -57,6 +57,14 @@ }; }; +&v3d { + assigned-clocks = + <&mipipll BCM_CYGNUS_MIPIPLL>, + <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>; + assigned-clock-rates = <525000000>, <300000000>; + status = "okay"; +}; + &uart3 { status = "okay"; }; -- cgit v1.2.3 From 2896cb55dc6dd11bd9d07ab1f1eca8a6d478c68a Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Fri, 28 Apr 2017 16:11:31 -0400 Subject: ARM: dts: NSP: Add Thermal Support Add thermal support via the ns-thermal driver and create a single thermal zone for the entire SoC. Signed-off-by: Jon Mason Acked-by: Eduardo Valentin Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index fe6cba994a97..7204d1def23d 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -413,6 +413,12 @@ <0x3f408 0x04>; }; + thermal: thermal@3f2c0 { + compatible = "brcm,ns-thermal"; + reg = <0x3f2c0 0x10>; + #thermal-sensor-cells = <0>; + }; + sata_phy: sata_phy@40100 { compatible = "brcm,iproc-nsp-sata-phy"; reg = <0x40100 0x340>; @@ -563,4 +569,24 @@ brcm,pcie-msi-inten; }; }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + coefficients = <(-556) 418000>; + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; }; -- cgit v1.2.3 From 40c26d3af60af5c5d1c434465ffd38a42e5d9bb1 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 28 Apr 2017 15:22:04 -0700 Subject: ARM: dts: Cygnus: Add the ethernet switch and ethernet PHY Cygnus has a single amac controller connected to the B53 switch with 2 PHYs. On the BCM911360_EP platform, those two PHYs are connected to the external ethernet jacks. Signed-off-by: Eric Anholt Reviewed-by: Florian Fainelli Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 58 ++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm911360_entphn.dts | 12 +++++++ 2 files changed, 70 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 5adbf74d2d70..bf8c83815753 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -142,6 +142,55 @@ interrupts = <0>; }; + mdio: mdio@18002000 { + compatible = "brcm,iproc-mdio"; + reg = <0x18002000 0x8>; + #size-cells = <1>; + #address-cells = <0>; + status = "disabled"; + + gphy0: ethernet-phy@0 { + reg = <0>; + }; + + gphy1: ethernet-phy@1 { + reg = <1>; + }; + }; + + switch: switch@18007000 { + compatible = "brcm,bcm11360-srab", "brcm,cygnus-srab"; + reg = <0x18007000 0x1000>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + phy-handle = <&gphy0>; + phy-mode = "rgmii"; + }; + + port@1 { + reg = <1>; + phy-handle = <&gphy1>; + phy-mode = "rgmii"; + }; + + port@8 { + reg = <8>; + label = "cpu"; + ethernet = <ð0>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + i2c0: i2c@18008000 { compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; reg = <0x18008000 0x100>; @@ -295,6 +344,15 @@ status = "disabled"; }; + eth0: ethernet@18042000 { + compatible = "brcm,amac"; + reg = <0x18042000 0x1000>, + <0x18110000 0x1000>; + reg-names = "amac_base", "idm_base"; + interrupts = ; + status = "disabled"; + }; + nand: nand@18046000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x18046000 0x600>, <0xf8105408 0x600>, diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts index 037621c13290..000f5f19215e 100644 --- a/arch/arm/boot/dts/bcm911360_entphn.dts +++ b/arch/arm/boot/dts/bcm911360_entphn.dts @@ -57,6 +57,18 @@ }; }; +ð0 { + status = "okay"; +}; + +&mdio { + status = "okay"; +}; + +&switch { + status = "okay"; +}; + &v3d { assigned-clocks = <&mipipll BCM_CYGNUS_MIPIPLL>, -- cgit v1.2.3 From 1aa1d858f582c7b1c245e8990ab21e1d9d8d00b1 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 21 May 2017 18:44:36 +0200 Subject: ARM: dts: bcm283x: Add dtsi for OTG mode The Raspberry Pi Zero also supports OTG mode. So provide a dtsi file to configure the USB interface accordingly. The fifo sizes are optimized for device endpoint 6 and 7 with the maximum of 768. Signed-off-by: Stefan Wahren Signed-off-by: Eric Anholt --- arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi b/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi new file mode 100644 index 000000000000..e7d217c967a1 --- /dev/null +++ b/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi @@ -0,0 +1,10 @@ +&usb { + dr_mode = "otg"; + g-rx-fifo-size = <256>; + g-np-tx-fifo-size = <32>; + /* + * According to dwc2 the sum of all device EP + * fifo sizes shouldn't exceed 3776 bytes. + */ + g-tx-fifo-size = <256 256 512 512 512 768 768>; +}; -- cgit v1.2.3 From 860a5d0b262eb3a98f578ffbd4469723315fd778 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 21 May 2017 18:44:37 +0200 Subject: ARM: dts: bcm283x: Add generic USB PHY In order to use dwc2 in OTG or gadget mode the USB PHY should be specified. Since there is no bcm283x USB PHY driver use the generic one. Signed-off-by: Stefan Wahren Acked-by: Stephen Warren Signed-off-by: Eric Anholt --- arch/arm/boot/dts/bcm283x.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index 86a5db53da8f..9a05cde8aced 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -589,6 +589,8 @@ #size-cells = <0>; clocks = <&clk_usb>; clock-names = "otg"; + phys = <&usbphy>; + phy-names = "usb2-phy"; }; v3d: v3d@7ec00000 { @@ -624,4 +626,8 @@ clock-frequency = <480000000>; }; }; + + usbphy: phy { + compatible = "usb-nop-xceiv"; + }; }; -- cgit v1.2.3 From 9c53535a15b63218204f2bab2c279b3e64c61c0e Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 21 May 2017 18:44:38 +0200 Subject: ARM: dts: bcm2835-rpi-zero: Enable OTG mode Since 635c21068cf ("usb: dwc2: gadget: Fix WARN_ON messages during FIFO init") the dwc2 driver is able to handle OTG and gadget mode for bcm2835. So enable this feature for the Raspberry Pi Zero. Signed-off-by: Stefan Wahren Signed-off-by: Eric Anholt --- arch/arm/boot/dts/bcm2835-rpi-zero.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts index cc8b832c4c78..79a20d520931 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts @@ -12,7 +12,7 @@ /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" +#include "bcm283x-rpi-usb-otg.dtsi" / { compatible = "raspberrypi,model-zero", "brcm,bcm2835"; -- cgit v1.2.3 From 3e9aaaf1d814586404dc93461ec955dd90dc8934 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 21 May 2017 18:44:39 +0200 Subject: ARM: bcm2835_defconfig: Enable serial & ethernet USB gadget support In order to use the serial and ethernet USB gadget support on Raspberry Zero, we also need to enable the PHY driver, kernel module and OTG support. Signed-off-by: Stefan Wahren Signed-off-by: Eric Anholt --- arch/arm/configs/bcm2835_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig index 3ba8cd3211f8..3ee9d78c412a 100644 --- a/arch/arm/configs/bcm2835_defconfig +++ b/arch/arm/configs/bcm2835_defconfig @@ -24,6 +24,8 @@ CONFIG_PROFILING=y CONFIG_OPROFILE=y CONFIG_JUMP_LABEL=y CONFIG_CC_STACKPROTECTOR_REGULAR=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y CONFIG_ARCH_MULTI_V6=y CONFIG_ARCH_BCM=y CONFIG_ARCH_BCM2835=y @@ -86,8 +88,14 @@ CONFIG_SND=y CONFIG_SND_SOC=y CONFIG_SND_BCM2835_SOC_I2S=y CONFIG_USB=y +CONFIG_USB_OTG=y CONFIG_USB_STORAGE=y CONFIG_USB_DWC2=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_GADGET=y +CONFIG_USB_ETH=m +CONFIG_USB_ETH_EEM=y +CONFIG_USB_G_SERIAL=m CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y -- cgit v1.2.3 From e585513b76f7b05d08ca3fb250fed11f6ba46ee5 Mon Sep 17 00:00:00 2001 From: "Kirill A. Shutemov" Date: Tue, 6 Jun 2017 14:31:20 +0300 Subject: x86/mm/gup: Switch GUP to the generic get_user_page_fast() implementation This patch provides all required callbacks required by the generic get_user_pages_fast() code and switches x86 over - and removes the platform specific implementation. Signed-off-by: Kirill A. Shutemov Cc: Andrew Morton Cc: Andy Lutomirski Cc: Andy Lutomirski Cc: Borislav Petkov Cc: Brian Gerst Cc: Dave Hansen Cc: Denys Vlasenko Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: linux-arch@vger.kernel.org Cc: linux-mm@kvack.org Link: http://lkml.kernel.org/r/20170606113133.22974-2-kirill.shutemov@linux.intel.com Signed-off-by: Ingo Molnar --- arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4c1a35f15838..c3c49c9491d5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1637,7 +1637,7 @@ config ARCH_SELECT_MEMORY_MODEL config HAVE_ARCH_PFN_VALID def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM -config HAVE_GENERIC_RCU_GUP +config HAVE_GENERIC_GUP def_bool y depends on ARM_LPAE -- cgit v1.2.3 From be36e000bc2d28512721c6e09c3df920b1bfad5e Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Jun 2017 12:18:02 +0200 Subject: ARM: at91: fix at91_suspend_entering_slow_clock link error When CONFIG_ARCH_AT91 is enabled, but none of the specific SoC support is in use, some at91 specific drivers fail to link: drivers/tty/serial/atmel_serial.o: In function `atmel_serial_suspend': atmel_serial.c:(.text.atmel_serial_suspend+0x1e): undefined reference to `at91_suspend_entering_slow_clock' drivers/usb/host/ohci-at91.o: In function `ohci_hcd_at91_drv_suspend': ohci-at91.c:(.text.ohci_hcd_at91_drv_suspend+0x12): undefined reference to `at91_suspend_entering_slow_clock' drivers/usb/gadget/udc/at91_udc.o: In function `at91udc_suspend': at91_udc.c:(.text.at91udc_suspend+0x26): undefined reference to `at91_suspend_entering_slow_clock' This changes the at91_suspend_entering_slow_clock hack once more, adding an alternative inline implementation that is used exactly in those cases that don't provide the normal implementation. Fixes: c1892c2379d2 ("ARM: at91: handle CONFIG_PM for armv7m configurations") Signed-off-by: Arnd Bergmann Signed-off-by: Alexandre Belloni --- arch/arm/mach-at91/samv7.c | 9 --------- 1 file changed, 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/samv7.c b/arch/arm/mach-at91/samv7.c index 910f0c68db62..11386f190c83 100644 --- a/arch/arm/mach-at91/samv7.c +++ b/arch/arm/mach-at91/samv7.c @@ -15,15 +15,6 @@ #include #include "generic.h" -#ifdef CONFIG_PM -/* This function has to be defined for various drivers that are using it */ -int at91_suspend_entering_slow_clock(void) -{ - return 0; -} -EXPORT_SYMBOL(at91_suspend_entering_slow_clock); -#endif - static const char *const samv7_dt_board_compat[] __initconst = { "atmel,samv7", NULL -- cgit v1.2.3 From b5db9dedc5584bf473566b9cf5c941d3ab6258db Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 13 Apr 2017 12:55:58 -0600 Subject: ARM: tegra: remove Whistler support Whistler is an ancient Tegra 2 reference board. I may have been the only person who ever used it with upstream software, and I've just recycled the board hardware. Hence, it makes sense to remove support from software. Signed-off-by: Stephen Warren Acked-by: Mark Brown Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/tegra20-whistler.dts | 636 --------------------------------- 2 files changed, 1 insertion(+), 638 deletions(-) delete mode 100644 arch/arm/boot/dts/tegra20-whistler.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9c5e1d944d1c..04d3b46d3646 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -920,8 +920,7 @@ dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ tegra20-seaboard.dtb \ tegra20-tec.dtb \ tegra20-trimslice.dtb \ - tegra20-ventana.dtb \ - tegra20-whistler.dtb + tegra20-ventana.dtb dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-apalis-eval.dtb \ tegra30-beaver.dtb \ diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts deleted file mode 100644 index 1e06f854c8b4..000000000000 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ /dev/null @@ -1,636 +0,0 @@ -/dts-v1/; - -#include -#include "tegra20.dtsi" - -/ { - model = "NVIDIA Tegra20 Whistler evaluation board"; - compatible = "nvidia,whistler", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000d000/max8907@3c"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x00000000 0x20000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata", "atb", "ate", "gma", "gmb", - "gmc", "gmd", "gpu"; - nvidia,function = "gmi"; - }; - atc { - nvidia,pins = "atc", "atd"; - nvidia,function = "sdio4"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "osc"; - }; - crtp { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd"; - nvidia,function = "vi"; - }; - dte { - nvidia,pins = "dte"; - nvidia,function = "rsvd1"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gme { - nvidia,pins = "gme"; - nvidia,function = "dap5"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint", "pta"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uartb"; - }; - kbca { - nvidia,pins = "kbca", "kbcc", "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - kbcb { - nvidia,pins = "kbcb", "kbcd"; - nvidia,function = "sdio2"; - }; - lcsn { - nvidia,pins = "lcsn", "lsck", "lsda", "lsdi", - "spia", "spib", "spic"; - nvidia,function = "spi3"; - }; - ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldc", "ldi", - "lhp0", "lhp1", "lhp2", "lhs", "lm0", - "lm1", "lpp", "lpw0", "lpw1", "lpw2", - "lsc0", "lsc1", "lspi", "lvp0", "lvp1", - "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc", "uac"; - nvidia,function = "owr"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd", "slxa", - "slxc", "slxd", "slxk"; - nvidia,function = "sdio3"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - spdi { - nvidia,pins = "spdi", "spdo"; - nvidia,function = "rsvd2"; - }; - spid { - nvidia,pins = "spid", "spie", "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - spif { - nvidia,pins = "spif"; - nvidia,function = "spi2"; - }; - uaa { - nvidia,pins = "uaa", "uab"; - nvidia,function = "uarta"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - uda { - nvidia,pins = "uda"; - nvidia,function = "spi1"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "ddc", "gma", - "gmb", "gmc", "gmd", "irrx", "irtx", - "kbca", "kbcb", "kbcc", "kbcd", "kbce", - "kbcf", "sdc", "sdd", "spie", "spig", - "spih", "uaa", "uab", "uad", "uca", - "ucb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_atd { - nvidia,pins = "atd", "ate", "cdev1", "csus", - "dap1", "dap2", "dap3", "dap4", "dte", - "dtf", "gpu", "gpu7", "gpv", "i2cp", - "rm", "sdio1", "slxa", "slxc", "slxd", - "slxk", "spdi", "spdo", "uac", "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_cdev2 { - nvidia,pins = "cdev2", "spia", "spib"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "lc", "pmca", - "pmcb", "pmcc", "pmcd", "xm2c", - "xm2d"; - nvidia,pull = ; - }; - conf_crtp { - nvidia,pins = "crtp"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", - "spid", "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_gme { - nvidia,pins = "gme", "owc", "pta", "spic"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - conf_ls { - nvidia,pins = "ls", "pmce"; - nvidia,pull = ; - }; - drive_dap1 { - nvidia,pins = "drive_dap1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,low-power-mode = ; - nvidia,pull-down-strength = <0>; - nvidia,pull-up-strength = <0>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - }; - - i2s@70002800 { - status = "okay"; - }; - - serial@70006000 { - status = "okay"; - }; - - hdmi_ddc: i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - codec: codec@1a { - compatible = "wlf,wm8753"; - reg = <0x1a>; - }; - - tca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - max8907@3c { - compatible = "maxim,max8907"; - reg = <0x3c>; - interrupts = ; - - maxim,system-power-controller; - - mbatt-supply = <&usb0_vbus_reg>; - in-v1-supply = <&mbatt_reg>; - in-v2-supply = <&mbatt_reg>; - in-v3-supply = <&mbatt_reg>; - in1-supply = <&mbatt_reg>; - in2-supply = <&nvvdd_sv3_reg>; - in3-supply = <&mbatt_reg>; - in4-supply = <&mbatt_reg>; - in5-supply = <&mbatt_reg>; - in6-supply = <&mbatt_reg>; - in7-supply = <&mbatt_reg>; - in8-supply = <&mbatt_reg>; - in9-supply = <&mbatt_reg>; - in10-supply = <&mbatt_reg>; - in11-supply = <&mbatt_reg>; - in12-supply = <&mbatt_reg>; - in13-supply = <&mbatt_reg>; - in14-supply = <&mbatt_reg>; - in15-supply = <&mbatt_reg>; - in16-supply = <&mbatt_reg>; - in17-supply = <&nvvdd_sv3_reg>; - in18-supply = <&nvvdd_sv3_reg>; - in19-supply = <&mbatt_reg>; - in20-supply = <&mbatt_reg>; - - regulators { - mbatt_reg: mbatt { - regulator-name = "vbat_pmu"; - regulator-always-on; - }; - - sd1 { - regulator-name = "nvvdd_sv1,vdd_cpu_pmu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - sd2 { - regulator-name = "nvvdd_sv2,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - nvvdd_sv3_reg: sd3 { - regulator-name = "nvvdd_sv3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo1 { - regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo2 { - regulator-name = "nvvdd_ldo2,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo3 { - regulator-name = "nvvdd_ldo3,vcom_1v8b"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "nvvdd_ldo4,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo5 { - regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - hdmi_pll_reg: ldo6 { - regulator-name = "nvvdd_ldo6,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo7 { - regulator-name = "nvvdd_ldo7,avddio_audio"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo8 { - regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo9 { - regulator-name = "nvvdd_ldo9,avdd_cam*"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo10 { - regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - hdmi_vdd_reg: ldo11 { - regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo12 { - regulator-name = "nvvdd_ldo12,vddio_sdio"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo13 { - regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo14 { - regulator-name = "nvvdd_ldo14,avdd_vdac"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo15 { - regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo16 { - regulator-name = "nvvdd_ldo16,vdd_dbrtr"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - ldo17 { - regulator-name = "nvvdd_ldo17,vddio_mipi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo18 { - regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19 { - regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo20 { - regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - out5v { - regulator-name = "usb0_vbus_reg"; - }; - - out33v { - regulator-name = "pmu_out3v3"; - }; - - bbat { - regulator-name = "pmu_bbat"; - regulator-min-microvolt = <2400000>; - regulator-max-microvolt = <2400000>; - regulator-always-on; - }; - - sdby { - regulator-name = "vdd_aon"; - regulator-always-on; - }; - - vrtc { - regulator-name = "vrtc,pmu_vccadc"; - regulator-always-on; - }; - }; - }; - }; - - kbc@7000e200 { - status = "okay"; - nvidia,debounce-delay-ms = <20>; - nvidia,repeat-delay-ms = <160>; - nvidia,kbc-row-pins = <0 1 2>; - nvidia,kbc-col-pins = <16 17>; - wakeup-source; - linux,keymap = ; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <1000>; - nvidia,core-pwr-good-time = <0 3845>; - nvidia,core-pwr-off-time = <93727>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - nvidia,combined-power-req; - }; - - usb@c5000000 { - status = "okay"; - }; - - usb-phy@c5000000 { - status = "okay"; - vbus-supply = <&vbus1_reg>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - vbus-supply = <&vbus3_reg>; - }; - - sdhci@c8000400 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; - bus-width = <8>; - }; - - sdhci@c8000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb0_vbus_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vbus1_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vbus1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&tca6416 0 0>; /* GPIO_PMU0 */ - regulator-always-on; - regulator-boot-on; - }; - - vbus3_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vbus3"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&tca6416 1 0>; /* GPIO_PMU1 */ - regulator-always-on; - regulator-boot-on; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8753-whistler", - "nvidia,tegra-audio-wm8753"; - nvidia,model = "NVIDIA Tegra Whistler"; - - nvidia,audio-routing = - "Headphone Jack", "LOUT1", - "Headphone Jack", "ROUT1", - "MIC2", "Mic Jack", - "MIC2N", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&codec>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; -- cgit v1.2.3 From 508d690e94218d306ab2092d6ee95ca75f9fa98b Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 21 Mar 2017 21:03:06 -0500 Subject: ARM: dts: tegra: fix PCI bus dtc warnings dtc recently added PCI bus checks. Fix these warnings. Signed-off-by: Rob Herring Cc: Stephen Warren Cc: Thierry Reding Cc: Alexandre Courbot Cc: linux-tegra@vger.kernel.org Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra124-apalis.dtsi | 2 +- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2 +- arch/arm/boot/dts/tegra124.dtsi | 4 +++- arch/arm/boot/dts/tegra20-harmony.dts | 2 +- arch/arm/boot/dts/tegra20-tamonten.dtsi | 2 +- arch/arm/boot/dts/tegra20-tec.dts | 2 +- arch/arm/boot/dts/tegra20-trimslice.dts | 2 +- arch/arm/boot/dts/tegra20.dtsi | 4 +++- arch/arm/boot/dts/tegra30-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra30-apalis.dtsi | 2 +- arch/arm/boot/dts/tegra30-beaver.dts | 2 +- arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 +- arch/arm/boot/dts/tegra30.dtsi | 5 ++++- 14 files changed, 21 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index 5b860ad5cbee..ecffcd115fa7 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -63,7 +63,7 @@ stdout-path = "serial0:115200n8"; }; - pcie-controller@01003000 { + pcie@1003000 { pci@1,0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index f9e623bdd5c3..5d9b18ef5af6 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -54,7 +54,7 @@ reg = <0x0 0x80000000 0x0 0x80000000>; }; - pcie-controller@01003000 { + pcie@1003000 { status = "okay"; avddio-pex-supply = <&vdd_1v05>; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 53994f9fbbcc..7bacb2954f58 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -27,7 +27,7 @@ reg = <0x0 0x80000000 0x0 0x80000000>; }; - pcie-controller@01003000 { + pcie@1003000 { status = "okay"; avddio-pex-supply = <&vdd_1v05_run>; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 187a36c6d0fc..1b10b14a6abd 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -14,7 +14,7 @@ #address-cells = <2>; #size-cells = <2>; - pcie-controller@01003000 { + pcie@1003000 { compatible = "nvidia,tegra124-pcie"; device_type = "pci"; reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ @@ -54,6 +54,7 @@ device_type = "pci"; assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; reg = <0x000800 0 0 0 0>; + bus-range = <0x00 0xff>; status = "disabled"; #address-cells = <3>; @@ -67,6 +68,7 @@ device_type = "pci"; assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; reg = <0x001000 0 0 0 0>; + bus-range = <0x00 0xff>; status = "disabled"; #address-cells = <3>; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index d4fb4d39ede7..41749693ec3c 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -566,7 +566,7 @@ nvidia,sys-clock-req-active-high; }; - pcie-controller@80003000 { + pcie@80003000 { status = "okay"; avdd-pex-supply = <&pci_vdd_reg>; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 27d2bbbf1eae..7361f4a82e80 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -478,7 +478,7 @@ nvidia,sys-clock-req-active-high; }; - pcie-controller@80003000 { + pcie@80003000 { avdd-pex-supply = <&pci_vdd_reg>; vdd-pex-supply = <&pci_vdd_reg>; avdd-pex-pll-supply = <&pci_vdd_reg>; diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts index c12d8bead2ee..9cb534f4441e 100644 --- a/arch/arm/boot/dts/tegra20-tec.dts +++ b/arch/arm/boot/dts/tegra20-tec.dts @@ -32,7 +32,7 @@ }; }; - pcie-controller@80003000 { + pcie@80003000 { status = "okay"; pci@1,0 { diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 87b07fbadbbe..b902ab594afa 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -321,7 +321,7 @@ nvidia,sys-clock-req-active-high; }; - pcie-controller@80003000 { + pcie@80003000 { status = "okay"; avdd-pex-supply = <&pci_vdd_reg>; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index e8807503f87c..7c85f97f72ea 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -586,7 +586,7 @@ reset-names = "fuse"; }; - pcie-controller@80003000 { + pcie@80003000 { compatible = "nvidia,tegra20-pcie"; device_type = "pci"; reg = <0x80003000 0x00000800 /* PADS registers */ @@ -625,6 +625,7 @@ device_type = "pci"; assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; reg = <0x000800 0 0 0 0>; + bus-range = <0x00 0xff>; status = "disabled"; #address-cells = <3>; @@ -638,6 +639,7 @@ device_type = "pci"; assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; reg = <0x001000 0 0 0 0>; + bus-range = <0x00 0xff>; status = "disabled"; #address-cells = <3>; diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 99a69457dbf5..fc530e4a96c4 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -21,7 +21,7 @@ stdout-path = "serial0:115200n8"; }; - pcie-controller@00003000 { + pcie@3000 { status = "okay"; pci@1,0 { diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index f6c7c3e958ac..7a6a1a014603 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -9,7 +9,7 @@ model = "Toradex Apalis T30"; compatible = "toradex,apalis_t30", "nvidia,tegra30"; - pcie-controller@00003000 { + pcie@3000 { avdd-pexa-supply = <&vdd2_reg>; vdd-pexa-supply = <&vdd2_reg>; avdd-pexb-supply = <&vdd2_reg>; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 0350002849d5..4f41b18d9547 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -20,7 +20,7 @@ reg = <0x80000000 0x7ff00000>; }; - pcie-controller@00003000 { + pcie@3000 { status = "okay"; avdd-pexa-supply = <&ldo1_reg>; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index f11012bb58cc..83dc14a9b353 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -43,7 +43,7 @@ reg = <0x80000000 0x40000000>; }; - pcie-controller@00003000 { + pcie@3000 { status = "okay"; /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */ diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index bbb1c002e7f1..13960fda7471 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -10,7 +10,7 @@ compatible = "nvidia,tegra30"; interrupt-parent = <&lic>; - pcie-controller@00003000 { + pcie@3000 { compatible = "nvidia,tegra30-pcie"; device_type = "pci"; reg = <0x00003000 0x00000800 /* PADS registers */ @@ -51,6 +51,7 @@ device_type = "pci"; assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; reg = <0x000800 0 0 0 0>; + bus-range = <0x00 0xff>; status = "disabled"; #address-cells = <3>; @@ -64,6 +65,7 @@ device_type = "pci"; assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; reg = <0x001000 0 0 0 0>; + bus-range = <0x00 0xff>; status = "disabled"; #address-cells = <3>; @@ -77,6 +79,7 @@ device_type = "pci"; assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; reg = <0x001800 0 0 0 0>; + bus-range = <0x00 0xff>; status = "disabled"; #address-cells = <3>; -- cgit v1.2.3 From cff94887d55a32bf8f7095482d9ba92784280a5c Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 15 May 2017 09:50:34 +0200 Subject: ARM: dts: add core I2C devices to the APQ8060 Dragonboard The APQ8060 Dragonboard has an Atmel AT24c128 EEPROM and a Wolfson Micro WM8903 codec connected to its GSBI8 I2C bus. Add entries for these to the device tree. The interrupt line from the WM8903 chip is not routed anywhere on this design so it can not be used. Signed-off-by: Linus Walleij Acked-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8060-dragonboard.dts | 49 ++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index 5225e489ef52..9d725f983282 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -180,6 +180,19 @@ }; }; + dragon_gsbi8_i2c_pins: gsbi8_i2c { + mux { + pins = "gpio64", "gpio65"; + function = "gsbi8"; + }; + pinconf { + pins = "gpio64", "gpio65"; + drive-strength = <16>; + /* These have external pull-up 2.2kOhm to 1.8V */ + bias-disable; + }; + }; + dragon_gsbi12_i2c_pins: gsbi12_i2c { mux { pins = "gpio115", "gpio116"; @@ -448,6 +461,42 @@ }; }; + gsbi@19800000 { + status = "ok"; + qcom,mode = ; + + i2c@19880000 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_gsbi8_i2c_pins>; + + eeprom@52 { + /* A 16KiB Platform ID EEPROM on the CPU carrier board */ + compatible = "atmel,24c128"; + reg = <0x52>; + vcc-supply = <&pm8058_s3>; + pagesize = <64>; + }; + wm8903: wm8903@1a { + /* This Woolfson Micro device has an unrouted interrupt line */ + compatible = "wlf,wm8903"; + reg = <0x1a>; + + AVDD-supply = <&pm8058_l16>; + CPVDD-supply = <&pm8058_l16>; + DBVDD-supply = <&pm8058_s3>; + DCVDD-supply = <&pm8058_l0>; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; + }; + }; + }; + gsbi@19c00000 { status = "ok"; qcom,mode = ; -- cgit v1.2.3 From 9eeb02247723c2ce881319368ce22982f1c7b1ef Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 1 Apr 2017 19:55:48 +0200 Subject: ARM: dts: Add Gemini DMA controller This adds the Faraday Technology FTDMAC020 DMA controller to the Gemini SoC DTSI file. It is only used for memcpy work so we can activate it for all users of the chipset. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index 80abf84f8a80..0beaa4ef757e 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -175,5 +175,22 @@ #interrupt-cells = <1>; }; }; + + dma-controller@67000000 { + compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell"; + /* Faraday Technology FTDMAC020 variant */ + arm,primecell-periphid = <0x0003b080>; + reg = <0x67000000 0x1000>; + interrupts = <9 IRQ_TYPE_EDGE_RISING>; + resets = <&syscon 10>; + clocks = <&syscon 1>; + clock-names = "apb_pclk"; + /* Bus interface AHB1 (AHB0) is totally tilted */ + lli-bus-interface-ahb2; + mem-bus-interface-ahb2; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + #dma-cells = <2>; + }; }; }; -- cgit v1.2.3 From 0d7a2c35d11e974b98a6396cd24b39b0f3f5bb7b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 20 Mar 2017 23:39:26 +0100 Subject: ARM: dts: add Gemini PATA/SATA support The NAS4229B and SQ201 Gemini systems have a PATA controller which is linked to a SATA bridge in the SoC. Enable both platforms to use the PATA/SATA devices. Cc: John Feng-Hsin Chiang Cc: Greentime Hu Acked-by: Hans Ulli Kroll Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini-nas4220b.dts | 10 ++++++++++ arch/arm/boot/dts/gemini-sq201.dts | 10 ++++++++++ arch/arm/boot/dts/gemini.dtsi | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 55 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini-nas4220b.dts index 7668ba52158e..55f6a4f1f801 100644 --- a/arch/arm/boot/dts/gemini-nas4220b.dts +++ b/arch/arm/boot/dts/gemini-nas4220b.dts @@ -98,5 +98,15 @@ read-only; }; }; + + sata: sata@46000000 { + cortina,gemini-ata-muxmode = <0>; + cortina,gemini-enable-sata-bridge; + status = "okay"; + }; + + ata@63000000 { + status = "okay"; + }; }; }; diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts index 46309e79cc7b..4d200f0bcd45 100644 --- a/arch/arm/boot/dts/gemini-sq201.dts +++ b/arch/arm/boot/dts/gemini-sq201.dts @@ -93,6 +93,12 @@ }; }; + sata: sata@46000000 { + cortina,gemini-ata-muxmode = <0>; + cortina,gemini-enable-sata-bridge; + status = "okay"; + }; + pci@50000000 { status = "okay"; interrupt-map-mask = <0xf800 0 0 7>; @@ -114,5 +120,9 @@ <0x6000 0 0 3 &pci_intc 1>, <0x6000 0 0 4 &pci_intc 2>; }; + + ata@63000000 { + status = "okay"; + }; }; }; diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index 0beaa4ef757e..141d8d3a1d07 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -81,6 +81,19 @@ clock-names = "PCLK", "EXTCLK"; }; + sata: sata@46000000 { + compatible = "cortina,gemini-sata-bridge"; + reg = <0x46000000 0x100>; + resets = <&syscon 26>, + <&syscon 27>; + reset-names = "sata0", "sata1"; + clocks = <&syscon 10>, + <&syscon 11>; + clock-names = "SATA0_PCLK", "SATA1_PCLK"; + syscon = <&syscon>; + status = "disabled"; + }; + intcon: interrupt-controller@48000000 { compatible = "faraday,ftintc010"; reg = <0x48000000 0x1000>; @@ -176,6 +189,28 @@ }; }; + ata@63000000 { + compatible = "cortina,gemini-pata", "faraday,ftide010"; + reg = <0x63000000 0x1000>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + resets = <&syscon 2>; + clocks = <&syscon 14>; + clock-names = "PCLK"; + sata = <&sata>; + status = "disabled"; + }; + + ata@63400000 { + compatible = "cortina,gemini-pata", "faraday,ftide010"; + reg = <0x63400000 0x1000>; + interrupts = <5 IRQ_TYPE_EDGE_RISING>; + resets = <&syscon 2>; + clocks = <&syscon 14>; + clock-names = "PCLK"; + sata = <&sata>; + status = "disabled"; + }; + dma-controller@67000000 { compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell"; /* Faraday Technology FTDMAC020 variant */ -- cgit v1.2.3 From 7ade445c26269d5af6c34ee50be97d54a3992d02 Mon Sep 17 00:00:00 2001 From: Petr Cvek Date: Mon, 13 Mar 2017 09:05:49 +0100 Subject: ARM: pxa: magician: Add support for ADS7846 touchscreen This patch adds a support for ADS7846 touchscreen driver. The basic functionality was tested, x_plate_ohms and y_plate_ohms were physically measured. The value pressure_max was empirically set to match the measured range, which is affected by x_plate_ohms and ADS samples. The value of keep_vref_on should be set. A tested model (T-Mobile MDA Compact PM10A) doesn't seem to use Vref pin as the input from an external source. On this model the unset keep_vref_on cause high jitter of measured values. SPI framing pin (gpio_cs) must be used in GPIO mode due to an incompatible autoframing of PXA27x controller and ADS7846 device. Signed-off-by: Petr Cvek Signed-off-by: Robert Jarzmik --- arch/arm/mach-pxa/include/mach/magician.h | 1 + arch/arm/mach-pxa/magician.c | 84 ++++++++++++++++++++++++++++++- 2 files changed, 84 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-pxa/include/mach/magician.h b/arch/arm/mach-pxa/include/mach/magician.h index 5f6b850ebe33..c48b54d0f331 100644 --- a/arch/arm/mach-pxa/include/mach/magician.h +++ b/arch/arm/mach-pxa/include/mach/magician.h @@ -24,6 +24,7 @@ #define GPIO10_MAGICIAN_GSM_IRQ 10 #define GPIO11_MAGICIAN_GSM_OUT1 11 #define GPIO13_MAGICIAN_CPLD_IRQ 13 +#define GPIO14_MAGICIAN_TSC2046_CS 14 #define GPIO18_MAGICIAN_UNKNOWN 18 #define GPIO22_MAGICIAN_VIBRA_EN 22 #define GPIO26_MAGICIAN_GSM_POWER 26 diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index b413e36506af..7f3566c93733 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -54,6 +54,10 @@ #include "devices.h" #include "generic.h" +#include +#include +#include + static unsigned long magician_pin_config[] __initdata = { /* SDRAM and Static Memory I/O Signals */ @@ -85,7 +89,7 @@ static unsigned long magician_pin_config[] __initdata = { /* SSP 2 TSC2046 touchscreen */ GPIO19_SSP2_SCLK, - GPIO14_SSP2_SFRM, + MFP_CFG_OUT(GPIO14, AF0, DRIVE_HIGH), /* frame as GPIO */ GPIO89_SSP2_TXD, GPIO88_SSP2_RXD, @@ -674,6 +678,37 @@ static struct platform_device bq24022 = { }, }; +/* + * fixed regulator for ads7846 + */ + +static struct regulator_consumer_supply ads7846_supply = + REGULATOR_SUPPLY("vcc", "spi2.0"); + +static struct regulator_init_data vads7846_regulator = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &ads7846_supply, +}; + +static struct fixed_voltage_config vads7846 = { + .supply_name = "vads7846", + .microvolts = 3300000, /* probably */ + .gpio = -EINVAL, + .startup_delay = 0, + .init_data = &vads7846_regulator, +}; + +static struct platform_device vads7846_device = { + .name = "reg-fixed-voltage", + .id = -1, + .dev = { + .platform_data = &vads7846, + }, +}; + /* * Vcore regulator MAX1587A */ @@ -851,6 +886,49 @@ static struct i2c_pxa_platform_data magician_i2c_power_info = { .fast_mode = 1, }; +/* + * Touchscreen + */ + +static struct ads7846_platform_data ads7846_pdata = { + .model = 7846, + .x_plate_ohms = 317, + .y_plate_ohms = 500, + .pressure_max = 1023, /* with x plate ohms it will overflow 255 */ + .debounce_max = 3, /* first readout is always bad */ + .debounce_tol = 30, + .debounce_rep = 0, + .gpio_pendown = GPIO115_MAGICIAN_nPEN_IRQ, + .keep_vref_on = 1, + .wakeup = true, + .vref_delay_usecs = 100, + .penirq_recheck_delay_usecs = 100, +}; + +struct pxa2xx_spi_chip tsc2046_chip_info = { + .tx_threshold = 1, + .rx_threshold = 2, + .timeout = 64, + /* NOTICE must be GPIO, incompatibility with hw PXA SPI framing */ + .gpio_cs = GPIO14_MAGICIAN_TSC2046_CS, +}; + +static struct pxa2xx_spi_master magician_spi_info = { + .num_chipselect = 1, + .enable_dma = 1, +}; + +static struct spi_board_info ads7846_spi_board_info[] __initdata = { + { + .modalias = "ads7846", + .bus_num = 2, + .max_speed_hz = 2500000, + .platform_data = &ads7846_pdata, + .controller_data = &tsc2046_chip_info, + .irq = PXA_GPIO_TO_IRQ(GPIO115_MAGICIAN_nPEN_IRQ), + }, +}; + /* * Platform devices */ @@ -865,6 +943,7 @@ static struct platform_device *devices[] __initdata = { &power_supply, &strataflash, &leds_gpio, + &vads7846_device, }; static struct gpio magician_global_gpios[] = { @@ -922,6 +1001,9 @@ static void __init magician_init(void) } else pr_err("LCD detection: CPLD mapping failed\n"); + pxa2xx_set_spi_info(2, &magician_spi_info); + spi_register_board_info(ARRAY_AND_SIZE(ads7846_spi_board_info)); + regulator_register_always_on(0, "power", pwm_backlight_supply, ARRAY_SIZE(pwm_backlight_supply), 5000000); -- cgit v1.2.3 From c276557de3087ef67ad1aec4222f9f8b1d005f80 Mon Sep 17 00:00:00 2001 From: Markus Elfring Date: Sat, 3 Jun 2017 21:34:48 +0200 Subject: ARM: pxa: Delete an error message for a failed memory allocation in pxa_pm_init() Omit an extra message for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Link: http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings-WSang_0.pdf Signed-off-by: Markus Elfring Signed-off-by: Robert Jarzmik --- arch/arm/mach-pxa/pm.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c index e7450fb49d24..f2237f471750 100644 --- a/arch/arm/mach-pxa/pm.c +++ b/arch/arm/mach-pxa/pm.c @@ -107,10 +107,8 @@ static int __init pxa_pm_init(void) sleep_save = kmalloc_array(pxa_cpu_pm_fns->save_count, sizeof(*sleep_save), GFP_KERNEL); - if (!sleep_save) { - printk(KERN_ERR "failed to alloc memory for pm save\n"); + if (!sleep_save) return -ENOMEM; - } suspend_set_ops(&pxa_pm_ops); return 0; -- cgit v1.2.3 From 361f7cc7f33607489bea815f9148e8e9a13ea673 Mon Sep 17 00:00:00 2001 From: Markus Elfring Date: Sat, 3 Jun 2017 21:43:11 +0200 Subject: ARM: pxa: Improve a size determination in pxa3xx_u2d_probe() Replace the specification of a data structure by a pointer dereference as the parameter for the operator "sizeof" to make the corresponding size determination a bit safer according to the Linux coding style convention. Signed-off-by: Markus Elfring Signed-off-by: Robert Jarzmik --- arch/arm/mach-pxa/pxa3xx-ulpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-pxa/pxa3xx-ulpi.c b/arch/arm/mach-pxa/pxa3xx-ulpi.c index eba595fac8ca..13f9909ac8bf 100644 --- a/arch/arm/mach-pxa/pxa3xx-ulpi.c +++ b/arch/arm/mach-pxa/pxa3xx-ulpi.c @@ -286,7 +286,7 @@ static int pxa3xx_u2d_probe(struct platform_device *pdev) struct resource *r; int err; - u2d = kzalloc(sizeof(struct pxa3xx_u2d_ulpi), GFP_KERNEL); + u2d = kzalloc(sizeof(*u2d), GFP_KERNEL); if (!u2d) { dev_err(&pdev->dev, "failed to allocate memory\n"); return -ENOMEM; -- cgit v1.2.3 From ce3de60ff92ba5e4d65f1c1ce07460795e3a6157 Mon Sep 17 00:00:00 2001 From: Markus Elfring Date: Sat, 3 Jun 2017 21:46:26 +0200 Subject: ARM: pxa: Delete an error message for a failed memory allocation in pxa3xx_u2d_probe() Omit an extra message for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Link: http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings-WSang_0.pdf Signed-off-by: Markus Elfring Signed-off-by: Robert Jarzmik --- arch/arm/mach-pxa/pxa3xx-ulpi.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-pxa/pxa3xx-ulpi.c b/arch/arm/mach-pxa/pxa3xx-ulpi.c index 13f9909ac8bf..60cb59a7ebd1 100644 --- a/arch/arm/mach-pxa/pxa3xx-ulpi.c +++ b/arch/arm/mach-pxa/pxa3xx-ulpi.c @@ -287,10 +287,8 @@ static int pxa3xx_u2d_probe(struct platform_device *pdev) int err; u2d = kzalloc(sizeof(*u2d), GFP_KERNEL); - if (!u2d) { - dev_err(&pdev->dev, "failed to allocate memory\n"); + if (!u2d) return -ENOMEM; - } u2d->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(u2d->clk)) { -- cgit v1.2.3 From 25e6cfc81a352a5e85aa8a26972d453c4c121ad1 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 13 Jun 2017 11:28:43 +0200 Subject: ARM: dts: omap4: Fix aes entry OMAP4 has a second aes module, so let's use proper name for the first instance. Signed-off-by: Sebastian Reichel Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 578c53f08309..589690e034d3 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -900,9 +900,9 @@ ctrl-module = <&omap_control_usbotg>; }; - aes: aes@4b501000 { + aes1: aes@4b501000 { compatible = "ti,omap4-aes"; - ti,hwmods = "aes"; + ti,hwmods = "aes1"; reg = <0x4b501000 0xa0>; interrupts = ; dmas = <&sdma 111>, <&sdma 110>; -- cgit v1.2.3 From 7ca3e39719aafb1b9eaf282102574f26d52acd95 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 13 Jun 2017 11:28:44 +0200 Subject: ARM: dts: omap4.dtsi: remove aes[12]_fck "aes1_fck" and "aes2_fck" are controlled by hwmod. Drop clock entries to avoid conflicts. Signed-off-by: Sebastian Reichel Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap44xx-clocks.dtsi | 16 ---------------- 1 file changed, 16 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi index 9cb205b87835..05732ed4f50f 100644 --- a/arch/arm/boot/dts/omap44xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi @@ -975,22 +975,6 @@ ti,max-div = <2>; }; - aes1_fck: aes1_fck@15a0 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3_div_ck>; - ti,bit-shift = <1>; - reg = <0x15a0>; - }; - - aes2_fck: aes2_fck@15a8 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3_div_ck>; - ti,bit-shift = <1>; - reg = <0x15a8>; - }; - dss_sys_clk: dss_sys_clk@1120 { #clock-cells = <0>; compatible = "ti,gate-clock"; -- cgit v1.2.3 From c6faccf21caffc433217f0fa58b8ef5c5e318a5d Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 13 Jun 2017 16:45:48 +0300 Subject: ARM: dts: omap4: add aes2 instance OMAP4 has AES2 instance, so add its integration data under DT. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 589690e034d3..00e7656e0856 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -909,6 +909,15 @@ dma-names = "tx", "rx"; }; + aes2: aes@4b701000 { + compatible = "ti,omap4-aes"; + ti,hwmods = "aes2"; + reg = <0x4b701000 0xa0>; + interrupts = ; + dmas = <&sdma 114>, <&sdma 113>; + dma-names = "tx", "rx"; + }; + des: des@480a5000 { compatible = "ti,omap4-des"; ti,hwmods = "des"; -- cgit v1.2.3 From 45f1d5e3c71d479995cefe9dd30344c62efd60c8 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 13 Jun 2017 16:45:49 +0300 Subject: ARM: dts: omap4: add SHAM node Add SHAM crypto accelerator. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 00e7656e0856..64d00f5893a6 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -927,6 +927,15 @@ dma-names = "tx", "rx"; }; + sham: sham@4b100000 { + compatible = "ti,omap4-sham"; + ti,hwmods = "sham"; + reg = <0x4b100000 0x300>; + interrupts = ; + dmas = <&sdma 119>; + dma-names = "rx"; + }; + abb_mpu: regulator-abb-mpu { compatible = "ti,abb-v2"; regulator-name = "abb_mpu"; -- cgit v1.2.3 From 9a9ded89ad9ca46382a4ea63f36f830bccfab4ec Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 13 Jun 2017 11:28:45 +0200 Subject: ARM: OMAP4: hwmod data: add aes1 This fixes the following error during kernel boot: platform 4b501000.aes: Cannot lookup hwmod 'aes1' Unfortunately the AES module is only documented partly in the OMAP4430 TRM. I found an old patch from Joel, which I took over and updated for currently mainline. Signed-off-by: Joel Fernandes Signed-off-by: Sebastian Reichel Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 41 ++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 0855434773fa..7833caf277b6 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -960,6 +960,46 @@ static struct omap_hwmod omap44xx_emif2_hwmod = { }, }; +/* + Crypto modules AES0/1 belong to: + PD_L4_PER power domain + CD_L4_SEC clock domain + On the L3, the AES modules are mapped to + L3_CLK2: Peripherals and multimedia sub clock domain +*/ +static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = { + .rev_offs = 0x80, + .sysc_offs = 0x84, + .syss_offs = 0x88, + .sysc_flags = SYSS_HAS_RESET_STATUS, +}; + +static struct omap_hwmod_class omap44xx_aes_hwmod_class = { + .name = "aes", + .sysc = &omap44xx_aes_sysc, +}; + +static struct omap_hwmod omap44xx_aes1_hwmod = { + .name = "aes1", + .class = &omap44xx_aes_hwmod_class, + .clkdm_name = "l4_secure_clkdm", + .main_clk = "l3_div_ck", + .prcm = { + .omap4 = { + .context_offs = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET, + .clkctrl_offs = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_aes1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* * 'fdif' class * face detection hw accelerator module @@ -4801,6 +4841,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_abe__wd_timer3_dma, &omap44xx_mpu__emif1, &omap44xx_mpu__emif2, + &omap44xx_l3_main_2__aes1, NULL, }; -- cgit v1.2.3 From 478523dd0341df5833b9f51cae3f9a7c3d20e6bb Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 13 Jun 2017 11:28:46 +0200 Subject: ARM: OMAP4: hwmod data: add aes2 This adds the hwmod entry for the second AES module available on OMAP4. Signed-off-by: Sebastian Reichel Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 7833caf277b6..e1b085977049 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -1000,6 +1000,27 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod omap44xx_aes2_hwmod = { + .name = "aes2", + .class = &omap44xx_aes_hwmod_class, + .clkdm_name = "l4_secure_clkdm", + .main_clk = "l3_div_ck", + .prcm = { + .omap4 = { + .context_offs = OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET, + .clkctrl_offs = OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_aes2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* * 'fdif' class * face detection hw accelerator module @@ -4842,6 +4863,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_mpu__emif1, &omap44xx_mpu__emif2, &omap44xx_l3_main_2__aes1, + &omap44xx_l3_main_2__aes2, NULL, }; -- cgit v1.2.3 From ebea90df78c1f290529e18b85c19653e131954de Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 13 Jun 2017 11:28:47 +0200 Subject: ARM: OMAP4: hwmod data: add des This fixes the following error during kernel boot: platform 480a5000.des: Cannot lookup hwmod 'des' Unfortunately the DES module is only documented partly in the OMAP4430 TRM. I found an old patch from Joel, which I took over and updated for currently mainline. Signed-off-by: Joel Fernandes Signed-off-by: Sebastian Reichel Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 37 ++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index e1b085977049..ef4389ce65fe 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -1021,6 +1021,42 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* + * 'des' class for DES3DES module + */ +static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = { + .rev_offs = 0x30, + .sysc_offs = 0x34, + .syss_offs = 0x38, + .sysc_flags = SYSS_HAS_RESET_STATUS, +}; + +static struct omap_hwmod_class omap44xx_des_hwmod_class = { + .name = "des", + .sysc = &omap44xx_des_sysc, +}; + +static struct omap_hwmod omap44xx_des_hwmod = { + .name = "des", + .class = &omap44xx_des_hwmod_class, + .clkdm_name = "l4_secure_clkdm", + .main_clk = "l3_div_ck", + .prcm = { + .omap4 = { + .context_offs = OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET, + .clkctrl_offs = OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_des_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* * 'fdif' class * face detection hw accelerator module @@ -4864,6 +4900,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_mpu__emif2, &omap44xx_l3_main_2__aes1, &omap44xx_l3_main_2__aes2, + &omap44xx_l3_main_2__des, NULL, }; -- cgit v1.2.3 From 1df5eaa6bced2d8a9de305d4a5f587adf57ddf35 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 13 Jun 2017 16:45:50 +0300 Subject: ARM: OMAP4: hwmod_data: add SHAM crypto accelerator OMAP4 SoC contains SHAM crypto hardware accelerator. Add hwmod data for this IP so that it can be utilized by crypto frameworks. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 36 ++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index ef4389ce65fe..3e2d792fd9df 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -880,6 +880,33 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = { .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), }; +/* sha0 HIB2 (the 'P' (public) device) */ +static struct omap_hwmod_class_sysconfig omap44xx_sha0_sysc = { + .rev_offs = 0x100, + .sysc_offs = 0x110, + .syss_offs = 0x114, + .sysc_flags = SYSS_HAS_RESET_STATUS, +}; + +static struct omap_hwmod_class omap44xx_sha0_hwmod_class = { + .name = "sham", + .sysc = &omap44xx_sha0_sysc, +}; + +struct omap_hwmod omap44xx_sha0_hwmod = { + .name = "sham", + .class = &omap44xx_sha0_hwmod_class, + .clkdm_name = "l4_secure_clkdm", + .main_clk = "l3_div_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + /* * 'elm' class * bch error location module @@ -3987,6 +4014,14 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { .user = OCP_USER_MPU, }; +/* l3_main_2 -> sham */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_sha0_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_per -> elm */ static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { .master = &omap44xx_l4_per_hwmod, @@ -4901,6 +4936,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l3_main_2__aes1, &omap44xx_l3_main_2__aes2, &omap44xx_l3_main_2__des, + &omap44xx_l3_main_2__sha0, NULL, }; -- cgit v1.2.3 From fd8cf827d8a635df3dad46773ad828ce4c93d95b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 12 Jun 2017 11:23:46 +0200 Subject: ARM: shmobile: pm-rmobile: Use GENPD_FLAG_ALWAYS_ON Improve handling of always-on PM domains by using the GENPD_FLAG_ALWAYS_ON flag introduced in commit ffaa42e8a40b7f10 ("PM / Domains: Enable users of genpd to specify always on PM domains"). Note that the PM domain containing the serial console is still handled locally. Signed-off-by: Geert Uytterhoeven Reviewed-by: Ulf Hansson Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/pm-rmobile.c | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c index 45a195501b78..699429f28b73 100644 --- a/arch/arm/mach-shmobile/pm-rmobile.c +++ b/arch/arm/mach-shmobile/pm-rmobile.c @@ -130,7 +130,7 @@ static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd) struct generic_pm_domain *genpd = &rmobile_pd->genpd; struct dev_power_governor *gov = rmobile_pd->gov; - genpd->flags = GENPD_FLAG_PM_CLK; + genpd->flags |= GENPD_FLAG_PM_CLK; genpd->dev_ops.active_wakeup = rmobile_pd_active_wakeup; genpd->power_off = rmobile_pd_power_down; genpd->power_on = rmobile_pd_power_up; @@ -140,14 +140,6 @@ static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd) pm_genpd_init(genpd, gov ? : &simple_qos_governor, false); } -static int rmobile_pd_suspend_busy(void) -{ - /* - * This domain should not be turned off. - */ - return -EBUSY; -} - static int rmobile_pd_suspend_console(void) { /* @@ -260,8 +252,7 @@ static void __init rmobile_setup_pm_domain(struct device_node *np, * only be turned off if the CPU is not in use. */ pr_debug("PM domain %s contains CPU\n", name); - pd->gov = &pm_domain_always_on_gov; - pd->suspend = rmobile_pd_suspend_busy; + pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON; break; case PD_CONSOLE: @@ -277,8 +268,7 @@ static void __init rmobile_setup_pm_domain(struct device_node *np, * is not in use. */ pr_debug("PM domain %s contains Coresight-ETM\n", name); - pd->gov = &pm_domain_always_on_gov; - pd->suspend = rmobile_pd_suspend_busy; + pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON; break; case PD_MEMCTL: @@ -287,8 +277,7 @@ static void __init rmobile_setup_pm_domain(struct device_node *np, * should only be turned off if memory is not in use. */ pr_debug("PM domain %s contains MEMCTL\n", name); - pd->gov = &pm_domain_always_on_gov; - pd->suspend = rmobile_pd_suspend_busy; + pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON; break; case PD_NORMAL: -- cgit v1.2.3 From d565ed38d045793b76f022565a50793a3535bdbd Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 14 Jun 2017 11:54:29 +0200 Subject: arm: mach-rpc: ecard: fix build error The last commit from me had a missing ';' which broke the build. Thanks to Arnd for pointing out the issue. Reported-by: Arnd Bergmann Signed-off-by: Greg Kroah-Hartman --- arch/arm/mach-rpc/ecard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-rpc/ecard.c b/arch/arm/mach-rpc/ecard.c index 5966964222b5..bdb5ec1cf560 100644 --- a/arch/arm/mach-rpc/ecard.c +++ b/arch/arm/mach-rpc/ecard.c @@ -789,7 +789,7 @@ static ssize_t resource_show(struct device *dev, struct device_attribute *attr, return str - buf; } -static DEVICE_ATTR_RO(resource) +static DEVICE_ATTR_RO(resource); static ssize_t vendor_show(struct device *dev, struct device_attribute *attr, char *buf) { -- cgit v1.2.3 From 1727339590fdb5a1ded881b540cd32121278d414 Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Fri, 26 May 2017 16:56:11 +0200 Subject: clocksource/drivers: Rename CLOCKSOURCE_OF_DECLARE to TIMER_OF_DECLARE The CLOCKSOURCE_OF_DECLARE macro is used widely for the timers to declare the clocksource at early stage. However, this macro is also used to initialize the clockevent if any, or the clockevent only. It was originally suggested to declare another macro to initialize a clockevent, so in order to separate the two entities even they belong to the same IP. This was not accepted because of the impact on the DT where splitting a clocksource/clockevent definition does not make sense as it is a Linux concept not a hardware description. On the other side, the clocksource has not interrupt declared while the clockevent has, so it is easy from the driver to know if the description is for a clockevent or a clocksource, IOW it could be implemented at the driver level. So instead of dealing with a named clocksource macro, let's use a more generic one: TIMER_OF_DECLARE. The patch has not functional changes. Signed-off-by: Daniel Lezcano Acked-by: Heiko Stuebner Acked-by: Neil Armstrong Acked-by: Arnd Bergmann Acked-by: Matthias Brugger Reviewed-by: Linus Walleij --- arch/arm/kernel/smp_twd.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index 895ae5197159..b30eafeef096 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c @@ -403,7 +403,7 @@ out: WARN(err, "twd_local_timer_of_register failed (%d)\n", err); return err; } -CLOCKSOURCE_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register); -CLOCKSOURCE_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register); -CLOCKSOURCE_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register); +TIMER_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register); +TIMER_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register); +TIMER_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register); #endif -- cgit v1.2.3 From ba5d08c0ea785d5710c5a1e7dc3182b7124d63c0 Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Fri, 26 May 2017 17:40:46 +0200 Subject: clocksource/drivers: Rename clocksource_probe to timer_probe The function name is now renamed to 'timer_probe' for consistency with the CLOCKSOURCE_OF_DECLARE => TIMER_OF_DECLARE change. Signed-off-by: Daniel Lezcano Acked-by: Viresh Kumar Acked-by: Heiko Stuebner Reviewed-by: Linus Walleij --- arch/arm/kernel/time.c | 2 +- arch/arm/mach-mediatek/mediatek.c | 2 +- arch/arm/mach-omap2/timer.c | 10 +++++----- arch/arm/mach-rockchip/rockchip.c | 2 +- arch/arm/mach-shmobile/setup-rcar-gen2.c | 2 +- arch/arm/mach-spear/spear13xx.c | 2 +- arch/arm/mach-sunxi/sunxi.c | 2 +- arch/arm/mach-u300/core.c | 2 +- arch/arm/mach-zynq/common.c | 2 +- 9 files changed, 13 insertions(+), 13 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index 97b22fa7cb3a..629f8e9981f1 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c @@ -120,6 +120,6 @@ void __init time_init(void) #ifdef CONFIG_COMMON_CLK of_clk_init(NULL); #endif - clocksource_probe(); + timer_probe(); } } diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c index a6e3c98b95ed..c3cf215773b2 100644 --- a/arch/arm/mach-mediatek/mediatek.c +++ b/arch/arm/mach-mediatek/mediatek.c @@ -41,7 +41,7 @@ static void __init mediatek_timer_init(void) } of_clk_init(NULL); - clocksource_probe(); + timer_probe(); }; static const char * const mediatek_board_dt_compat[] = { diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 07dd692c4737..ae4bb9fdc483 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -497,7 +497,7 @@ void __init omap_init_time(void) __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon", 2, "timer_sys_ck", NULL, false); - clocksource_probe(); + timer_probe(); } #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX) @@ -506,7 +506,7 @@ void __init omap3_secure_sync32k_timer_init(void) __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure", 2, "timer_sys_ck", NULL, false); - clocksource_probe(); + timer_probe(); } #endif /* CONFIG_ARCH_OMAP3 */ @@ -517,7 +517,7 @@ void __init omap3_gptimer_timer_init(void) __omap_sync32k_timer_init(2, "timer_sys_ck", NULL, 1, "timer_sys_ck", "ti,timer-alwon", true); if (of_have_populated_dt()) - clocksource_probe(); + timer_probe(); } #endif @@ -532,7 +532,7 @@ static void __init omap4_sync32k_timer_init(void) void __init omap4_local_timer_init(void) { omap4_sync32k_timer_init(); - clocksource_probe(); + timer_probe(); } #endif @@ -656,7 +656,7 @@ void __init omap5_realtime_timer_init(void) omap4_sync32k_timer_init(); realtime_counter_init(); - clocksource_probe(); + timer_probe(); } #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */ diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c index ef0500a4c8ad..5ab834ebcb49 100644 --- a/arch/arm/mach-rockchip/rockchip.c +++ b/arch/arm/mach-rockchip/rockchip.c @@ -55,7 +55,7 @@ static void __init rockchip_timer_init(void) } of_clk_init(NULL); - clocksource_probe(); + timer_probe(); } static void __init rockchip_dt_init(void) diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c index 52d466b75973..a6e74f481dea 100644 --- a/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c @@ -113,7 +113,7 @@ void __init rcar_gen2_timer_init(void) #endif /* CONFIG_ARM_ARCH_TIMER */ of_clk_init(NULL); - clocksource_probe(); + timer_probe(); } struct memory_reserve_config { diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c index ca2f6a82a414..31c43cabf362 100644 --- a/arch/arm/mach-spear/spear13xx.c +++ b/arch/arm/mach-spear/spear13xx.c @@ -124,5 +124,5 @@ void __init spear13xx_timer_init(void) clk_put(pclk); spear_setup_of_timer(); - clocksource_probe(); + timer_probe(); } diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index f44e3acb5c90..7ab353fb25f2 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -42,7 +42,7 @@ static void __init sun6i_timer_init(void) of_clk_init(NULL); if (IS_ENABLED(CONFIG_RESET_CONTROLLER)) sun6i_reset_init(); - clocksource_probe(); + timer_probe(); } DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family") diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index a4910ea6811a..048f15e8c669 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -407,7 +407,7 @@ static const char * u300_board_compat[] = { DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)") .map_io = u300_map_io, .init_irq = u300_init_irq_dt, - .init_time = clocksource_probe, + .init_time = timer_probe, .init_machine = u300_init_machine_dt, .restart = u300_restart, .dt_compat = u300_board_compat, diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index ed118648313f..6aba9ebf8041 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -150,7 +150,7 @@ static void __init zynq_timer_init(void) { zynq_clock_init(); of_clk_init(NULL); - clocksource_probe(); + timer_probe(); } static struct map_desc zynq_cortex_a9_scu_map __initdata = { -- cgit v1.2.3 From bb0eb050a577a866cb47c2dc37596f1207f4c2d9 Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Fri, 26 May 2017 19:34:11 +0200 Subject: clocksource/drivers: Rename CLKSRC_OF to TIMER_OF The config option name is now renamed to 'TIMER_OF' for consistency with the CLOCKSOURCE_OF_DECLARE => TIMER_OF_DECLARE change. Signed-off-by: Daniel Lezcano Reviewed-by: Linus Walleij --- arch/arm/Kconfig | 10 +++++----- arch/arm/mach-bcm/Kconfig | 2 +- arch/arm/mach-clps711x/Kconfig | 2 +- arch/arm/mach-s3c24xx/Kconfig | 2 +- arch/arm/mach-s3c64xx/Kconfig | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4c1a35f15838..1c7e165b0a93 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -337,7 +337,7 @@ config ARCH_MULTIPLATFORM select ARM_HAS_SG_CHAIN select ARM_PATCH_PHYS_VIRT select AUTO_ZRELADDR - select CLKSRC_OF + select TIMER_OF select COMMON_CLK select GENERIC_CLOCKEVENTS select MIGHT_HAVE_PCI @@ -351,7 +351,7 @@ config ARM_SINGLE_ARMV7M depends on !MMU select ARM_NVIC select AUTO_ZRELADDR - select CLKSRC_OF + select TIMER_OF select COMMON_CLK select CPU_V7M select GENERIC_CLOCKEVENTS @@ -532,7 +532,7 @@ config ARCH_PXA select CLKDEV_LOOKUP select CLKSRC_PXA select CLKSRC_MMIO - select CLKSRC_OF + select TIMER_OF select CPU_XSCALE if !CPU_XSC3 select GENERIC_CLOCKEVENTS select GPIO_PXA @@ -571,7 +571,7 @@ config ARCH_SA1100 select CLKDEV_LOOKUP select CLKSRC_MMIO select CLKSRC_PXA - select CLKSRC_OF if OF + select TIMER_OF if OF select CPU_FREQ select CPU_SA1100 select GENERIC_CLOCKEVENTS @@ -1357,7 +1357,7 @@ config HAVE_ARM_ARCH_TIMER config HAVE_ARM_TWD bool - select CLKSRC_OF if OF + select TIMER_OF if OF help This options enables support for the ARM timer and watchdog unit diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index f9389c5910e7..f23a23934162 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -150,7 +150,7 @@ config ARCH_BCM2835 select ARM_ERRATA_411920 if ARCH_MULTI_V6 select ARM_TIMER_SP804 select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7 - select CLKSRC_OF + select TIMER_OF select BCM2835_TIMER select PINCTRL select PINCTRL_BCM2835 diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig index 61284b9389cf..f385b1fcafef 100644 --- a/arch/arm/mach-clps711x/Kconfig +++ b/arch/arm/mach-clps711x/Kconfig @@ -2,7 +2,7 @@ menuconfig ARCH_CLPS711X bool "Cirrus Logic EP721x/EP731x-based" depends on ARCH_MULTI_V4T select AUTO_ZRELADDR - select CLKSRC_OF + select TIMER_OF select CLPS711X_TIMER select COMMON_CLK select CPU_ARM720T diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index 4b1690acb6a5..f07da82ebfea 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -394,7 +394,7 @@ config MACH_SMDK2416 config MACH_S3C2416_DT bool "Samsung S3C2416 machine using devicetree" - select CLKSRC_OF + select TIMER_OF select USE_OF select PINCTRL select PINCTRL_S3C24XX diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 459214fa20b4..71a49343d711 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -336,7 +336,7 @@ config MACH_WLF_CRAGG_6410 config MACH_S3C64XX_DT bool "Samsung S3C6400/S3C6410 machine using Device Tree" - select CLKSRC_OF + select TIMER_OF select CPU_S3C6400 select CPU_S3C6410 select PINCTRL -- cgit v1.2.3 From bc97e88ecd360a730b0f9c96f285b680be496e06 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 12 Jun 2017 11:23:54 -0700 Subject: ARM: dts: imx6qdl: add multiplexer controls The IOMUXC General Purpose Register space contains various bitfields that control video bus multiplexers. Describe them using a mmio-mux node. The placement of the IPU CSI video mux controls differs between i.MX6D/Q and i.MX6S/DL. Signed-off-by: Philipp Zabel Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl.dtsi | 10 ++++++++++ arch/arm/boot/dts/imx6q.dtsi | 10 ++++++++++ arch/arm/boot/dts/imx6qdl.dtsi | 7 ++++++- 3 files changed, 26 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 7aa120fbdc71..10bc9d135956 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -181,6 +181,16 @@ "di0", "di1"; }; +&mux { + mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */ + <0x34 0x00000038>, /* IPU_CSI1_MUX */ + <0x0c 0x0000000c>, /* HDMI_MUX_CTL */ + <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */ + <0x0c 0x00000300>, /* LVDS1_MUX_CTL */ + <0x28 0x00000003>, /* DCIC1_MUX_CTL */ + <0x28 0x0000000c>; /* DCIC2_MUX_CTL */ +}; + &vpu { compatible = "fsl,imx6dl-vpu", "cnm,coda960"; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index dd33849335b2..1a14ae2ce6d8 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -332,6 +332,16 @@ }; }; +&mux { + mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */ + <0x04 0x00100000>, /* MIPI_IPU2_MUX */ + <0x0c 0x0000000c>, /* HDMI_MUX_CTL */ + <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */ + <0x0c 0x00000300>, /* LVDS1_MUX_CTL */ + <0x28 0x00000003>, /* DCIC1_MUX_CTL */ + <0x28 0x0000000c>; /* DCIC2_MUX_CTL */ +}; + &vpu { compatible = "fsl,imx6q-vpu", "cnm,coda960"; }; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index f325411f66aa..4ea7d86e625e 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -826,8 +826,13 @@ }; gpr: iomuxc-gpr@020e0000 { - compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; + compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; reg = <0x020e0000 0x38>; + + mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + }; }; iomuxc: iomuxc@020e0000 { -- cgit v1.2.3 From b0cb1bd4a380da07ef9536054f37f2cd9a777384 Mon Sep 17 00:00:00 2001 From: Steve Longerbeam Date: Mon, 12 Jun 2017 11:23:55 -0700 Subject: ARM: dts: imx6qdl: Add compatible, clocks, irqs to MIPI CSI-2 node Add to the MIPI CSI2 receiver node: compatible strings, interrupt sources, and clocks. Signed-off-by: Steve Longerbeam Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 4ea7d86e625e..a42a3fd3ee94 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1158,7 +1158,14 @@ }; mipi_csi: mipi@021dc000 { + compatible = "fsl,imx6-mipi-csi2"; reg = <0x021dc000 0x4000>; + interrupts = <0 100 0x04>, <0 101 0x04>; + clocks = <&clks IMX6QDL_CLK_HSI_TX>, + <&clks IMX6QDL_CLK_VIDEO_27M>, + <&clks IMX6QDL_CLK_EIM_PODF>; + clock-names = "dphy", "ref", "pix"; + status = "disabled"; }; mipi_dsi: mipi@021e0000 { -- cgit v1.2.3 From 2539f517acbdc8471f0aebdffe894eb571103368 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 12 Jun 2017 11:23:56 -0700 Subject: ARM: dts: imx6qdl: Add video multiplexers, mipi_csi, and their connections This patch adds the device tree graph connecting the input multiplexers to the IPU CSIs and the MIPI-CSI2 gasket on i.MX6. The MIPI_IPU multiplexers are added as children of the iomuxc-gpr syscon device node. On i.MX6Q/D two two-input multiplexers in front of IPU1 CSI0 and IPU2 CSI1 allow to select between CSI0/1 parallel input pads and the MIPI CSI-2 virtual channels 0/3. On i.MX6DL/S two five-input multiplexers in front of IPU1 CSI0 and IPU1 CSI1 allow to select between CSI0/1 parallel input pads and any of the four MIPI CSI-2 virtual channels. Changes from Steve Longerbeam: - Removed some dangling/unused endpoints (ipu2_csi0_from_csi2ipu) - Renamed the mipi virtual channel endpoint labels, from "mipi_csiX_..." to "mipi_vcX...". - Added input endpoint anchors to the video muxes for the connections from parallel sensors. Signed-off-by: Philipp Zabel Signed-off-by: Steve Longerbeam Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl.dtsi | 174 +++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx6q.dtsi | 110 ++++++++++++++++++++++++++ arch/arm/boot/dts/imx6qdl.dtsi | 6 ++ 3 files changed, 290 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 10bc9d135956..4049af7cb45a 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -164,6 +164,116 @@ <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>; }; +&gpr { + ipu1_csi0_mux: ipu1_csi0_mux@34 { + compatible = "video-mux"; + mux-controls = <&mux 0>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ipu1_csi0_mux_from_mipi_vc0: endpoint { + remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>; + }; + }; + + port@1 { + reg = <1>; + + ipu1_csi0_mux_from_mipi_vc1: endpoint { + remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>; + }; + }; + + port@2 { + reg = <2>; + + ipu1_csi0_mux_from_mipi_vc2: endpoint { + remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>; + }; + }; + + port@3 { + reg = <3>; + + ipu1_csi0_mux_from_mipi_vc3: endpoint { + remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>; + }; + }; + + port@4 { + reg = <4>; + + ipu1_csi0_mux_from_parallel_sensor: endpoint { + }; + }; + + port@5 { + reg = <5>; + + ipu1_csi0_mux_to_ipu1_csi0: endpoint { + remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>; + }; + }; + }; + + ipu1_csi1_mux: ipu1_csi1_mux@34 { + compatible = "video-mux"; + mux-controls = <&mux 1>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ipu1_csi1_mux_from_mipi_vc0: endpoint { + remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>; + }; + }; + + port@1 { + reg = <1>; + + ipu1_csi1_mux_from_mipi_vc1: endpoint { + remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>; + }; + }; + + port@2 { + reg = <2>; + + ipu1_csi1_mux_from_mipi_vc2: endpoint { + remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>; + }; + }; + + port@3 { + reg = <3>; + + ipu1_csi1_mux_from_mipi_vc3: endpoint { + remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>; + }; + }; + + port@4 { + reg = <4>; + + ipu1_csi1_mux_from_parallel_sensor: endpoint { + }; + }; + + port@5 { + reg = <5>; + + ipu1_csi1_mux_to_ipu1_csi1: endpoint { + remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>; + }; + }; + }; +}; + &gpt { compatible = "fsl,imx6dl-gpt"; }; @@ -172,6 +282,12 @@ compatible = "fsl,imx6dl-hdmi"; }; +&ipu1_csi1 { + ipu1_csi1_from_ipu1_csi1_mux: endpoint { + remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>; + }; +}; + &ldb { clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, @@ -181,6 +297,64 @@ "di0", "di1"; }; +&mipi_csi { + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_vc0_to_ipu1_csi0_mux: endpoint@0 { + remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>; + }; + + mipi_vc0_to_ipu1_csi1_mux: endpoint@1 { + remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>; + }; + }; + + port@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_vc1_to_ipu1_csi0_mux: endpoint@0 { + remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>; + }; + + mipi_vc1_to_ipu1_csi1_mux: endpoint@1 { + remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>; + }; + }; + + port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_vc2_to_ipu1_csi0_mux: endpoint@0 { + remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>; + }; + + mipi_vc2_to_ipu1_csi1_mux: endpoint@1 { + remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>; + }; + }; + + port@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_vc3_to_ipu1_csi0_mux: endpoint@0 { + remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>; + }; + + mipi_vc3_to_ipu1_csi1_mux: endpoint@1 { + remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>; + }; + }; +}; + &mux { mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */ <0x34 0x00000038>, /* IPU_CSI1_MUX */ diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 1a14ae2ce6d8..39d150463dfc 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -143,10 +143,18 @@ ipu2_csi0: port@0 { reg = <0>; + + ipu2_csi0_from_mipi_vc2: endpoint { + remote-endpoint = <&mipi_vc2_to_ipu2_csi0>; + }; }; ipu2_csi1: port@1 { reg = <1>; + + ipu2_csi1_from_ipu2_csi1_mux: endpoint { + remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>; + }; }; ipu2_di0: port@2 { @@ -246,6 +254,68 @@ gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>; }; +&gpr { + ipu1_csi0_mux { + compatible = "video-mux"; + mux-controls = <&mux 0>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ipu1_csi0_mux_from_mipi_vc0: endpoint { + remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>; + }; + }; + + port@1 { + reg = <1>; + + ipu1_csi0_mux_from_parallel_sensor: endpoint { + }; + }; + + port@2 { + reg = <2>; + + ipu1_csi0_mux_to_ipu1_csi0: endpoint { + remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>; + }; + }; + }; + + ipu2_csi1_mux { + compatible = "video-mux"; + mux-controls = <&mux 1>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ipu2_csi1_mux_from_mipi_vc3: endpoint { + remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>; + }; + }; + + port@1 { + reg = <1>; + + ipu2_csi1_mux_from_parallel_sensor: endpoint { + }; + }; + + port@2 { + reg = <2>; + + ipu2_csi1_mux_to_ipu2_csi1: endpoint { + remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>; + }; + }; + }; +}; + &hdmi { compatible = "fsl,imx6q-hdmi"; @@ -266,6 +336,12 @@ }; }; +&ipu1_csi1 { + ipu1_csi1_from_mipi_vc1: endpoint { + remote-endpoint = <&mipi_vc1_to_ipu1_csi1>; + }; +}; + &ldb { clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, @@ -312,6 +388,40 @@ }; }; +&mipi_csi { + port@1 { + reg = <1>; + + mipi_vc0_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>; + }; + }; + + port@2 { + reg = <2>; + + mipi_vc1_to_ipu1_csi1: endpoint { + remote-endpoint = <&ipu1_csi1_from_mipi_vc1>; + }; + }; + + port@3 { + reg = <3>; + + mipi_vc2_to_ipu2_csi0: endpoint { + remote-endpoint = <&ipu2_csi0_from_mipi_vc2>; + }; + }; + + port@4 { + reg = <4>; + + mipi_vc3_to_ipu2_csi1_mux: endpoint { + remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>; + }; + }; +}; + &mipi_dsi { ports { port@2 { diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index a42a3fd3ee94..a9723b94bafa 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1160,6 +1160,8 @@ mipi_csi: mipi@021dc000 { compatible = "fsl,imx6-mipi-csi2"; reg = <0x021dc000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 100 0x04>, <0 101 0x04>; clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>, @@ -1267,6 +1269,10 @@ ipu1_csi0: port@0 { reg = <0>; + + ipu1_csi0_from_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>; + }; }; ipu1_csi1: port@1 { -- cgit v1.2.3 From d72ee3a12b9a1c43dbe412ef799df341d8161dd0 Mon Sep 17 00:00:00 2001 From: Steve Longerbeam Date: Mon, 12 Jun 2017 11:23:57 -0700 Subject: ARM: dts: imx6qdl: add capture-subsystem device Signed-off-by: Steve Longerbeam Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl.dtsi | 5 +++++ arch/arm/boot/dts/imx6q.dtsi | 5 +++++ 2 files changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 4049af7cb45a..8475e6cc59ac 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -100,6 +100,11 @@ }; }; + capture-subsystem { + compatible = "fsl,imx-capture-subsystem"; + ports = <&ipu1_csi0>, <&ipu1_csi1>; + }; + display-subsystem { compatible = "fsl,imx-display-subsystem"; ports = <&ipu1_di0>, <&ipu1_di1>; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 39d150463dfc..90a741732f60 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -206,6 +206,11 @@ }; }; + capture-subsystem { + compatible = "fsl,imx-capture-subsystem"; + ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>; + }; + display-subsystem { compatible = "fsl,imx-display-subsystem"; ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; -- cgit v1.2.3 From 4c8777892e80bbe39efd0584502793b4b244f99b Mon Sep 17 00:00:00 2001 From: Steve Longerbeam Date: Mon, 12 Jun 2017 11:23:58 -0700 Subject: ARM: dts: imx6qdl-sabrelite: remove erratum ERR006687 workaround There is a pin conflict with GPIO_6. This pin functions as a power input pin to the OV5642 camera sensor, but ENET uses it as the h/w workaround for erratum ERR006687, to wake-up the ARM cores on normal RX and TX packet done events. So we need to remove the h/w workaround to support the OV5642. The result is that the CPUidle driver will no longer allow entering the deep idle states on the sabrelite. This is a partial revert of commit 6261c4c8f13e ("ARM: dts: imx6qdl-sabrelite: use GPIO_6 for FEC interrupt.") commit a28eeb43ee57 ("ARM: dts: imx6: tag boards that have the HW workaround for ERR006687") Signed-off-by: Steve Longerbeam Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index 84131794e97b..89dce27dfbad 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -270,9 +270,6 @@ txd1-skew-ps = <0>; txd2-skew-ps = <0>; txd3-skew-ps = <0>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; status = "okay"; }; @@ -373,7 +370,6 @@ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 /* Phy reset */ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 >; }; -- cgit v1.2.3 From 789459c41cae9c52e8c16ff9557e53487c243e6d Mon Sep 17 00:00:00 2001 From: Steve Longerbeam Date: Mon, 12 Jun 2017 11:23:59 -0700 Subject: ARM: dts: imx6-sabrelite: add OV5642 and OV5640 camera sensors Adds the OV5642 parallel-bus sensor, and the OV5640 MIPI CSI-2 sensor. Both hang off the same i2c2 bus, so they require different (and non- default) i2c slave addresses. The OV5642 connects to the parallel-bus mux input port on ipu1_csi0_mux. The OV5640 connects to the input port on the MIPI CSI-2 receiver on mipi_csi. The OV5642 node is disabled temporarily while the subdev driver is cleaned up and submitted later. Signed-off-by: Steve Longerbeam Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-sabrelite.dts | 5 ++ arch/arm/boot/dts/imx6q-sabrelite.dts | 5 ++ arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 148 +++++++++++++++++++++++++++++++ 3 files changed, 158 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6dl-sabrelite.dts b/arch/arm/boot/dts/imx6dl-sabrelite.dts index 2f904527a097..33040761b253 100644 --- a/arch/arm/boot/dts/imx6dl-sabrelite.dts +++ b/arch/arm/boot/dts/imx6dl-sabrelite.dts @@ -48,3 +48,8 @@ model = "Freescale i.MX6 DualLite SABRE Lite Board"; compatible = "fsl,imx6dl-sabrelite", "fsl,imx6dl"; }; + +&ipu1_csi1_from_ipu1_csi1_mux { + clock-lanes = <0>; + data-lanes = <1 2>; +}; diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index 02a7cdfd57c9..dc51262e7b2f 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -52,3 +52,8 @@ &sata { status = "okay"; }; + +&ipu1_csi1_from_mipi_vc1 { + clock-lanes = <0>; + data-lanes = <1 2>; +}; diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index 89dce27dfbad..afe7449c47da 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -39,6 +39,8 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ + +#include #include #include @@ -94,6 +96,42 @@ pinctrl-0 = <&pinctrl_can_xcvr>; gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; }; + + reg_1p5v: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "1P5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + reg_1p8v: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p8v: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "2P8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + }; + + mipi_xclk: mipi_xclk { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <22000000>; + clock-output-names = "mipi_pwm3"; + pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */ + status = "okay"; }; gpio-keys { @@ -220,6 +258,22 @@ }; }; +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <8>; + data-shift = <12>; /* Lines 19:12 used */ + hsync-active = <1>; + vync-active = <1>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&ov5642_to_ipu1_csi0_mux>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; +}; + &audmux { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; @@ -298,6 +352,53 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + + ov5640: camera@40 { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x40>; + clocks = <&mipi_xclk>; + clock-names = "xclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p8v>; + DVDD-supply = <®_1p5v>; + reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* NANDF_D5 */ + powerdown-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* NANDF_WP_B */ + + port { + #address-cells = <1>; + #size-cells = <0>; + + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + + ov5642: camera@42 { + compatible = "ovti,ov5642"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5642>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "xclk"; + reg = <0x42>; + reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + powerdown-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + gp-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; + status = "disabled"; + + port { + ov5642_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <8>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; }; &i2c3 { @@ -411,6 +512,23 @@ >; }; + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0 + >; + }; + pinctrl_j15: j15grp { fsl,pins = < MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 @@ -444,6 +562,22 @@ >; }; + pinctrl_ov5640: ov5640grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 + >; + }; + + pinctrl_ov5642: ov5642grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0 + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 + >; + }; + pinctrl_pwm1: pwm1grp { fsl,pins = < MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 @@ -598,3 +732,17 @@ vmmc-supply = <®_3p3v>; status = "okay"; }; + +&mipi_csi { + status = "okay"; + + port@0 { + reg = <0>; + + mipi_csi2_in: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; +}; -- cgit v1.2.3 From 545fb52e53d6dfa9e64e0a10c336d8473319d077 Mon Sep 17 00:00:00 2001 From: Steve Longerbeam Date: Mon, 12 Jun 2017 11:24:00 -0700 Subject: ARM: dts: imx6-sabresd: add OV5642 and OV5640 camera sensors Enables the OV5642 parallel-bus sensor, and the OV5640 MIPI CSI-2 sensor. The OV5642 connects to the parallel-bus mux input port on ipu1_csi0_mux. The OV5640 connects to the input port on the MIPI CSI-2 receiver on mipi_csi. Until the OV5652 sensor module compatible with the SabreSD becomes available for testing, the ov5642 node is currently disabled. Signed-off-by: Steve Longerbeam Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-sabresd.dts | 5 ++ arch/arm/boot/dts/imx6q-sabresd.dts | 5 ++ arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 114 ++++++++++++++++++++++++++++++++- 3 files changed, 123 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts index 1e45f2f9d0b6..9607afe088fc 100644 --- a/arch/arm/boot/dts/imx6dl-sabresd.dts +++ b/arch/arm/boot/dts/imx6dl-sabresd.dts @@ -15,3 +15,8 @@ model = "Freescale i.MX6 DualLite SABRE Smart Device Board"; compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; }; + +&ipu1_csi1_from_ipu1_csi1_mux { + clock-lanes = <0>; + data-lanes = <1 2>; +}; diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts index 9cbdfe7a0931..527772b62fee 100644 --- a/arch/arm/boot/dts/imx6q-sabresd.dts +++ b/arch/arm/boot/dts/imx6q-sabresd.dts @@ -23,3 +23,8 @@ &sata { status = "okay"; }; + +&ipu1_csi1_from_mipi_vc1 { + clock-lanes = <0>; + data-lanes = <1 2>; +}; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index db705f1cbe37..b72b6fa47580 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -10,6 +10,7 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include #include #include @@ -146,6 +147,36 @@ }; }; +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <8>; + data-shift = <12>; /* Lines 19:12 used */ + hsync-active = <1>; + vsync-active = <1>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&ov5642_to_ipu1_csi0_mux>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; +}; + +&mipi_csi { + status = "okay"; + + port@0 { + reg = <0>; + + mipi_csi2_in: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; +}; + &audmux { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; @@ -213,7 +244,32 @@ 0x8014 /* 4:FN_DMICCDAT */ 0x0000 /* 5:Default */ >; - }; + }; + + ov5642: camera@3c { + compatible = "ovti,ov5642"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5642>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "xclk"; + reg = <0x3c>; + DOVDD-supply = <&vgen4_reg>; /* 1.8v */ + AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 + rev B board is VGEN5 */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + status = "disabled"; + + port { + ov5642_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <8>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; }; &i2c2 { @@ -222,6 +278,32 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + ov5640: camera@3c { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x3c>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "xclk"; + DOVDD-supply = <&vgen4_reg>; /* 1.8v */ + AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 + rev B board is VGEN5 */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + pmic: pfuze100@08 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -425,6 +507,36 @@ >; }; + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + >; + }; + + pinctrl_ov5640: ov5640grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 + >; + }; + + pinctrl_ov5642: ov5642grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 + >; + }; + pinctrl_pcie: pciegrp { fsl,pins = < MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 -- cgit v1.2.3 From 9976c92df9c347acd9726f5c187705f191d51999 Mon Sep 17 00:00:00 2001 From: Steve Longerbeam Date: Mon, 12 Jun 2017 11:24:01 -0700 Subject: ARM: dts: imx6-sabreauto: create i2cmux for i2c3 The sabreauto uses a steering pin to select between the SDA signal on i2c3 bus, and a data-in pin for an SPI NOR chip. Use i2cmux to control this steering pin. Idle state of the i2cmux selects SPI NOR. This is not a classic way to use i2cmux, since one side of the mux selects something other than an i2c bus, but it works and is probably the cleanest solution. Note that if one thread is attempting to access SPI NOR while another thread is accessing i2c3, the SPI NOR access will fail since the i2cmux has selected the SDA pin rather than SPI NOR data-in. This couldn't be avoided in any case, the board is not designed to allow concurrent i2c3 and SPI NOR functions (and the default device-tree does not enable SPI NOR anyway). Devices hanging off i2c3 should now be defined under i2cmux, so that the steering pin can be properly controlled to access those devices. The port expanders (MAX7310) are thus moved into i2cmux. Signed-off-by: Steve Longerbeam Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 65 +++++++++++++++++++++----------- 1 file changed, 44 insertions(+), 21 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index a2a714d199ea..c8e35c4e9d6a 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -108,6 +108,44 @@ default-brightness-level = <7>; status = "okay"; }; + + i2cmux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3mux>; + mux-gpios = <&gpio5 4 0>; + i2c-parent = <&i2c3>; + idle-state = <0>; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + max7310_a: gpio@30 { + compatible = "maxim,max7310"; + reg = <0x30>; + gpio-controller; + #gpio-cells = <2>; + }; + + max7310_b: gpio@32 { + compatible = "maxim,max7310"; + reg = <0x32>; + gpio-controller; + #gpio-cells = <2>; + }; + + max7310_c: gpio@34 { + compatible = "maxim,max7310"; + reg = <0x34>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; }; &clks { @@ -290,27 +328,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - - max7310_a: gpio@30 { - compatible = "maxim,max7310"; - reg = <0x30>; - gpio-controller; - #gpio-cells = <2>; - }; - - max7310_b: gpio@32 { - compatible = "maxim,max7310"; - reg = <0x32>; - gpio-controller; - #gpio-cells = <2>; - }; - - max7310_c: gpio@34 { - compatible = "maxim,max7310"; - reg = <0x34>; - gpio-controller; - #gpio-cells = <2>; - }; }; &iomuxc { @@ -418,6 +435,12 @@ >; }; + pinctrl_i2c3mux: i2c3muxgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1 + >; + }; + pinctrl_pwm3: pwm1grp { fsl,pins = < MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 -- cgit v1.2.3 From f9f1353b7508d133e4359f703ec06827dd0be26e Mon Sep 17 00:00:00 2001 From: Steve Longerbeam Date: Mon, 12 Jun 2017 11:24:02 -0700 Subject: ARM: dts: imx6-sabreauto: add reset-gpios property for max7310_b The reset pin to the port expander chip (MAX7310) is controlled by a gpio, so define a reset-gpios property to control it. There are three MAX7310's on the SabreAuto CPU card (max7310_[abc]), but all use the same pin for their reset. Since all can't acquire the same pin, assign it to max7310_b, that chip is needed by more functions (usb and adv7180). Signed-off-by: Steve Longerbeam Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index c8e35c4e9d6a..21dea5f50a37 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -136,6 +136,9 @@ reg = <0x32>; gpio-controller; #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max7310>; + reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; max7310_c: gpio@34 { @@ -441,6 +444,12 @@ >; }; + pinctrl_max7310: max7310grp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 + >; + }; + pinctrl_pwm3: pwm1grp { fsl,pins = < MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 -- cgit v1.2.3 From ba4105401a893c429a2542f3f33bb7fb813dd5c9 Mon Sep 17 00:00:00 2001 From: Steve Longerbeam Date: Mon, 12 Jun 2017 11:24:03 -0700 Subject: ARM: dts: imx6-sabreauto: add pinctrl for gpt input capture Add pinctrl groups for both GPT input capture channels. Signed-off-by: Steve Longerbeam Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 21dea5f50a37..1212f822c44f 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -456,6 +456,18 @@ >; }; + pinctrl_gpt_input_capture0: gptinputcapture0grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0 + >; + }; + + pinctrl_gpt_input_capture1: gptinputcapture1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0 + >; + }; + pinctrl_spdif: spdifgrp { fsl,pins = < MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 -- cgit v1.2.3 From ad8046a56da562677f41ca3a6d1a93619dbb0f97 Mon Sep 17 00:00:00 2001 From: Steve Longerbeam Date: Mon, 12 Jun 2017 11:24:04 -0700 Subject: ARM: dts: imx6-sabreauto: add the ADV7180 video decoder Enables the ADV7180 decoder sensor. The ADV7180 connects to the parallel-bus mux input on ipu1_csi0_mux. The ADV7180 power pin is via max7310_b port expander. Changes from Tim Harvey: - Use IRQ_TYPE_LEVEL_LOW instead of 0x8 for interrupt type for clarity. - For 8-bit parallel IPU1-CSI0 bus connection only data[12-19] are used. Signed-off-by: Steve Longerbeam Signed-off-by: Tim Harvey Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 45 ++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 1212f822c44f..6a7594e5d183 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -124,6 +124,21 @@ #size-cells = <0>; reg = <1>; + adv7180: camera@21 { + compatible = "adi,adv7180"; + reg = <0x21>; + powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio1>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + port { + adv7180_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <8>; + }; + }; + }; + max7310_a: gpio@30 { compatible = "maxim,max7310"; reg = <0x30>; @@ -151,6 +166,20 @@ }; }; +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <8>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; + bus-width = <8>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; +}; + &clks { assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>, <&clks IMX6QDL_PLL4_BYPASS>, @@ -444,6 +473,22 @@ >; }; + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + >; + }; + pinctrl_max7310: max7310grp { fsl,pins = < MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 -- cgit v1.2.3 From 0e9d528f0702ee07216a7f1d2a55cee0b23a3bba Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Wed, 7 Jun 2017 19:33:44 +0200 Subject: ARM: sun8i: a83t: Add dt node for the syscon control module This patch add the dt node for the syscon register present on the Allwinner A83T Signed-off-by: Corentin Labbe Reviewed-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index bf63e3b77572..8923ba625b76 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -165,6 +165,12 @@ #size-cells = <1>; ranges; + syscon: syscon@1c00000 { + compatible = "allwinner,sun8i-a83t-system-controller", + "syscon"; + reg = <0x01c00000 0x1000>; + }; + dma: dma-controller@1c02000 { compatible = "allwinner,sun8i-a83t-dma"; reg = <0x01c02000 0x1000>; -- cgit v1.2.3 From 723ca929a507a05bf4638f620b284f25d2047cf3 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 10 Jun 2017 00:05:48 +0800 Subject: ARM: sun6i: a31s: primo81: Change USB OTG to OTG mode Now that we have support for the AXP221 PMIC's USB VBUS detection and DRIVEVBUS vbus control, we can use the USB OTG port in proper OTG mode. This patch enables the aforementioned PMIC functions, adds the OTG ID detection pin to the USB PHY node, and changes the mode of USB OTG to "otg". Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31s-primo81.dts | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts index f3712753fa42..73b163a7d9dd 100644 --- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts +++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts @@ -158,6 +158,7 @@ reg = <0x68>; interrupt-parent = <&nmi_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + x-powers,drive-vbus-en; }; }; @@ -226,6 +227,11 @@ regulator-name = "vddio-csi"; }; +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + ®_eldo3 { regulator-min-microvolt = <1080000>; regulator-max-microvolt = <1320000>; @@ -238,12 +244,18 @@ }; &usb_otg { - /* otg support requires support for AXP221 usb-power-supply and GPIO */ - dr_mode = "host"; + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { status = "okay"; }; &usbphy { + usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; usb1_vbus-supply = <®_dldo1>; status = "okay"; }; -- cgit v1.2.3 From d5e9edfd37fc32098349b7753637bc1c80a16003 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 10 Jun 2017 00:05:49 +0800 Subject: ARM: sun6i: a31s: primo81: Enable battery power supply The MSI Primo81 tablet has a 3500 mAh 3.7V LiPo battery. Enable the PMIC's battery power supply so the battery can be monitored. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31s-primo81.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts index 73b163a7d9dd..4c10123509c4 100644 --- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts +++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts @@ -164,6 +164,10 @@ #include "axp22x.dtsi" +&battery_power_supply { + status = "okay"; +}; + ®_aldo3 { regulator-always-on; regulator-min-microvolt = <2700000>; -- cgit v1.2.3 From 9b00064ba7d6fcc3bb0b50b790a0178f8d9cc91f Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Thu, 8 Jun 2017 19:26:57 +0300 Subject: ARM: imx_v6_v7_defconfig: Set THERMAL_WRITABLE_TRIPS=y for testing Setting trip points is supported by the imx thermal driver and it is useful to be able to test this without adjusting config. Signed-off-by: Leonard Crestez Signed-off-by: Shawn Guo --- arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 51ca814f38fd..2dbbc52d4efa 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -207,6 +207,7 @@ CONFIG_POWER_SUPPLY=y CONFIG_SENSORS_GPIO_FAN=y CONFIG_SENSORS_IIO_HWMON=y CONFIG_THERMAL=y +CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_CPU_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_WATCHDOG=y -- cgit v1.2.3 From b6f5e70193913361d3378f9f2bb401d3d7228f34 Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Fri, 9 Jun 2017 14:25:45 +0800 Subject: ARM: dts: ls1021a: update the clockgen node qoriq clock driver has been updated to parse the clock configuration information defined in driver itself not in dts. Since the new implementation and the bindings have been merged, it is time to update the clock related node and remove redundent clock configuration information from the dts. Signed-off-by: Tang Yuantian Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 90 ++++++++++++++++-------------------------- 1 file changed, 33 insertions(+), 57 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 45ea57fafa18..7bb9df2c1460 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -75,7 +75,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0xf00>; - clocks = <&cluster1_clk>; + clocks = <&clockgen 1 0>; #cooling-cells = <2>; }; @@ -83,10 +83,17 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0xf01>; - clocks = <&cluster1_clk>; + clocks = <&clockgen 1 0>; }; }; + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + timer { compatible = "arm,armv7-timer"; interrupts = , @@ -165,7 +172,7 @@ <0x0 0x20220520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; dma-coherent; status = "disabled"; }; @@ -216,41 +223,10 @@ }; clockgen: clocking@1ee1000 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1ee1000 0x10000>; - - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "sysclk"; - }; - - cga_pll1: pll@800 { - compatible = "fsl,qoriq-core-pll-2.0"; - #clock-cells = <1>; - reg = <0x800 0x10>; - clocks = <&sysclk>; - clock-output-names = "cga-pll1", "cga-pll1-div2", - "cga-pll1-div4"; - }; - - platform_clk: pll@c00 { - compatible = "fsl,qoriq-core-pll-2.0"; - #clock-cells = <1>; - reg = <0xc00 0x10>; - clocks = <&sysclk>; - clock-output-names = "platform-clk", "platform-clk-div2"; - }; - - cluster1_clk: clk0c0@0 { - compatible = "fsl,qoriq-core-mux-2.0"; - #clock-cells = <0>; - reg = <0x0 0x10>; - clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4"; - clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>; - clock-output-names = "cluster1-clk"; - }; + compatible = "fsl,ls1021a-clockgen"; + reg = <0x0 0x1ee1000 0x0 0x1000>; + #clock-cells = <2>; + clocks = <&sysclk>; }; tmu: tmu@1f00000 { @@ -338,7 +314,7 @@ reg = <0x0 0x2100000 0x0 0x10000>; interrupts = ; clock-names = "dspi"; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; spi-num-chipselects = <6>; big-endian; status = "disabled"; @@ -351,7 +327,7 @@ reg = <0x0 0x2110000 0x0 0x10000>; interrupts = ; clock-names = "dspi"; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; spi-num-chipselects = <6>; big-endian; status = "disabled"; @@ -364,7 +340,7 @@ reg = <0x0 0x2180000 0x0 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; status = "disabled"; }; @@ -375,7 +351,7 @@ reg = <0x0 0x2190000 0x0 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; status = "disabled"; }; @@ -386,7 +362,7 @@ reg = <0x0 0x21a0000 0x0 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; status = "disabled"; }; @@ -479,7 +455,7 @@ compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2960000 0x0 0x1000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; @@ -488,7 +464,7 @@ compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2970000 0x0 0x1000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; @@ -497,7 +473,7 @@ compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2980000 0x0 0x1000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; @@ -506,7 +482,7 @@ compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2990000 0x0 0x1000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; @@ -515,7 +491,7 @@ compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x29a0000 0x0 0x1000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; @@ -524,7 +500,7 @@ compatible = "fsl,imx21-wdt"; reg = <0x0 0x2ad0000 0x0 0x10000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "wdog-en"; big-endian; }; @@ -534,8 +510,8 @@ compatible = "fsl,vf610-sai"; reg = <0x0 0x2b50000 0x0 0x10000>; interrupts = ; - clocks = <&platform_clk 1>, <&platform_clk 1>, - <&platform_clk 1>, <&platform_clk 1>; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 47>, @@ -548,8 +524,8 @@ compatible = "fsl,vf610-sai"; reg = <0x0 0x2b60000 0x0 0x10000>; interrupts = ; - clocks = <&platform_clk 1>, <&platform_clk 1>, - <&platform_clk 1>, <&platform_clk 1>; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 45>, @@ -569,16 +545,16 @@ dma-channels = <32>; big-endian; clock-names = "dmamux0", "dmamux1"; - clocks = <&platform_clk 1>, - <&platform_clk 1>; + clocks = <&clockgen 4 1>, + <&clockgen 4 1>; }; dcu: dcu@2ce0000 { compatible = "fsl,ls1021a-dcu"; reg = <0x0 0x2ce0000 0x0 0x10000>; interrupts = ; - clocks = <&platform_clk 0>, - <&platform_clk 0>; + clocks = <&clockgen 4 0>, + <&clockgen 4 0>; clock-names = "dcu", "pix"; big-endian; status = "disabled"; -- cgit v1.2.3 From d5f7b828ffab28e5684913e76697e94e2442d164 Mon Sep 17 00:00:00 2001 From: Arvind Yadav Date: Thu, 15 Jun 2017 14:55:37 +0530 Subject: arm: perf: make of_device_ids const of_device_ids are not supposed to change at runtime. All functions working with of_device_ids provided by work with const of_device_ids. So mark the non-const structs as const. Signed-off-by: Arvind Yadav Signed-off-by: Will Deacon --- arch/arm/kernel/perf_event_v6.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c index 96b7a477a8db..8226d0b71fd3 100644 --- a/arch/arm/kernel/perf_event_v6.c +++ b/arch/arm/kernel/perf_event_v6.c @@ -552,7 +552,7 @@ static int armv6mpcore_pmu_init(struct arm_pmu *cpu_pmu) return 0; } -static struct of_device_id armv6_pmu_of_device_ids[] = { +static const struct of_device_id armv6_pmu_of_device_ids[] = { {.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init}, {.compatible = "arm,arm1176-pmu", .data = armv6_1176_pmu_init}, {.compatible = "arm,arm1136-pmu", .data = armv6_1136_pmu_init}, -- cgit v1.2.3 From 82d1afbce1e021819b913d9f6a314c3b12b56ed8 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Tue, 13 Jun 2017 15:47:06 +0200 Subject: ARM: dts: exynos: add needs-hpd to &hdmicec for Odroid-U3 The Odroid-U3 board has an IP4791CZ12 level shifter that is disabled if the HPD is low, which means that the CEC pin is disabled as well. Signed-off-by: Hans Verkuil Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-odroidu3.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index 7504a5aa538e..44a4de08466b 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -78,6 +78,10 @@ regulator-max-microvolt = <3300000>; }; +&hdmicec { + needs-hpd; +}; + /* VDDQ for MSHC (eMMC card) */ &ldo22_reg { regulator-name = "LDO22_VDDQ_MMC4_2.8V"; -- cgit v1.2.3 From 231ce279e6e37960f8c61d99f86e4937733ed96b Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Fri, 9 Jun 2017 10:21:10 -0700 Subject: ARM: davinci: fix const warnings After VPIF was converted to enable getting subdevs from DT, the pdata is no longer const, so remove these to avoid compiler warnings. Signed-off-by: Kevin Hilman [nsekhar@ti.com: minor commit message fixup] Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/board-dm646x-evm.c | 4 ++-- arch/arm/mach-davinci/pdata-quirks.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index cb176826d1cb..055e947a6a39 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -641,7 +641,7 @@ static struct vpif_subdev_info vpif_capture_sdev_info[] = { }, }; -static const struct vpif_input dm6467_ch0_inputs[] = { +static struct vpif_input dm6467_ch0_inputs[] = { { .input = { .index = 0, @@ -656,7 +656,7 @@ static const struct vpif_input dm6467_ch0_inputs[] = { }, }; -static const struct vpif_input dm6467_ch1_inputs[] = { +static struct vpif_input dm6467_ch1_inputs[] = { { .input = { .index = 0, diff --git a/arch/arm/mach-davinci/pdata-quirks.c b/arch/arm/mach-davinci/pdata-quirks.c index 329f5402ad1d..4858b1cdf31b 100644 --- a/arch/arm/mach-davinci/pdata-quirks.c +++ b/arch/arm/mach-davinci/pdata-quirks.c @@ -33,7 +33,7 @@ static struct tvp514x_platform_data tvp5146_pdata = { #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) -static const struct vpif_input da850_ch0_inputs[] = { +static struct vpif_input da850_ch0_inputs[] = { { .input = { .index = 0, @@ -48,7 +48,7 @@ static const struct vpif_input da850_ch0_inputs[] = { }, }; -static const struct vpif_input da850_ch1_inputs[] = { +static struct vpif_input da850_ch1_inputs[] = { { .input = { .index = 0, -- cgit v1.2.3 From 9e4ffee82249ab8b289cd888071676af9b5477ca Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Thu, 8 Jun 2017 20:07:32 +0530 Subject: ARM: davinci_all_defconfig: enable mtdtests mtdtests module has some useful tests to verify that mtd drivers like davinci_nand are working correctly. Enable it in davinci_all_defconfig to make testing and debug easier. Signed-off-by: Sekhar Nori --- arch/arm/configs/davinci_all_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index 7f726277dd1b..1f1b4a795dc6 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig @@ -58,6 +58,7 @@ CONFIG_DEVTMPFS_MOUNT=y # CONFIG_FW_LOADER is not set CONFIG_DA8XX_MSTPRI=y CONFIG_MTD=m +CONFIG_MTD_TESTS=m CONFIG_MTD_BLOCK=m CONFIG_MTD_CFI=m CONFIG_MTD_CFI_INTELEXT=m -- cgit v1.2.3 From 82cc56ccf127899cde1d74a0380c29814ceb1b71 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Thu, 8 Jun 2017 20:07:33 +0530 Subject: ARM: davinci_all_defconfig: enable USB CDC NCM gadget Enable USB CDC NCM gadget module in davinci_all_defconfig to make it easier to use it on these devices. Signed-off-by: Sekhar Nori --- arch/arm/configs/davinci_all_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index 1f1b4a795dc6..06e2e2a1a9be 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig @@ -186,6 +186,7 @@ CONFIG_USB_GADGET_DEBUG_FILES=y CONFIG_USB_GADGET_DEBUG_FS=y CONFIG_USB_ZERO=m CONFIG_USB_ETH=m +CONFIG_USB_G_NCM=m CONFIG_USB_GADGETFS=m CONFIG_USB_MASS_STORAGE=m CONFIG_USB_G_SERIAL=m -- cgit v1.2.3 From bc8ebb86392dc2e81abee68c4e569f8d23628603 Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Thu, 15 Jun 2017 19:03:29 +0900 Subject: ARM: dts: exynos: Fix polarity of panel reset gpio in Rinato This reset gpio is active low, therefore fix from active high to low. Signed-off-by: Hoegeun Kwon Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250-rinato.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 118235b72e90..443e0c98dc73 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -240,7 +240,7 @@ reg = <0>; vdd3-supply = <&ldo16_reg>; vci-supply = <&ldo20_reg>; - reset-gpios = <&gpe0 1 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpe0 1 GPIO_ACTIVE_LOW>; te-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>; power-on-delay= <30>; power-off-delay= <120>; -- cgit v1.2.3 From 79eb80b70c4e05defb4d6f6e68840a052e73ae2d Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 10 Jun 2017 00:20:39 +0200 Subject: ARM: dts: meson8: fix the IR receiver pins The IR receiver pins are currently defined in the CBUS pin-controller. However the pins are in the AO region, which is controlled by the AOBUS pin-controller. Move the pins to pinctrl_aobus so they can actually be used. Fixes: b60e1157d8fa ("ARM: dts: amlogic: Split pinctrl device for Meson8 / Meson8b") Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 9b0b3ddbb17e..e4f7357b4b31 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -116,6 +116,13 @@ function = "i2c_mst_ao"; }; }; + + ir_recv_pins: remote { + mux { + groups = "remote_input"; + function = "remote"; + }; + }; }; }; @@ -151,13 +158,6 @@ }; }; - ir_recv_pins: remote { - mux { - groups = "remote_input"; - function = "remote"; - }; - }; - eth_pins: ethernet { mux { groups = "eth_tx_clk_50m", "eth_tx_en", -- cgit v1.2.3 From 7a16f06b90ab73343af982ded3ac2710259c37aa Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Thu, 15 Jun 2017 23:33:43 +0200 Subject: ARM: dts: meson: use C preprocessor friendly include syntax This replaces the "/include/" syntax with the "#include" syntax in all Amlogic Meson .dts and .dtsi files. That is required to use preprocessor defines (like GIC_SPI and IRQ_TYPE_EDGE_RISING) in meson.dtsi (all files which directly or indirectly include meson.dtsi need to use the "#include" syntax, otherwise the .dts files cannot be compiled). Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson6-atv1200.dts | 2 +- arch/arm/boot/dts/meson6.dtsi | 2 +- arch/arm/boot/dts/meson8.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts index 1237faa63ce6..9444b0d9628f 100644 --- a/arch/arm/boot/dts/meson6-atv1200.dts +++ b/arch/arm/boot/dts/meson6-atv1200.dts @@ -46,7 +46,7 @@ */ /dts-v1/; -/include/ "meson6.dtsi" +#include "meson6.dtsi" / { model = "Geniatech ATV1200"; diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi index b0fc91ffd6a1..8557b6117a4b 100644 --- a/arch/arm/boot/dts/meson6.dtsi +++ b/arch/arm/boot/dts/meson6.dtsi @@ -45,7 +45,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/include/ "meson.dtsi" +#include "meson.dtsi" / { model = "Amlogic Meson6 SoC"; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index e4f7357b4b31..c5d73b999773 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -45,7 +45,7 @@ #include #include -/include/ "meson.dtsi" +#include "meson.dtsi" / { model = "Amlogic Meson8 SoC"; -- cgit v1.2.3 From 5239e0504826d4b2ca7c225cc32d1a1a9e755453 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Thu, 15 Jun 2017 23:33:44 +0200 Subject: ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson.dtsi | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index 8d9c36970dfd..d287f606e06f 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -45,6 +45,8 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include +#include /include/ "skeleton.dtsi" / { @@ -81,21 +83,21 @@ uart_A: serial@84c0 { compatible = "amlogic,meson-uart"; reg = <0x84c0 0x18>; - interrupts = <0 26 1>; + interrupts = ; status = "disabled"; }; uart_B: serial@84dc { compatible = "amlogic,meson-uart"; reg = <0x84dc 0x18>; - interrupts = <0 75 1>; + interrupts = ; status = "disabled"; }; i2c_A: i2c@8500 { compatible = "amlogic,meson6-i2c"; reg = <0x8500 0x20>; - interrupts = <0 21 1>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -104,14 +106,14 @@ uart_C: serial@8700 { compatible = "amlogic,meson-uart"; reg = <0x8700 0x18>; - interrupts = <0 93 1>; + interrupts = ; status = "disabled"; }; i2c_B: i2c@87c0 { compatible = "amlogic,meson6-i2c"; reg = <0x87c0 0x20>; - interrupts = <0 128 1>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -128,13 +130,13 @@ wdt: watchdog@9900 { compatible = "amlogic,meson6-wdt"; reg = <0x9900 0x8>; - interrupts = <0 0 1>; + interrupts = ; }; timer@9940 { compatible = "amlogic,meson6-timer"; reg = <0x9940 0x18>; - interrupts = <0 10 1>; + interrupts = ; }; }; @@ -148,21 +150,21 @@ ir_receiver: ir-receiver@480 { compatible= "amlogic,meson6-ir"; reg = <0x480 0x20>; - interrupts = <0 15 1>; + interrupts = ; status = "disabled"; }; uart_AO: serial@4c0 { compatible = "amlogic,meson-uart"; reg = <0x4c0 0x18>; - interrupts = <0 90 1>; + interrupts = ; status = "disabled"; }; i2c_AO: i2c@500 { compatible = "amlogic,meson6-i2c"; reg = <0x500 0x20>; - interrupts = <0 92 1>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -173,7 +175,7 @@ compatible = "amlogic,meson6-dwmac", "snps,dwmac"; reg = <0xc9410000 0x10000 0xc1108108 0x4>; - interrupts = <0 8 1>; + interrupts = ; interrupt-names = "macirq"; status = "disabled"; }; -- cgit v1.2.3 From 192ec775f5b1530b4394de6236aa72f1dc69422e Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Thu, 15 Jun 2017 23:33:45 +0200 Subject: ARM: dts: meson8: add the PWM_E and PWM_F pins This adds the definition of the PWM_E (CBUS) and PWM_F (AOBUS) to meson8.dtsi, allowing devices to use them. PWM_E can be used on some devices to generate the 32.768kHz clock for the SDIO wifi module, while PWM_F can be used to control the power LED. Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index c5d73b999773..5ff7903964c6 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -123,6 +123,13 @@ function = "remote"; }; }; + + pwm_f_ao_pins: pwm-f-ao { + mux { + groups = "pwm_f_ao"; + function = "pwm_f_ao"; + }; + }; }; }; @@ -168,6 +175,13 @@ function = "ethernet"; }; }; + + pwm_e_pins: pwm-e { + mux { + groups = "pwm_e"; + function = "pwm_e"; + }; + }; }; }; -- cgit v1.2.3 From d42ce5a98dcd7ffc59699127d0597c17859f347d Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Thu, 15 Jun 2017 23:33:46 +0200 Subject: ARM: dts: meson8: add the pins for the SDIO controller Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 5ff7903964c6..bb3608bddc98 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -158,6 +158,30 @@ gpio-ranges = <&pinctrl_cbus 0 0 120>; }; + sd_a_pins: sd-a { + mux { + groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", + "sd_d3_a", "sd_clk_a", "sd_cmd_a"; + function = "sd_a"; + }; + }; + + sd_b_pins: sd-b { + mux { + groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", + "sd_d3_b", "sd_clk_b", "sd_cmd_b"; + function = "sd_b"; + }; + }; + + sd_c_pins: sd-c { + mux { + groups = "sd_d0_c", "sd_d1_c", "sd_d2_c", + "sd_d3_c", "sd_clk_c", "sd_cmd_c"; + function = "sd_c"; + }; + }; + spi_nor_pins: nor { mux { groups = "nor_d", "nor_q", "nor_c", "nor_cs"; -- cgit v1.2.3 From a39a3b9f4ff0aba7c2c475afaa52a3eb52d2b9ad Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Thu, 15 Jun 2017 23:33:47 +0200 Subject: ARM: dts: meson: add the SAR ADC This adds the SAR ADC to meson.dtsi and configures the clocks on Meson8 and Meson8b to allow boards to use it. Some boards use it to connect a button to it. Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson.dtsi | 8 ++++++++ arch/arm/boot/dts/meson8.dtsi | 8 ++++++++ arch/arm/boot/dts/meson8b.dtsi | 8 ++++++++ 3 files changed, 24 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index d287f606e06f..46706d74a145 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -103,6 +103,14 @@ status = "disabled"; }; + saradc: adc@8680 { + compatible = "amlogic,meson-saradc"; + reg = <0x8680 0x34>; + #io-channel-cells = <1>; + interrupts = ; + status = "disabled"; + }; + uart_C: serial@8700 { compatible = "amlogic,meson-uart"; reg = <0x8700 0x18>; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index bb3608bddc98..6687b1b4c7c9 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -232,6 +232,14 @@ arm,filter-ranges = <0x100000 0xc0000000>; }; +&saradc { + compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; + clocks = <&clkc CLKID_XTAL>, + <&clkc CLKID_SAR_ADC>, + <&clkc CLKID_SANA>; + clock-names = "clkin", "core", "sana"; +}; + &spifc { clocks = <&clkc CLKID_CLK81>; }; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index d9f116a418b2..1c09090ff4a5 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -177,6 +177,14 @@ arm,filter-ranges = <0x100000 0xc0000000>; }; +&saradc { + compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc"; + clocks = <&clkc CLKID_XTAL>, + <&clkc CLKID_SAR_ADC>, + <&clkc CLKID_SANA>; + clock-names = "clkin", "core", "sana"; +}; + &uart_AO { clocks = <&clkc CLKID_CLK81>; }; -- cgit v1.2.3 From 8a7f0c52e8a07ac31784a2dd62c001d38843dfe6 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Thu, 15 Jun 2017 23:33:48 +0200 Subject: ARM: dts: meson8: add reserved memory zones There seem to be two memory regions that need to be reserved, otherwise the system just hangs when running: $ stress --vm-bytes $(awk '/MemFree/{printf "%d\n", $2 * 0.9;}' < /proc/meminfo)k \ --vm-keep -m 1 The first memory region is really crucial and without it the system hangs. I could not find any references to this in Amlogic's GPL kernel sources. The second region is used by the "suspend firmware". The u-boot sources (/arch/arm/cpu/aml_meson/m8/firmwareld.c) state that the suspend firmware is located at "64M + 15M" which matches CONFIG_MESON_SUSPEND in the Amlogic GPL kernel sources. The "suspend firmware" is responsible for waking up the system from suspend state. This also fixes reading the full SD card as without this the system would simply hang (probably related to the first memory region, if some buffer is allocated there). Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 6687b1b4c7c9..df79a34a3530 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -83,6 +83,33 @@ reg = <0x203>; }; }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* 2 MiB reserved for Hardware ROM Firmware? */ + hwrom@0 { + reg = <0x0 0x200000>; + no-map; + }; + + /* + * 1 MiB reserved for the "ARM Power Firmware": this is ARM + * code which is responsible for system suspend. It loads a + * piece of ARC code ("arc_power" in the vendor u-boot tree) + * into SRAM, executes that and shuts down the (last) ARM core. + * The arc_power firmware then checks various wakeup sources + * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or + * simply the power key) and re-starts the ARM core once it + * detects a wakeup request. + */ + power-firmware@4f00000 { + reg = <0x4f00000 0x100000>; + no-map; + }; + }; }; /* end of / */ &aobus { -- cgit v1.2.3 From a35910d3994a6d1f59b140dea6b00b8a7b134878 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Thu, 15 Jun 2017 23:33:49 +0200 Subject: ARM: dts: meson: add the hardware random number generator All supported Meson SoCs have a random number generator in CBUS. Newer SoCs (GXBB, GXL and GXM) provide only one 32-bit random number register, whereas the older SoCs (Meson6, Meson8 and Meson8b) have two 32-bit random number registers. The existing meson-rng driver only supports the lower 32-bit - but it still works fine on the older SoCs apart from this small limitation. Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson.dtsi | 5 +++++ arch/arm/boot/dts/meson8.dtsi | 6 ++++++ arch/arm/boot/dts/meson8b.dtsi | 6 ++++++ 3 files changed, 17 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index 46706d74a145..bf37606ba82e 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -80,6 +80,11 @@ #size-cells = <1>; ranges = <0x0 0xc1100000 0x200000>; + hwrng: rng@8100 { + compatible = "amlogic,meson-rng"; + reg = <0x8100 0x8>; + }; + uart_A: serial@84c0 { compatible = "amlogic,meson-uart"; reg = <0x84c0 0x18>; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index df79a34a3530..b4c5fdd7b451 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -241,6 +241,12 @@ clock-names = "stmmaceth"; }; +&hwrng { + compatible = "amlogic,meson8-rng", "amlogic,meson-rng"; + clocks = <&clkc CLKID_RNG0>; + clock-names = "core"; +}; + &i2c_AO { clocks = <&clkc CLKID_CLK81>; }; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 1c09090ff4a5..a9d7074e6369 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -171,6 +171,12 @@ }; }; +&hwrng { + compatible = "amlogic,meson8b-rng", "amlogic,meson-rng"; + clocks = <&clkc CLKID_RNG0>; + clock-names = "core"; +}; + &L2 { arm,data-latency = <3 3 3>; arm,tag-latency = <2 2 2>; -- cgit v1.2.3 From e29b1cf87473811584c8cf02d624954d7784fa5a Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Thu, 15 Jun 2017 23:33:50 +0200 Subject: ARM: dts: meson: add USB support on Meson8 and Meson8b This adds the DWC2 USB controller nodes and the corresponding USB2 PHY nodes to meson.dtsi (as the same - or at least a very similar) IP block is used on all SoCs (at the same physical address). Additionally meson8.dtsi and meson8b.dtsi add the required clocks to the DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be initialized by the dwc2 driver. Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson.dtsi | 38 ++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/meson8.dtsi | 24 ++++++++++++++++++++++++ arch/arm/boot/dts/meson8b.dtsi | 26 ++++++++++++++++++++++++++ 3 files changed, 88 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index bf37606ba82e..15204e44161d 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -132,6 +132,20 @@ status = "disabled"; }; + usb0_phy: phy@8800 { + compatible = "amlogic,meson-mx-usb2-phy"; + #phy-cells = <0>; + reg = <0x8800 0x20>; + status = "disabled"; + }; + + usb1_phy: phy@8820 { + compatible = "amlogic,meson-mx-usb2-phy"; + #phy-cells = <0>; + reg = <0x8820 0x20>; + status = "disabled"; + }; + spifc: spi@8c80 { compatible = "amlogic,meson6-spifc"; reg = <0x8c80 0x80>; @@ -184,6 +198,30 @@ }; }; + usb0: usb@c9040000 { + compatible = "snps,dwc2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc9040000 0x40000>; + interrupts = ; + phys = <&usb0_phy>; + phy-names = "usb2-phy"; + dr_mode = "host"; + status = "disabled"; + }; + + usb1: usb@c90c0000 { + compatible = "snps,dwc2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc90c0000 0x40000>; + interrupts = ; + phys = <&usb1_phy>; + phy-names = "usb2-phy"; + dr_mode = "host"; + status = "disabled"; + }; + ethmac: ethernet@c9410000 { compatible = "amlogic,meson6-dwmac", "snps,dwmac"; reg = <0xc9410000 0x10000 diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index b4c5fdd7b451..17a4c6255589 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -292,3 +292,27 @@ &uart_C { clocks = <&clkc CLKID_CLK81>; }; + +&usb0 { + compatible = "amlogic,meson8-usb", "snps,dwc2"; + clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; + clock-names = "otg"; +}; + +&usb1 { + compatible = "amlogic,meson8-usb", "snps,dwc2"; + clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; + clock-names = "otg"; +}; + +&usb0_phy { + compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; + clock-names = "usb_general", "usb"; +}; + +&usb1_phy { + compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; + clock-names = "usb_general", "usb"; +}; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index a9d7074e6369..521be5dfa8ef 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -206,3 +206,29 @@ &uart_C { clocks = <&clkc CLKID_CLK81>; }; + +&usb0 { + compatible = "amlogic,meson8b-usb", "snps,dwc2"; + clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; + clock-names = "otg"; +}; + +&usb1 { + compatible = "amlogic,meson8b-usb", "snps,dwc2"; + clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; + clock-names = "otg"; +}; + +&usb0_phy { + compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; + clock-names = "usb_general", "usb"; + resets = <&reset RESET_USB_OTG>; +}; + +&usb1_phy { + compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; + clock-names = "usb_general", "usb"; + resets = <&reset RESET_USB_OTG>; +}; -- cgit v1.2.3 From d8dd3d29d02cb04f37098b10ede5251764f06754 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Thu, 15 Jun 2017 23:33:51 +0200 Subject: ARM: dts: meson8b: add the SCU device node Amlogic's Meson8b SoC has a Snoop Control Unit (SCU), just like many other Cortex-A5 SoCs. Add the corresponding devicetree node so it can be used during SMP boot. Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 5 +++++ arch/arm/boot/dts/meson8b.dtsi | 5 +++++ 2 files changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 17a4c6255589..dfe83364eceb 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -110,6 +110,11 @@ no-map; }; }; + + scu@c4300000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xc4300000 0x100>; + }; }; /* end of / */ &aobus { diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 521be5dfa8ef..173b12a999e6 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -82,6 +82,11 @@ reg = <0x203>; }; }; + + scu@c4300000 { + compatible = "arm,cortex-a5-scu"; + reg = <0xc4300000 0x100>; + }; }; /* end of / */ &aobus { -- cgit v1.2.3 From f28d4bdb74b6fec482cdbba032369a185baa74b9 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Thu, 15 Jun 2017 23:33:52 +0200 Subject: ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b Until now clk81 was used as gate clock for the ethernet controller on Meson8 whereas Meson8b did not configure a gate clock at all. Use CLKID_ETH for both SoCs, which is the real gate clock for the ethernet controller. Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 2 +- arch/arm/boot/dts/meson8b.dtsi | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index dfe83364eceb..cada35828931 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -242,7 +242,7 @@ }; ðmac { - clocks = <&clkc CLKID_CLK81>; + clocks = <&clkc CLKID_ETH>; clock-names = "stmmaceth"; }; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 173b12a999e6..72e4f425f190 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -176,6 +176,11 @@ }; }; +ðmac { + clocks = <&clkc CLKID_ETH>; + clock-names = "stmmaceth"; +}; + &hwrng { compatible = "amlogic,meson8b-rng", "amlogic,meson-rng"; clocks = <&clkc CLKID_RNG0>; -- cgit v1.2.3 From 4cdcf1efcc2623c7a5358d38d71aecc8bed32b7e Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Fri, 14 Apr 2017 17:40:54 +0200 Subject: ARM: mvebu: Enable SENSORS_PWM_FAN in defconfig Now that the GPIO driver also supports PWM operation, enable the PWM framework and fan driver in mvebu_v7_defconfig. Signed-off-by: Andrew Lunn URL: https://patchwork.ozlabs.org/patch/427297/ [Ralph Sennhauser: add fan driver to defconfig] Signed-off-by: Ralph Sennhauser Tested-by: Andrew Lunn Acked-by: Linus Walleij Signed-off-by: Gregory CLEMENT --- arch/arm/configs/mvebu_v7_defconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig index f1a0e2503cbe..69553704f2dc 100644 --- a/arch/arm/configs/mvebu_v7_defconfig +++ b/arch/arm/configs/mvebu_v7_defconfig @@ -135,6 +135,8 @@ CONFIG_DMADEVICES=y CONFIG_MV_XOR=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_MEMORY=y +CONFIG_PWM=y +CONFIG_SENSORS_PWM_FAN=y CONFIG_EXT4_FS=y CONFIG_ISO9660_FS=y CONFIG_JOLIET=y -- cgit v1.2.3 From 0c8c9ff8ec8eb1b41817bd547895e360b66853d6 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Thu, 1 Jun 2017 22:09:26 +0200 Subject: ARM: dts: mvebu: Add PWM properties to .dtsi files Add properties to the GPIO nodes for Armada 370/XP to allow them to be also used as PWM lines. Signed-off-by: Andrew Lunn URL: https://patchwork.ozlabs.org/patch/427294/ [Ralph Sennhauser: Add new compatible string marvell,armada-370-gpio] Signed-off-by: Ralph Sennhauser Tested-by: Andrew Lunn Acked-by: Linus Walleij Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-370.dtsi | 19 ++++++++++++++----- arch/arm/boot/dts/armada-xp-mv78230.dtsi | 16 ++++++++++++---- arch/arm/boot/dts/armada-xp-mv78260.dtsi | 19 ++++++++++++++----- arch/arm/boot/dts/armada-xp-mv78460.dtsi | 19 ++++++++++++++----- 4 files changed, 54 insertions(+), 19 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index cc011c8bc36b..f9cf1273f35e 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -137,29 +137,38 @@ }; gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18100 0x40>, <0x181c0 0x08>; + reg-names = "gpio", "pwm"; ngpios = <32>; gpio-controller; #gpio-cells = <2>; + #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <82>, <83>, <84>, <85>; + clocks = <&coreclk 0>; }; gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18140 0x40>, <0x181c8 0x08>; + reg-names = "gpio", "pwm"; ngpios = <32>; gpio-controller; #gpio-cells = <2>; + #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <87>, <88>, <89>, <90>; + clocks = <&coreclk 0>; }; gpio2: gpio@18180 { - compatible = "marvell,orion-gpio"; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; reg = <0x18180 0x40>; ngpios = <2>; gpio-controller; diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index 07c5090ecd29..9f25814077f2 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -202,25 +202,33 @@ internal-regs { gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18100 0x40>, <0x181c0 0x08>; + reg-names = "gpio", "pwm"; ngpios = <32>; gpio-controller; #gpio-cells = <2>; + #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <82>, <83>, <84>, <85>; + clocks = <&coreclk 0>; }; gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18140 0x40>, <0x181c8 0x08>; + reg-names = "gpio", "pwm"; ngpios = <17>; gpio-controller; #gpio-cells = <2>; + #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <87>, <88>, <89>; + clocks = <&coreclk 0>; }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index 64e936ae7b22..2bfe07aebf1a 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -285,29 +285,38 @@ internal-regs { gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18100 0x40>, <0x181c0 0x08>; + reg-names = "gpio", "pwm"; ngpios = <32>; gpio-controller; #gpio-cells = <2>; + #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <82>, <83>, <84>, <85>; + clocks = <&coreclk 0>; }; gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18140 0x40>, <0x181c8 0x08>; + reg-names = "gpio", "pwm"; ngpios = <32>; gpio-controller; #gpio-cells = <2>; + #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <87>, <88>, <89>, <90>; + clocks = <&coreclk 0>; }; gpio2: gpio@18180 { - compatible = "marvell,orion-gpio"; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; reg = <0x18180 0x40>; ngpios = <3>; gpio-controller; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index d1383dde43eb..6c33935f7074 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -323,29 +323,38 @@ internal-regs { gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18100 0x40>, <0x181c0 0x08>; + reg-names = "gpio", "pwm"; ngpios = <32>; gpio-controller; #gpio-cells = <2>; + #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <82>, <83>, <84>, <85>; + clocks = <&coreclk 0>; }; gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18140 0x40>, <0x181c8 0x08>; + reg-names = "gpio", "pwm"; ngpios = <32>; gpio-controller; #gpio-cells = <2>; + #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <87>, <88>, <89>, <90>; + clocks = <&coreclk 0>; }; gpio2: gpio@18180 { - compatible = "marvell,orion-gpio"; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; reg = <0x18180 0x40>; ngpios = <3>; gpio-controller; -- cgit v1.2.3 From 7cb2acb3fbae5e499a619406a13fe856e3b0b07a Mon Sep 17 00:00:00 2001 From: Ralph Sennhauser Date: Thu, 1 Jun 2017 22:10:30 +0200 Subject: ARM: dts: mvebu: Add PWM properties for armada-38x Add the required properties to the GPIO nodes for them to be used as PWM lines. Signed-off-by: Ralph Sennhauser Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-38x.dtsi | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 8b165c31de1e..af31f5d6c0e5 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -312,31 +312,39 @@ }; gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18100 0x40>, <0x181c0 0x08>; + reg-names = "gpio", "pwm"; ngpios = <32>; gpio-controller; #gpio-cells = <2>; + #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = , , , ; + clocks = <&coreclk 0>; }; gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18140 0x40>, <0x181c8 0x08>; + reg-names = "gpio", "pwm"; ngpios = <28>; gpio-controller; #gpio-cells = <2>; + #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = , , , ; + clocks = <&coreclk 0>; }; systemc: system-controller@18200 { -- cgit v1.2.3 From 8035eaadefc69a8add75f1fecc8e63e36bab81ea Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Fri, 14 Apr 2017 17:40:55 +0200 Subject: ARM: dts: armada-xp: Use pwm-fan rather than gpio-fan The mvebu GPIO driver can also perform PWM on some pins. Use the pwm-fan driver to control the fan of the WRT1900AC, giving us finer grained control over its speed and hence noise. Signed-off-by: Andrew Lunn URL: https://patchwork.ozlabs.org/patch/427291/ [Ralph Sennhauser: drop flags paramter from pwms, no longer used] Signed-off-by: Ralph Sennhauser Tested-by: Andrew Lunn Acked-by: Linus Walleij Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts index 9efcf59c9b44..6d705f518254 100644 --- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts @@ -308,13 +308,11 @@ }; }; - gpio_fan { + pwm_fan { /* SUNON HA4010V4-0000-C99 */ - compatible = "gpio-fan"; - gpios = <&gpio0 24 0>; - gpio-fan,speed-map = <0 0 - 4500 1>; + compatible = "pwm-fan"; + pwms = <&gpio0 24 4000>; }; dsa { -- cgit v1.2.3 From 948e7d98e666fe8bfca5102d813053553e9866a6 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 21 Apr 2017 09:58:13 +1200 Subject: ARM: dts: mvebu: add missing interrupt to 98dx4251 switch The 98dx4251 has 4 interrupts for the packet processor whereas the 98dx3236 and 98dx3336 only have 3. Signed-off-by: Chris Packham Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi index 51de91b31a9d..bc9f824020eb 100644 --- a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi +++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi @@ -87,4 +87,5 @@ &pp0 { compatible = "marvell,prestera-98dx4251"; + interrupts = <33>, <34>, <35>, <36>; }; -- cgit v1.2.3 From 3bef2ac4bda818be598e6d1084750015d26edac9 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 21 Apr 2017 09:58:14 +1200 Subject: ARM: dts: mvebu: disable the rtc on 98dx3236 SoC There is no rtc for the 98dx3236 and derivative SoCs. Disable the rtc node inherited from the armada-370-xp base. Signed-off-by: Chris Packham Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi index 84cc232a29e9..be22ec5236ac 100644 --- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi @@ -311,6 +311,10 @@ reg = <0x20a00 0x2d0>, <0x21070 0x58>; }; +&rtc { + status = "disabled"; +}; + &timer { compatible = "marvell,armada-xp-timer"; clocks = <&coreclk 2>, <&refclk>; -- cgit v1.2.3 From a90c9eaefbe732c33a441fdc99352a7ddf3bf355 Mon Sep 17 00:00:00 2001 From: Ralph Sennhauser Date: Sun, 21 May 2017 14:48:50 +0200 Subject: ARM: dts: armada-385-linksys: flatten dtsi Since the addition of the spi reference two styles are used. Use references instead of recreating the same structure over and over again. This helps to distinguish which are changes to the underlying nodes and which are new additions and helps maintainability in general. Verified the resulting dtb to be binary identical. Signed-off-by: Ralph Sennhauser Signed-off-by: Imre Kaloz Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-linksys.dtsi | 414 +++++++++++++++--------------- 1 file changed, 206 insertions(+), 208 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi index 2306c45685b1..481e4a36e26b 100644 --- a/arch/arm/boot/dts/armada-385-linksys.dtsi +++ b/arch/arm/boot/dts/armada-385-linksys.dtsi @@ -61,214 +61,6 @@ MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>; - - internal-regs { - i2c@11000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - tmp421@4c { - compatible = "ti,tmp421"; - reg = <0x4c>; - }; - - pca9635@68 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nxp,pca9635"; - reg = <0x68>; - }; - }; - - /* J10: VCC, NC, RX, NC, TX, GND */ - serial@12000 { - status = "okay"; - }; - - ethernet@70000 { - status = "okay"; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - bm,pool-short = <3>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - ethernet@34000 { - status = "okay"; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <1>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - mdio@72004 { - status = "okay"; - - switch@0 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan4"; - }; - - port@1 { - reg = <1>; - label = "lan3"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <ð2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - }; - - sata@a8000 { - status = "okay"; - }; - - bm@c8000 { - status = "okay"; - }; - - /* USB part of the eSATA/USB 2.0 port */ - usb@58000 { - status = "okay"; - }; - - usb3@f8000 { - status = "okay"; - usb-phy = <&usb3_phy>; - }; - - flash@d0000 { - status = "okay"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x200000>; /* 2MB */ - read-only; - }; - - partition@100000 { - label = "u_env"; - reg = <0x200000 0x40000>; /* 256KB */ - }; - - partition@140000 { - label = "s_env"; - reg = <0x240000 0x40000>; /* 256KB */ - }; - - partition@900000 { - label = "devinfo"; - reg = <0x900000 0x100000>; /* 1MB */ - read-only; - }; - - /* kernel1 overlaps with rootfs1 by design */ - partition@a00000 { - label = "kernel1"; - reg = <0xa00000 0x2800000>; /* 40MB */ - }; - - partition@1000000 { - label = "rootfs1"; - reg = <0x1000000 0x2200000>; /* 34MB */ - }; - - /* kernel2 overlaps with rootfs2 by design */ - partition@3200000 { - label = "kernel2"; - reg = <0x3200000 0x2800000>; /* 40MB */ - }; - - partition@3800000 { - label = "rootfs2"; - reg = <0x3800000 0x2200000>; /* 34MB */ - }; - - /* - * 38MB, last MB is for the BBT, not writable - */ - partition@5a00000 { - label = "syscfg"; - reg = <0x5a00000 0x2600000>; - }; - - /* - * Unused area between "s_env" and "devinfo". - * Moved here because otherwise the renumbered - * partitions would break the bootloader - * supplied bootargs - */ - partition@180000 { - label = "unused_area"; - reg = <0x280000 0x680000>; /* 6.5MB */ - }; - }; - }; - - bm-bppi { - status = "okay"; - }; - - pcie-controller { - status = "okay"; - - pcie@1,0 { - /* Marvell 88W8864, 5GHz-only */ - status = "okay"; - }; - - pcie@2,0 { - /* Marvell 88W8864, 2GHz-only */ - status = "okay"; - }; - }; }; usb3_phy: usb3_phy { @@ -372,6 +164,197 @@ }; }; +&ahci0 { + status = "okay"; +}; + +&bm { + status = "okay"; +}; + +&bm_bppi { + status = "okay"; +}; + +ð0 { + status = "okay"; + phy-mode = "rgmii-id"; + buffer-manager = <&bm>; + bm,pool-long = <2>; + bm,pool-short = <3>; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +ð2 { + status = "okay"; + phy-mode = "sgmii"; + buffer-manager = <&bm>; + bm,pool-long = <0>; + bm,pool-short = <1>; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + + pca9635@68 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9635"; + reg = <0x68>; + }; +}; + +&nand { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x200000>; /* 2MB */ + read-only; + }; + + partition@100000 { + label = "u_env"; + reg = <0x200000 0x40000>; /* 256KB */ + }; + + partition@140000 { + label = "s_env"; + reg = <0x240000 0x40000>; /* 256KB */ + }; + + partition@900000 { + label = "devinfo"; + reg = <0x900000 0x100000>; /* 1MB */ + read-only; + }; + + /* kernel1 overlaps with rootfs1 by design */ + partition@a00000 { + label = "kernel1"; + reg = <0xa00000 0x2800000>; /* 40MB */ + }; + + partition@1000000 { + label = "rootfs1"; + reg = <0x1000000 0x2200000>; /* 34MB */ + }; + + /* kernel2 overlaps with rootfs2 by design */ + partition@3200000 { + label = "kernel2"; + reg = <0x3200000 0x2800000>; /* 40MB */ + }; + + partition@3800000 { + label = "rootfs2"; + reg = <0x3800000 0x2200000>; /* 34MB */ + }; + + /* + * 38MB, last MB is for the BBT, not writable + */ + partition@5a00000 { + label = "syscfg"; + reg = <0x5a00000 0x2600000>; + }; + + /* + * Unused area between "s_env" and "devinfo". + * Moved here because otherwise the renumbered + * partitions would break the bootloader + * supplied bootargs + */ + partition@180000 { + label = "unused_area"; + reg = <0x280000 0x680000>; /* 6.5MB */ + }; +}; + +&mdio { + status = "okay"; + + switch@0 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan4"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <ð2>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie1 { + /* Marvell 88W8864, 5GHz-only */ + status = "okay"; +}; + +&pcie2 { + /* Marvell 88W8864, 2GHz-only */ + status = "okay"; +}; + &pinctrl { keys_pin: keys-pin { marvell,pins = "mpp24", "mpp29"; @@ -397,3 +380,18 @@ &spi0 { status = "disabled"; }; + +&uart0 { + /* J10: VCC, NC, RX, NC, TX, GND */ + status = "okay"; +}; + +&usb0 { + /* USB part of the eSATA/USB 2.0 port */ + status = "okay"; +}; + +&usb3_1 { + status = "okay"; + usb-phy = <&usb3_phy>; +}; -- cgit v1.2.3 From 77c82b5f83e07591710f43abf4c85e1897f2114d Mon Sep 17 00:00:00 2001 From: Ralph Sennhauser Date: Sun, 21 May 2017 14:48:51 +0200 Subject: ARM: dts: armada-385-linksys: label nodes Add labels to nodes used by dependants. Also rename node gpio_keys to gpio-keys to match the style of the rest of the file as well as the documented example. Signed-off-by: Ralph Sennhauser Signed-off-by: Imre Kaloz Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-linksys.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi index 481e4a36e26b..b7f0a16e8a2e 100644 --- a/arch/arm/boot/dts/armada-385-linksys.dtsi +++ b/arch/arm/boot/dts/armada-385-linksys.dtsi @@ -79,7 +79,7 @@ gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; }; - gpio_keys { + gpio_keys: gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; @@ -99,7 +99,7 @@ }; }; - gpio-leds { + gpio_leds: gpio-leds { compatible = "gpio-leds"; pinctrl-0 = <&power_led_pin &sata_led_pin>; pinctrl-names = "default"; @@ -210,7 +210,7 @@ reg = <0x4c>; }; - pca9635@68 { + expander0: pca9635@68 { #address-cells = <1>; #size-cells = <0>; compatible = "nxp,pca9635"; -- cgit v1.2.3 From ecdcd24864ca42d6f4ebd7cb6e340c6333b51a79 Mon Sep 17 00:00:00 2001 From: Ralph Sennhauser Date: Sun, 21 May 2017 14:48:52 +0200 Subject: ARM: dts: armada-385-linksys: flatten dependants Flatten dts of individual boards to match the new style used in armada-385-linksys.dtsi and for the Rango addition. * Caiman - Linksys WRT1200AC v1 & v2 * Cobra - Linksys WRT1900AC v2 * Shelby - Linksys WRT1900ACS v1 & v2 Signed-off-by: Ralph Sennhauser Signed-off-by: Imre Kaloz Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-linksys-caiman.dts | 99 ++++++++++++------------- arch/arm/boot/dts/armada-385-linksys-cobra.dts | 99 ++++++++++++------------- arch/arm/boot/dts/armada-385-linksys-shelby.dts | 99 ++++++++++++------------- 3 files changed, 138 insertions(+), 159 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-385-linksys-caiman.dts b/arch/arm/boot/dts/armada-385-linksys-caiman.dts index f3cee918d285..765c9394d02c 100644 --- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts +++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts @@ -44,71 +44,64 @@ model = "Linksys WRT1200AC"; compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385", "marvell,armada380"; +}; - soc { - internal-regs{ - i2c@11000 { - - pca9635@68 { - #address-cells = <1>; - #size-cells = <0>; +&expander0 { + #address-cells = <1>; + #size-cells = <0>; - wan_amber@0 { - label = "caiman:amber:wan"; - reg = <0x0>; - }; + wan_amber@0 { + label = "caiman:amber:wan"; + reg = <0x0>; + }; - wan_white@1 { - label = "caiman:white:wan"; - reg = <0x1>; - }; + wan_white@1 { + label = "caiman:white:wan"; + reg = <0x1>; + }; - wlan_2g@2 { - label = "caiman:white:wlan_2g"; - reg = <0x2>; - }; + wlan_2g@2 { + label = "caiman:white:wlan_2g"; + reg = <0x2>; + }; - wlan_5g@3 { - label = "caiman:white:wlan_5g"; - reg = <0x3>; - }; + wlan_5g@3 { + label = "caiman:white:wlan_5g"; + reg = <0x3>; + }; - usb2@5 { - label = "caiman:white:usb2"; - reg = <0x5>; - }; + usb2@5 { + label = "caiman:white:usb2"; + reg = <0x5>; + }; - usb3_1@6 { - label = "caiman:white:usb3_1"; - reg = <0x6>; - }; + usb3_1@6 { + label = "caiman:white:usb3_1"; + reg = <0x6>; + }; - usb3_2@7 { - label = "caiman:white:usb3_2"; - reg = <0x7>; - }; + usb3_2@7 { + label = "caiman:white:usb3_2"; + reg = <0x7>; + }; - wps_white@8 { - label = "caiman:white:wps"; - reg = <0x8>; - }; + wps_white@8 { + label = "caiman:white:wps"; + reg = <0x8>; + }; - wps_amber@9 { - label = "caiman:amber:wps"; - reg = <0x9>; - }; - }; - }; - }; + wps_amber@9 { + label = "caiman:amber:wps"; + reg = <0x9>; }; +}; - gpio-leds { - power { - label = "caiman:white:power"; - }; +&gpio_leds { + power { + label = "caiman:white:power"; + }; - sata { - label = "caiman:white:sata"; - }; + sata { + label = "caiman:white:sata"; }; }; diff --git a/arch/arm/boot/dts/armada-385-linksys-cobra.dts b/arch/arm/boot/dts/armada-385-linksys-cobra.dts index 111071860559..2ae1e7164f79 100644 --- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts +++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts @@ -44,71 +44,64 @@ model = "Linksys WRT1900ACv2"; compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385", "marvell,armada380"; +}; - soc { - internal-regs{ - i2c@11000 { - - pca9635@68 { - #address-cells = <1>; - #size-cells = <0>; +&expander0 { + #address-cells = <1>; + #size-cells = <0>; - wan_amber@0 { - label = "cobra:amber:wan"; - reg = <0x0>; - }; + wan_amber@0 { + label = "cobra:amber:wan"; + reg = <0x0>; + }; - wan_white@1 { - label = "cobra:white:wan"; - reg = <0x1>; - }; + wan_white@1 { + label = "cobra:white:wan"; + reg = <0x1>; + }; - wlan_2g@2 { - label = "cobra:white:wlan_2g"; - reg = <0x2>; - }; + wlan_2g@2 { + label = "cobra:white:wlan_2g"; + reg = <0x2>; + }; - wlan_5g@3 { - label = "cobra:white:wlan_5g"; - reg = <0x3>; - }; + wlan_5g@3 { + label = "cobra:white:wlan_5g"; + reg = <0x3>; + }; - usb2@5 { - label = "cobra:white:usb2"; - reg = <0x5>; - }; + usb2@5 { + label = "cobra:white:usb2"; + reg = <0x5>; + }; - usb3_1@6 { - label = "cobra:white:usb3_1"; - reg = <0x6>; - }; + usb3_1@6 { + label = "cobra:white:usb3_1"; + reg = <0x6>; + }; - usb3_2@7 { - label = "cobra:white:usb3_2"; - reg = <0x7>; - }; + usb3_2@7 { + label = "cobra:white:usb3_2"; + reg = <0x7>; + }; - wps_white@8 { - label = "cobra:white:wps"; - reg = <0x8>; - }; + wps_white@8 { + label = "cobra:white:wps"; + reg = <0x8>; + }; - wps_amber@9 { - label = "cobra:amber:wps"; - reg = <0x9>; - }; - }; - }; - }; + wps_amber@9 { + label = "cobra:amber:wps"; + reg = <0x9>; }; +}; - gpio-leds { - power { - label = "cobra:white:power"; - }; +&gpio_leds { + power { + label = "cobra:white:power"; + }; - sata { - label = "cobra:white:sata"; - }; + sata { + label = "cobra:white:sata"; }; }; diff --git a/arch/arm/boot/dts/armada-385-linksys-shelby.dts b/arch/arm/boot/dts/armada-385-linksys-shelby.dts index c7a8ddd7f9a5..74f427314626 100644 --- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts +++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts @@ -44,71 +44,64 @@ model = "Linksys WRT1900ACS"; compatible = "linksys,shelby", "linksys,armada385", "marvell,armada385", "marvell,armada380"; +}; - soc { - internal-regs{ - i2c@11000 { - - pca9635@68 { - #address-cells = <1>; - #size-cells = <0>; +&expander0 { + #address-cells = <1>; + #size-cells = <0>; - wan_amber@0 { - label = "shelby:amber:wan"; - reg = <0x0>; - }; + wan_amber@0 { + label = "shelby:amber:wan"; + reg = <0x0>; + }; - wan_white@1 { - label = "shelby:white:wan"; - reg = <0x1>; - }; + wan_white@1 { + label = "shelby:white:wan"; + reg = <0x1>; + }; - wlan_2g@2 { - label = "shelby:white:wlan_2g"; - reg = <0x2>; - }; + wlan_2g@2 { + label = "shelby:white:wlan_2g"; + reg = <0x2>; + }; - wlan_5g@3 { - label = "shelby:white:wlan_5g"; - reg = <0x3>; - }; + wlan_5g@3 { + label = "shelby:white:wlan_5g"; + reg = <0x3>; + }; - usb2@5 { - label = "shelby:white:usb2"; - reg = <0x5>; - }; + usb2@5 { + label = "shelby:white:usb2"; + reg = <0x5>; + }; - usb3_1@6 { - label = "shelby:white:usb3_1"; - reg = <0x6>; - }; + usb3_1@6 { + label = "shelby:white:usb3_1"; + reg = <0x6>; + }; - usb3_2@7 { - label = "shelby:white:usb3_2"; - reg = <0x7>; - }; + usb3_2@7 { + label = "shelby:white:usb3_2"; + reg = <0x7>; + }; - wps_white@8 { - label = "shelby:white:wps"; - reg = <0x8>; - }; + wps_white@8 { + label = "shelby:white:wps"; + reg = <0x8>; + }; - wps_amber@9 { - label = "shelby:amber:wps"; - reg = <0x9>; - }; - }; - }; - }; + wps_amber@9 { + label = "shelby:amber:wps"; + reg = <0x9>; }; +}; - gpio-leds { - power { - label = "shelby:white:power"; - }; +&gpio_leds { + power { + label = "shelby:white:power"; + }; - sata { - label = "shelby:white:sata"; - }; + sata { + label = "shelby:white:sata"; }; }; -- cgit v1.2.3 From 70fd74252ed7b056fe44097e6ff76b23a530cc94 Mon Sep 17 00:00:00 2001 From: Ralph Sennhauser Date: Sun, 21 May 2017 14:48:53 +0200 Subject: ARM: dts: armada-385-linksys: drop redundant properties in dependants Drop redundant declaration of #address-cells and #size-cells. Signed-off-by: Ralph Sennhauser Signed-off-by: Imre Kaloz Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-linksys-caiman.dts | 3 --- arch/arm/boot/dts/armada-385-linksys-cobra.dts | 3 --- arch/arm/boot/dts/armada-385-linksys-shelby.dts | 3 --- 3 files changed, 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-385-linksys-caiman.dts b/arch/arm/boot/dts/armada-385-linksys-caiman.dts index 765c9394d02c..05e854a14e0c 100644 --- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts +++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts @@ -47,9 +47,6 @@ }; &expander0 { - #address-cells = <1>; - #size-cells = <0>; - wan_amber@0 { label = "caiman:amber:wan"; reg = <0x0>; diff --git a/arch/arm/boot/dts/armada-385-linksys-cobra.dts b/arch/arm/boot/dts/armada-385-linksys-cobra.dts index 2ae1e7164f79..5b1662b95a58 100644 --- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts +++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts @@ -47,9 +47,6 @@ }; &expander0 { - #address-cells = <1>; - #size-cells = <0>; - wan_amber@0 { label = "cobra:amber:wan"; reg = <0x0>; diff --git a/arch/arm/boot/dts/armada-385-linksys-shelby.dts b/arch/arm/boot/dts/armada-385-linksys-shelby.dts index 74f427314626..a90937104b2b 100644 --- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts +++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts @@ -47,9 +47,6 @@ }; &expander0 { - #address-cells = <1>; - #size-cells = <0>; - wan_amber@0 { label = "shelby:amber:wan"; reg = <0x0>; -- cgit v1.2.3 From a43df48fbee96179bc0a90762b761c23be67d836 Mon Sep 17 00:00:00 2001 From: Ralph Sennhauser Date: Sun, 21 May 2017 14:48:54 +0200 Subject: ARM: dts: armada-385-linksys: bm pools by label order Which pools we assing doesn't matter. Use the order which doesen't leave a chance for questions for first time readers. Signed-off-by: Ralph Sennhauser Signed-off-by: Imre Kaloz Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-linksys.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi index b7f0a16e8a2e..932fca4d64c3 100644 --- a/arch/arm/boot/dts/armada-385-linksys.dtsi +++ b/arch/arm/boot/dts/armada-385-linksys.dtsi @@ -180,8 +180,8 @@ status = "okay"; phy-mode = "rgmii-id"; buffer-manager = <&bm>; - bm,pool-long = <2>; - bm,pool-short = <3>; + bm,pool-long = <0>; + bm,pool-short = <1>; fixed-link { speed = <1000>; full-duplex; @@ -192,8 +192,8 @@ status = "okay"; phy-mode = "sgmii"; buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <1>; + bm,pool-long = <2>; + bm,pool-short = <3>; fixed-link { speed = <1000>; full-duplex; -- cgit v1.2.3 From da3ac208f88af4302ca36e0d4bf6e621aa557e71 Mon Sep 17 00:00:00 2001 From: Ralph Sennhauser Date: Sun, 21 May 2017 14:48:55 +0200 Subject: ARM: dts: armada-385-linksys: usb3 label cleanup Now that we use the reference for the USB3.0 port update the node name and labels for the phy and vbus to match the label used by armada-38x.dtsi. Signed-off-by: Ralph Sennhauser Signed-off-by: Imre Kaloz Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-linksys.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi index 932fca4d64c3..6cc1ec7699ff 100644 --- a/arch/arm/boot/dts/armada-385-linksys.dtsi +++ b/arch/arm/boot/dts/armada-385-linksys.dtsi @@ -63,16 +63,16 @@ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>; }; - usb3_phy: usb3_phy { + usb3_1_phy: usb3_1-phy { compatible = "usb-nop-xceiv"; - vcc-supply = <®_xhci0_vbus>; + vcc-supply = <&usb3_1_vbus>; }; - reg_xhci0_vbus: xhci0-vbus { + usb3_1_vbus: usb3_1-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&xhci0_vbus_pins>; - regulator-name = "xhci0-vbus"; + pinctrl-0 = <&usb3_1_vbus_pins>; + regulator-name = "usb3_1-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; @@ -371,7 +371,7 @@ marvell,function = "gpio"; }; - xhci0_vbus_pins: xhci0-vbus-pins { + usb3_1_vbus_pins: usb3_1-vbus-pins { marvell,pins = "mpp50"; marvell,function = "gpio"; }; @@ -393,5 +393,5 @@ &usb3_1 { status = "okay"; - usb-phy = <&usb3_phy>; + usb-phy = <&usb3_1_phy>; }; -- cgit v1.2.3 From 4c38d10c75bc196c703643f72669d9be0d11e4e5 Mon Sep 17 00:00:00 2001 From: Ralph Sennhauser Date: Sun, 21 May 2017 14:48:56 +0200 Subject: ARM: dts: armada-385-linksys: drop legacy DSA bindings The new ones work so there is little reason to keep the legacy bindings. Use the rework as the opportunity to drop the legacy node. Signed-off-by: Ralph Sennhauser Signed-off-by: Imre Kaloz Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-linksys.dtsi | 47 ------------------------------- 1 file changed, 47 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi index 6cc1ec7699ff..f1d6b77c73fe 100644 --- a/arch/arm/boot/dts/armada-385-linksys.dtsi +++ b/arch/arm/boot/dts/armada-385-linksys.dtsi @@ -115,53 +115,6 @@ linux,default-trigger = "disk-activity"; }; }; - - dsa@0 { - status = "disabled"; - - compatible = "marvell,dsa"; - #address-cells = <2>; - #size-cells = <0>; - - dsa,ethernet = <ð2>; - dsa,mii-bus = <&mdio>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0>; /* MDIO address 0, switch 0 in tree */ - - port@0 { - reg = <0>; - label = "lan4"; - }; - - port@1 { - reg = <1>; - label = "lan3"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - }; - }; }; &ahci0 { -- cgit v1.2.3 From 0ebbb9575ac6bafa1219a4ae81639712bb3054cb Mon Sep 17 00:00:00 2001 From: Ralph Sennhauser Date: Sun, 21 May 2017 14:48:57 +0200 Subject: ARM: dts: armada-385-linksys: use binary unit prefixes Use IEEE 1541-2002 unit prefixes for sizes. Signed-off-by: Ralph Sennhauser Signed-off-by: Imre Kaloz Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-linksys.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi index f1d6b77c73fe..4049eaf80638 100644 --- a/arch/arm/boot/dts/armada-385-linksys.dtsi +++ b/arch/arm/boot/dts/armada-385-linksys.dtsi @@ -52,7 +52,7 @@ memory { device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ + reg = <0x00000000 0x20000000>; /* 512 MiB */ }; soc { @@ -180,50 +180,50 @@ partition@0 { label = "u-boot"; - reg = <0x0000000 0x200000>; /* 2MB */ + reg = <0x0000000 0x200000>; /* 2MiB */ read-only; }; partition@100000 { label = "u_env"; - reg = <0x200000 0x40000>; /* 256KB */ + reg = <0x200000 0x40000>; /* 256KiB */ }; partition@140000 { label = "s_env"; - reg = <0x240000 0x40000>; /* 256KB */ + reg = <0x240000 0x40000>; /* 256KiB */ }; partition@900000 { label = "devinfo"; - reg = <0x900000 0x100000>; /* 1MB */ + reg = <0x900000 0x100000>; /* 1MiB */ read-only; }; /* kernel1 overlaps with rootfs1 by design */ partition@a00000 { label = "kernel1"; - reg = <0xa00000 0x2800000>; /* 40MB */ + reg = <0xa00000 0x2800000>; /* 40MiB */ }; partition@1000000 { label = "rootfs1"; - reg = <0x1000000 0x2200000>; /* 34MB */ + reg = <0x1000000 0x2200000>; /* 34MiB */ }; /* kernel2 overlaps with rootfs2 by design */ partition@3200000 { label = "kernel2"; - reg = <0x3200000 0x2800000>; /* 40MB */ + reg = <0x3200000 0x2800000>; /* 40MiB */ }; partition@3800000 { label = "rootfs2"; - reg = <0x3800000 0x2200000>; /* 34MB */ + reg = <0x3800000 0x2200000>; /* 34MiB */ }; /* - * 38MB, last MB is for the BBT, not writable + * 38MiB, last MiB is for the BBT, not writable */ partition@5a00000 { label = "syscfg"; @@ -238,7 +238,7 @@ */ partition@180000 { label = "unused_area"; - reg = <0x280000 0x680000>; /* 6.5MB */ + reg = <0x280000 0x680000>; /* 6.5MiB */ }; }; -- cgit v1.2.3 From bf6c959eb43ebe8d8ea4fac6d622a70f3ddc8e63 Mon Sep 17 00:00:00 2001 From: Ralph Sennhauser Date: Sun, 21 May 2017 14:48:58 +0200 Subject: ARM: dts: armada-385-linksys: partition layout is board specific Move the partition layout to individual boards. The Linksys WRT 3200 ACM (Rango) comes with a 256MiB nand flash chip and different layout. Signed-off-by: Ralph Sennhauser Signed-off-by: Imre Kaloz Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-linksys-caiman.dts | 67 +++++++++++++++++++++++++ arch/arm/boot/dts/armada-385-linksys-cobra.dts | 67 +++++++++++++++++++++++++ arch/arm/boot/dts/armada-385-linksys-shelby.dts | 67 +++++++++++++++++++++++++ arch/arm/boot/dts/armada-385-linksys.dtsi | 64 +---------------------- 4 files changed, 202 insertions(+), 63 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-385-linksys-caiman.dts b/arch/arm/boot/dts/armada-385-linksys-caiman.dts index 05e854a14e0c..ee669ae61011 100644 --- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts +++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts @@ -102,3 +102,70 @@ label = "caiman:white:sata"; }; }; + +&nand { + /* 128MiB */ + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x200000>; /* 2MiB */ + read-only; + }; + + partition@100000 { + label = "u_env"; + reg = <0x200000 0x40000>; /* 256KiB */ + }; + + partition@140000 { + label = "s_env"; + reg = <0x240000 0x40000>; /* 256KiB */ + }; + + partition@900000 { + label = "devinfo"; + reg = <0x900000 0x100000>; /* 1MiB */ + read-only; + }; + + /* kernel1 overlaps with rootfs1 by design */ + partition@a00000 { + label = "kernel1"; + reg = <0xa00000 0x2800000>; /* 40MiB */ + }; + + partition@1000000 { + label = "rootfs1"; + reg = <0x1000000 0x2200000>; /* 34MiB */ + }; + + /* kernel2 overlaps with rootfs2 by design */ + partition@3200000 { + label = "kernel2"; + reg = <0x3200000 0x2800000>; /* 40MiB */ + }; + + partition@3800000 { + label = "rootfs2"; + reg = <0x3800000 0x2200000>; /* 34MiB */ + }; + + /* + * 38MiB, last MiB is for the BBT, not writable + */ + partition@5a00000 { + label = "syscfg"; + reg = <0x5a00000 0x2600000>; + }; + + /* + * Unused area between "s_env" and "devinfo". + * Moved here because otherwise the renumbered + * partitions would break the bootloader + * supplied bootargs + */ + partition@180000 { + label = "unused_area"; + reg = <0x280000 0x680000>; /* 6.5MiB */ + }; +}; diff --git a/arch/arm/boot/dts/armada-385-linksys-cobra.dts b/arch/arm/boot/dts/armada-385-linksys-cobra.dts index 5b1662b95a58..5169ca89c55a 100644 --- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts +++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts @@ -102,3 +102,70 @@ label = "cobra:white:sata"; }; }; + +&nand { + /* 128MiB */ + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x200000>; /* 2MiB */ + read-only; + }; + + partition@100000 { + label = "u_env"; + reg = <0x200000 0x40000>; /* 256KiB */ + }; + + partition@140000 { + label = "s_env"; + reg = <0x240000 0x40000>; /* 256KiB */ + }; + + partition@900000 { + label = "devinfo"; + reg = <0x900000 0x100000>; /* 1MiB */ + read-only; + }; + + /* kernel1 overlaps with rootfs1 by design */ + partition@a00000 { + label = "kernel1"; + reg = <0xa00000 0x2800000>; /* 40MiB */ + }; + + partition@1000000 { + label = "rootfs1"; + reg = <0x1000000 0x2200000>; /* 34MiB */ + }; + + /* kernel2 overlaps with rootfs2 by design */ + partition@3200000 { + label = "kernel2"; + reg = <0x3200000 0x2800000>; /* 40MiB */ + }; + + partition@3800000 { + label = "rootfs2"; + reg = <0x3800000 0x2200000>; /* 34MiB */ + }; + + /* + * 38MiB, last MiB is for the BBT, not writable + */ + partition@5a00000 { + label = "syscfg"; + reg = <0x5a00000 0x2600000>; + }; + + /* + * Unused area between "s_env" and "devinfo". + * Moved here because otherwise the renumbered + * partitions would break the bootloader + * supplied bootargs + */ + partition@180000 { + label = "unused_area"; + reg = <0x280000 0x680000>; /* 6.5MiB */ + }; +}; diff --git a/arch/arm/boot/dts/armada-385-linksys-shelby.dts b/arch/arm/boot/dts/armada-385-linksys-shelby.dts index a90937104b2b..94aa35bc0bff 100644 --- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts +++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts @@ -102,3 +102,70 @@ label = "shelby:white:sata"; }; }; + +&nand { + /* 128MiB */ + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x200000>; /* 2MiB */ + read-only; + }; + + partition@100000 { + label = "u_env"; + reg = <0x200000 0x40000>; /* 256KiB */ + }; + + partition@140000 { + label = "s_env"; + reg = <0x240000 0x40000>; /* 256KiB */ + }; + + partition@900000 { + label = "devinfo"; + reg = <0x900000 0x100000>; /* 1MiB */ + read-only; + }; + + /* kernel1 overlaps with rootfs1 by design */ + partition@a00000 { + label = "kernel1"; + reg = <0xa00000 0x2800000>; /* 40MiB */ + }; + + partition@1000000 { + label = "rootfs1"; + reg = <0x1000000 0x2200000>; /* 34MiB */ + }; + + /* kernel2 overlaps with rootfs2 by design */ + partition@3200000 { + label = "kernel2"; + reg = <0x3200000 0x2800000>; /* 40MiB */ + }; + + partition@3800000 { + label = "rootfs2"; + reg = <0x3800000 0x2200000>; /* 34MiB */ + }; + + /* + * 38MiB, last MiB is for the BBT, not writable + */ + partition@5a00000 { + label = "syscfg"; + reg = <0x5a00000 0x2600000>; + }; + + /* + * Unused area between "s_env" and "devinfo". + * Moved here because otherwise the renumbered + * partitions would break the bootloader + * supplied bootargs + */ + partition@180000 { + label = "unused_area"; + reg = <0x280000 0x680000>; /* 6.5MiB */ + }; +}; diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi index 4049eaf80638..485abffb4368 100644 --- a/arch/arm/boot/dts/armada-385-linksys.dtsi +++ b/arch/arm/boot/dts/armada-385-linksys.dtsi @@ -172,74 +172,12 @@ }; &nand { + /* 128MiB or 256MiB */ status = "okay"; num-cs = <1>; marvell,nand-keep-config; marvell,nand-enable-arbiter; nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x200000>; /* 2MiB */ - read-only; - }; - - partition@100000 { - label = "u_env"; - reg = <0x200000 0x40000>; /* 256KiB */ - }; - - partition@140000 { - label = "s_env"; - reg = <0x240000 0x40000>; /* 256KiB */ - }; - - partition@900000 { - label = "devinfo"; - reg = <0x900000 0x100000>; /* 1MiB */ - read-only; - }; - - /* kernel1 overlaps with rootfs1 by design */ - partition@a00000 { - label = "kernel1"; - reg = <0xa00000 0x2800000>; /* 40MiB */ - }; - - partition@1000000 { - label = "rootfs1"; - reg = <0x1000000 0x2200000>; /* 34MiB */ - }; - - /* kernel2 overlaps with rootfs2 by design */ - partition@3200000 { - label = "kernel2"; - reg = <0x3200000 0x2800000>; /* 40MiB */ - }; - - partition@3800000 { - label = "rootfs2"; - reg = <0x3800000 0x2200000>; /* 34MiB */ - }; - - /* - * 38MiB, last MiB is for the BBT, not writable - */ - partition@5a00000 { - label = "syscfg"; - reg = <0x5a00000 0x2600000>; - }; - - /* - * Unused area between "s_env" and "devinfo". - * Moved here because otherwise the renumbered - * partitions would break the bootloader - * supplied bootargs - */ - partition@180000 { - label = "unused_area"; - reg = <0x280000 0x680000>; /* 6.5MiB */ - }; }; &mdio { -- cgit v1.2.3 From 1216132f4dd57a4a6b8557ce2dbc64758b433991 Mon Sep 17 00:00:00 2001 From: Ralph Sennhauser Date: Sun, 21 May 2017 14:48:59 +0200 Subject: ARM: dts: armada-385-linksys: group pins in pinctrl A pin group per node is sufficient, further specialization only serves as documentation which can be a comment just as well. This simplifies configuring pins for nodes in dependants. Also use labels which end up right by the node they are intended for. Signed-off-by: Ralph Sennhauser Signed-off-by: Imre Kaloz Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-linksys.dtsi | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi index 485abffb4368..1bb974a7c30b 100644 --- a/arch/arm/boot/dts/armada-385-linksys.dtsi +++ b/arch/arm/boot/dts/armada-385-linksys.dtsi @@ -83,7 +83,7 @@ compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; - pinctrl-0 = <&keys_pin>; + pinctrl-0 = <&gpio_keys_pins>; pinctrl-names = "default"; button@1 { @@ -101,7 +101,7 @@ gpio_leds: gpio-leds { compatible = "gpio-leds"; - pinctrl-0 = <&power_led_pin &sata_led_pin>; + pinctrl-0 = <&gpio_leds_pins>; pinctrl-names = "default"; power { @@ -247,18 +247,15 @@ }; &pinctrl { - keys_pin: keys-pin { + gpio_keys_pins: gpio-keys-pins { + /* mpp24: wps, mpp29: reset */ marvell,pins = "mpp24", "mpp29"; marvell,function = "gpio"; }; - power_led_pin: power-led-pin { - marvell,pins = "mpp55"; - marvell,function = "gpio"; - }; - - sata_led_pin: sata-led-pin { - marvell,pins = "mpp54"; + gpio_leds_pins: gpio-leds-pins { + /* mpp54: sata, mpp55: power */ + marvell,pins = "mpp54", "mpp55"; marvell,function = "gpio"; }; -- cgit v1.2.3 From b2758f8edbf87f964825de1119887d9deb56dbaa Mon Sep 17 00:00:00 2001 From: Ralph Sennhauser Date: Sun, 21 May 2017 14:49:00 +0200 Subject: ARM: dts: armada-385-linksys: fixup button node names Buttons don't have a reg property; drop pseudo address and fixup names of individual button nodes. Also drop #address-cells and #size-cells properties. Signed-off-by: Ralph Sennhauser Signed-off-by: Imre Kaloz Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-linksys.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi index 1bb974a7c30b..e1f355ffc8f7 100644 --- a/arch/arm/boot/dts/armada-385-linksys.dtsi +++ b/arch/arm/boot/dts/armada-385-linksys.dtsi @@ -81,18 +81,16 @@ gpio_keys: gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&gpio_keys_pins>; pinctrl-names = "default"; - button@1 { + wps { label = "WPS"; linux,code = ; gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; }; - button@2 { + reset { label = "Factory Reset Button"; linux,code = ; gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; -- cgit v1.2.3 From 41c8652096268988207d4fa13ee9236c9980d34d Mon Sep 17 00:00:00 2001 From: Ralph Sennhauser Date: Wed, 24 May 2017 08:16:46 +0200 Subject: ARM: dts: mvebu: add support for Linksys WRT3200ACM (Rango) The Linksys WRT3200ACM (Rango) is the lates Armada-385 based router in the Linksys WRT AC Series which got released in October 2016. Key differences to the earlier Armada-385 based devices in the series is a bigger flash chip, next generation wireless modules (Marvell 88W8964) in the mini pcie slots as well as a Marvell SD8887. Finally the CPU is clocked at 1866 GHz by default. The file armada-385-linksys-rango.dts is loosly based off of a DTS authored by Imre Kaloz. As Rango is part of the armada-385-linksys family of boards use the armada-385-linksys.dtsi as basis. As for functional differences to Imre Kaloz dts, the wlan LEDs aren't connected to the expander chip pca9635 but directly to GPIOs. Then mpp47 controls the USB2.0 port and not the USB3.0 port, so use the correct GPIO mpp44 for it. Finally use non-removable instead of broken-cd with the sdhci node to avoid polling. Other changes can be categorized as just cleanup / reorganization due to using the armada-385-linksys.dtsi. URL: https://github.com/openwrt/openwrt/blob/0abc3fa5a996daf7dafdc7794ccfe3fa7e955c5a/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys-rango.dts Signed-off-by: Ralph Sennhauser Signed-off-by: Imre Kaloz Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/armada-385-linksys-rango.dts | 203 +++++++++++++++++++++++++ 2 files changed, 204 insertions(+) create mode 100644 arch/arm/boot/dts/armada-385-linksys-rango.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9c5e1d944d1c..6be297427c11 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -999,6 +999,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \ armada-385-db-ap.dtb \ armada-385-linksys-caiman.dtb \ armada-385-linksys-cobra.dtb \ + armada-385-linksys-rango.dtb \ armada-385-linksys-shelby.dtb \ armada-385-synology-ds116.dtb \ armada-385-turris-omnia.dtb \ diff --git a/arch/arm/boot/dts/armada-385-linksys-rango.dts b/arch/arm/boot/dts/armada-385-linksys-rango.dts new file mode 100644 index 000000000000..da8a0f3d432b --- /dev/null +++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts @@ -0,0 +1,203 @@ +/* + * Device Tree file for the Linksys WRT3200ACM (Rango) + * + * Copyright (C) 2016 Imre Kaloz + * + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include +#include +#include "armada-385-linksys.dtsi" + +/ { + model = "Linksys WRT3200ACM"; + compatible = "linksys,rango", "linksys,armada385", "marvell,armada385", + "marvell,armada380"; +}; + +&expander0 { + wan_amber@0 { + label = "rango:amber:wan"; + reg = <0x0>; + }; + + wan_white@1 { + label = "rango:white:wan"; + reg = <0x1>; + }; + + usb2@5 { + label = "rango:white:usb2"; + reg = <0x5>; + }; + + usb3_1@6 { + label = "rango:white:usb3_1"; + reg = <0x6>; + }; + + usb3_2@7 { + label = "rango:white:usb3_2"; + reg = <0x7>; + }; + + wps_white@8 { + label = "rango:white:wps"; + reg = <0x8>; + }; + + wps_amber@9 { + label = "rango:amber:wps"; + reg = <0x9>; + }; +}; + +&gpio_leds { + power { + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + label = "rango:white:power"; + }; + + sata { + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + label = "rango:white:sata"; + }; + + wlan_2g { + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + label = "rango:white:wlan_2g"; + }; + + wlan_5g { + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + label = "rango:white:wlan_5g"; + }; +}; + +&gpio_leds_pins { + marvell,pins = "mpp21", "mpp45", "mpp46", "mpp56"; +}; + +&nand { + /* AMD/Spansion S34ML02G2 256MiB, OEM Layout */ + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x200000>; /* 2MiB */ + read-only; + }; + + partition@200000 { + label = "u_env"; + reg = <0x200000 0x20000>; /* 128KiB */ + }; + + partition@220000 { + label = "s_env"; + reg = <0x220000 0x40000>; /* 256KiB */ + }; + + partition@7e0000 { + label = "devinfo"; + reg = <0x7e0000 0x40000>; /* 256KiB */ + read-only; + }; + + partition@820000 { + label = "sysdiag"; + reg = <0x820000 0x1e0000>; /* 1920KiB */ + read-only; + }; + + /* kernel1 overlaps with rootfs1 by design */ + partition@a00000 { + label = "kernel1"; + reg = <0xa00000 0x5000000>; /* 80MiB */ + }; + + partition@1000000 { + label = "rootfs1"; + reg = <0x1000000 0x4a00000>; /* 74MiB */ + }; + + /* kernel2 overlaps with rootfs2 by design */ + partition@5a00000 { + label = "kernel2"; + reg = <0x5a00000 0x5000000>; /* 80MiB */ + }; + + partition@6000000 { + label = "rootfs2"; + reg = <0x6000000 0x4a00000>; /* 74MiB */ + }; + + /* + * 86MiB, last MiB is for the BBT, not writable + */ + partition@aa00000 { + label = "syscfg"; + reg = <0xaa00000 0x5600000>; + }; + + /* + * Unused area between "s_env" and "devinfo". + * Moved here because otherwise the renumbered + * partitions would break the bootloader + * supplied bootargs + */ + partition@180000 { + label = "unused_area"; + reg = <0x260000 0x5c0000>; /* 5.75MiB */ + }; +}; + +&sdhci { + pinctrl-names = "default"; + pinctrl-0 = <&sdhci_pins>; + no-1-8-v; + non-removable; + wp-inverted; + bus-width = <8>; + status = "okay"; +}; + +&usb3_1_vbus { + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; +}; + +&usb3_1_vbus_pins { + marvell,pins = "mpp44"; +}; -- cgit v1.2.3 From 97800cf8b6a81cf17ad216ec9d0c8e78c68b7aef Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Tue, 23 May 2017 15:34:32 +0200 Subject: ARM: dts: turris-omnia: Add generic compatible string for I2C EEPROM The at24 driver allows to register I2C EEPROM chips using different vendor and devices, but the I2C subsystem does not take the vendor into account when matching using the I2C table since it only has device entries. But when matching using an OF table, both the vendor and device has to be taken into account so the driver defines only a set of compatible strings using the "atmel" vendor as a generic fallback for compatible I2C devices. So add this generic fallback to the device node compatible string to make the device to match the driver using the OF device ID table. Signed-off-by: Javier Martinez Canillas Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-turris-omnia.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index 28eede180e4f..be16ce39fb3d 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -171,7 +171,7 @@ /* leds device (in STM32F0) at address 0x2b */ eeprom@54 { - compatible = "at,24c64"; + compatible = "atmel,24c64"; reg = <0x54>; /* The EEPROM contains data for bootloader. -- cgit v1.2.3 From 4fcee14d3802b60f22baf1aeab9f1cff08834c56 Mon Sep 17 00:00:00 2001 From: Peter Korsgaard Date: Fri, 16 Jun 2017 14:39:57 +0200 Subject: ARM: dts: kirkwood: Fix Openblock A6 nand partition overlap The "test" and "conf" nand partitions partly overlap: Creating 6 MTD partitions on "orion_nand": 0x000000000000-0x000000090000 : "uboot" 0x000000090000-0x0000000d4000 : "env" 0x0000000d4000-0x0000000f8000 : "test" 0x0000000f4000-0x0000004f4000 : "conf" That is unlikely to be desired, and not matching the partition map used in u-boot - So adjust the test partition size to fix this. Signed-off-by: Peter Korsgaard Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/kirkwood-openblocks_a6.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index 94e49f32d5f9..c75da5f0ca48 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts @@ -141,7 +141,7 @@ partition@d4000 { label = "test"; - reg = <0xd4000 0x24000>; + reg = <0xd4000 0x20000>; }; partition@f4000 { -- cgit v1.2.3 From d8710c3fb912574709166bba24f4c64162ab832c Mon Sep 17 00:00:00 2001 From: Christopher Spinrath Date: Tue, 30 May 2017 22:16:01 +0200 Subject: ARM: dts: imx6q-cm-fx6: add sdio wifi/bt nodes The cm-fx6 module has an on-board AW-NH387 WiFi/BT module which is based on Marvell's SD8787 chip and is connected to the usdhc1 controller. Unfortunately, the chip gets unresponsive if the Bluetooth AMP (Alternate Mac/Phy) function gets probed but the loaded firmware doesn't support it. For instance, this is the case for the most recent firmware in linux-firmware (Version 14.66.35.p52). Thus, just add the required nodes but leave the usdhc1 node disabled explicitly. Users who disabled the Bluetooth (AMP) support of their OS can then conveniently enable WiFi (or even plain Bluetooth) support with a simple device tree overlay/bootloader configuration. Signed-off-by: Christopher Spinrath Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-cm-fx6.dts | 41 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index a8af3822d9df..fe6ab0aa34f9 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -64,6 +64,14 @@ }; }; + awnh387_pwrseq: pwrseq { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwrseq>; + compatible = "mmc-pwrseq-sd8787"; + powerdown-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + }; + reg_pcie_power_on_gpio: regulator-pcie-power-on-gpio { compatible = "regulator-fixed"; regulator-name = "regulator-pcie-power-on-gpio"; @@ -304,6 +312,13 @@ >; }; + pinctrl_pwrseq: pwrseqgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 + >; + }; + pinctrl_spdif: spdifgrp { fsl,pins = < MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 @@ -330,6 +345,17 @@ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 >; }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 + >; + }; }; &pcie { @@ -382,3 +408,18 @@ dr_mode = "otg"; status = "okay"; }; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + mmc-pwrseq = <&awnh387_pwrseq>; + non-removable; + /* + * If the OS probes the Bluetooth AMP function advertised on this bus + * but the firmware in place does not support it, the WiFi/BT module + * gets unresponsive. + * Users who configured their OS properly can enable this node to gain + * WiFi and/or plain Bluetooth support. + */ + status = "disabled"; +}; -- cgit v1.2.3 From 6db53373884327f0457d90aa665d249a11461b07 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 17 Jun 2017 18:02:54 -0300 Subject: ARM: imx_v6_v7_defconfig: Select CONFIG_IMX7D_ADC Select CONFIG_IMX7D_ADC so that the i.MX7 ADC driver can be built by default. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 2dbbc52d4efa..e74de69caeab 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -345,6 +345,7 @@ CONFIG_IMX_SDMA=y CONFIG_MXS_DMA=y CONFIG_STAGING=y CONFIG_IIO=y +CONFIG_IMX7D_ADC=y CONFIG_VF610_ADC=y CONFIG_MPL3115=y CONFIG_PWM=y -- cgit v1.2.3 From 620176f335017fbfcbc79d26a8c9beb6e64f4868 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 26 May 2017 21:49:47 +0100 Subject: ARM: 8678/1: ftrace: Adds support for CONFIG_DYNAMIC_FTRACE_WITH_REGS The DYNAMIC_FTRACE_WITH_REGS configuration makes it possible for a ftrace operation to specify if registers need to saved/restored by the ftrace handler. This is needed by kgraft and possibly other ftrace-based tools, and the ARM architecture is currently lacking this feature. It would also be the first step to support the "Kprobes-on-ftrace" optimization on ARM. This patch introduces a new ftrace handler that stores the registers on the stack before calling the next stage. The registers are restored from the stack before going back to the instrumented function. A side-effect of this patch is to activate the support for ftrace_modify_call() as it defines ARCH_SUPPORTS_FTRACE_OPS for the ARM architecture. Signed-off-by: Abel Vesa Signed-off-by: Russell King --- arch/arm/Kconfig | 1 + arch/arm/include/asm/ftrace.h | 4 ++ arch/arm/kernel/entry-ftrace.S | 100 +++++++++++++++++++++++++++++++++++++++++ arch/arm/kernel/ftrace.c | 37 +++++++++++++++ 4 files changed, 142 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4c1a35f15838..730d456e2843 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -56,6 +56,7 @@ config ARM select HAVE_DMA_API_DEBUG select HAVE_DMA_CONTIGUOUS if MMU select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU + select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU select HAVE_EXIT_THREAD select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) diff --git a/arch/arm/include/asm/ftrace.h b/arch/arm/include/asm/ftrace.h index 22b73112b75f..f379881d5cc3 100644 --- a/arch/arm/include/asm/ftrace.h +++ b/arch/arm/include/asm/ftrace.h @@ -1,6 +1,10 @@ #ifndef _ASM_ARM_FTRACE #define _ASM_ARM_FTRACE +#ifdef CONFIG_DYNAMIC_FTRACE_WITH_REGS +#define ARCH_SUPPORTS_FTRACE_OPS 1 +#endif + #ifdef CONFIG_FUNCTION_TRACER #define MCOUNT_ADDR ((unsigned long)(__gnu_mcount_nc)) #define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */ diff --git a/arch/arm/kernel/entry-ftrace.S b/arch/arm/kernel/entry-ftrace.S index c73c4030ca5d..efcd9f25a14b 100644 --- a/arch/arm/kernel/entry-ftrace.S +++ b/arch/arm/kernel/entry-ftrace.S @@ -92,12 +92,95 @@ 2: mcount_exit .endm +#ifdef CONFIG_DYNAMIC_FTRACE_WITH_REGS + +.macro __ftrace_regs_caller + + sub sp, sp, #8 @ space for PC and CPSR OLD_R0, + @ OLD_R0 will overwrite previous LR + + add ip, sp, #12 @ move in IP the value of SP as it was + @ before the push {lr} of the mcount mechanism + + str lr, [sp, #0] @ store LR instead of PC + + ldr lr, [sp, #8] @ get previous LR + + str r0, [sp, #8] @ write r0 as OLD_R0 over previous LR + + stmdb sp!, {ip, lr} + stmdb sp!, {r0-r11, lr} + + @ stack content at this point: + @ 0 4 48 52 56 60 64 68 72 + @ R0 | R1 | ... | LR | SP + 4 | previous LR | LR | PSR | OLD_R0 | + + mov r3, sp @ struct pt_regs* + + ldr r2, =function_trace_op + ldr r2, [r2] @ pointer to the current + @ function tracing op + + ldr r1, [sp, #S_LR] @ lr of instrumented func + + ldr lr, [sp, #S_PC] @ get LR + + mcount_adjust_addr r0, lr @ instrumented function + + .globl ftrace_regs_call +ftrace_regs_call: + bl ftrace_stub + +#ifdef CONFIG_FUNCTION_GRAPH_TRACER + .globl ftrace_graph_regs_call +ftrace_graph_regs_call: + mov r0, r0 +#endif + + @ pop saved regs + ldmia sp!, {r0-r12} @ restore r0 through r12 + ldr ip, [sp, #8] @ restore PC + ldr lr, [sp, #4] @ restore LR + ldr sp, [sp, #0] @ restore SP + mov pc, ip @ return +.endm + +#ifdef CONFIG_FUNCTION_GRAPH_TRACER +.macro __ftrace_graph_regs_caller + + sub r0, fp, #4 @ lr of instrumented routine (parent) + + @ called from __ftrace_regs_caller + ldr r1, [sp, #S_PC] @ instrumented routine (func) + mcount_adjust_addr r1, r1 + + mov r2, fp @ frame pointer + bl prepare_ftrace_return + + @ pop registers saved in ftrace_regs_caller + ldmia sp!, {r0-r12} @ restore r0 through r12 + ldr ip, [sp, #8] @ restore PC + ldr lr, [sp, #4] @ restore LR + ldr sp, [sp, #0] @ restore SP + mov pc, ip @ return + +.endm +#endif +#endif + .macro __ftrace_caller suffix mcount_enter mcount_get_lr r1 @ lr of instrumented func mcount_adjust_addr r0, lr @ instrumented function +#ifdef CONFIG_DYNAMIC_FTRACE_WITH_REGS + ldr r2, =function_trace_op + ldr r2, [r2] @ pointer to the current + @ function tracing op + mov r3, #0 @ regs is NULL +#endif + .globl ftrace_call\suffix ftrace_call\suffix: bl ftrace_stub @@ -212,6 +295,15 @@ UNWIND(.fnstart) __ftrace_caller UNWIND(.fnend) ENDPROC(ftrace_caller) + +#ifdef CONFIG_DYNAMIC_FTRACE_WITH_REGS +ENTRY(ftrace_regs_caller) +UNWIND(.fnstart) + __ftrace_regs_caller +UNWIND(.fnend) +ENDPROC(ftrace_regs_caller) +#endif + #endif #ifdef CONFIG_FUNCTION_GRAPH_TRACER @@ -220,6 +312,14 @@ UNWIND(.fnstart) __ftrace_graph_caller UNWIND(.fnend) ENDPROC(ftrace_graph_caller) + +#ifdef CONFIG_DYNAMIC_FTRACE_WITH_REGS +ENTRY(ftrace_graph_regs_caller) +UNWIND(.fnstart) + __ftrace_graph_regs_caller +UNWIND(.fnend) +ENDPROC(ftrace_graph_regs_caller) +#endif #endif .purgem mcount_enter diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c index 833c991075a1..5617932a83df 100644 --- a/arch/arm/kernel/ftrace.c +++ b/arch/arm/kernel/ftrace.c @@ -141,6 +141,15 @@ int ftrace_update_ftrace_func(ftrace_func_t func) ret = ftrace_modify_code(pc, 0, new, false); +#ifdef CONFIG_DYNAMIC_FTRACE_WITH_REGS + if (!ret) { + pc = (unsigned long)&ftrace_regs_call; + new = ftrace_call_replace(pc, (unsigned long)func); + + ret = ftrace_modify_code(pc, 0, new, false); + } +#endif + #ifdef CONFIG_OLD_MCOUNT if (!ret) { pc = (unsigned long)&ftrace_call_old; @@ -159,11 +168,29 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) unsigned long ip = rec->ip; old = ftrace_nop_replace(rec); + + new = ftrace_call_replace(ip, adjust_address(rec, addr)); + + return ftrace_modify_code(rec->ip, old, new, true); +} + +#ifdef CONFIG_DYNAMIC_FTRACE_WITH_REGS + +int ftrace_modify_call(struct dyn_ftrace *rec, unsigned long old_addr, + unsigned long addr) +{ + unsigned long new, old; + unsigned long ip = rec->ip; + + old = ftrace_call_replace(ip, adjust_address(rec, old_addr)); + new = ftrace_call_replace(ip, adjust_address(rec, addr)); return ftrace_modify_code(rec->ip, old, new, true); } +#endif + int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec, unsigned long addr) { @@ -231,6 +258,8 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr, extern unsigned long ftrace_graph_call; extern unsigned long ftrace_graph_call_old; extern void ftrace_graph_caller_old(void); +extern unsigned long ftrace_graph_regs_call; +extern void ftrace_graph_regs_caller(void); static int __ftrace_modify_caller(unsigned long *callsite, void (*func) (void), bool enable) @@ -253,6 +282,14 @@ static int ftrace_modify_graph_caller(bool enable) ftrace_graph_caller, enable); +#ifdef CONFIG_DYNAMIC_FTRACE_WITH_REGS + if (!ret) + ret = __ftrace_modify_caller(&ftrace_graph_regs_call, + ftrace_graph_regs_caller, + enable); +#endif + + #ifdef CONFIG_OLD_MCOUNT if (!ret) ret = __ftrace_modify_caller(&ftrace_graph_call_old, -- cgit v1.2.3 From 2d618fee6984c5124f8e66972df5b1262ac7836e Mon Sep 17 00:00:00 2001 From: Marc Gonzalez Date: Tue, 30 May 2017 16:41:31 +0100 Subject: ARM: 8679/1: bitops: Align prototypes to generic API include/asm-generic/bitops/find.h declares: extern unsigned long find_first_zero_bit(const unsigned long *addr, unsigned long size); while arch/arm/include/asm/bitops.h declares: #define find_first_zero_bit(p,sz) _find_first_zero_bit_le(p,sz) extern int _find_first_zero_bit_le(const void * p, unsigned size); Align the arm prototypes to the generic API, to have gcc report inadequate arguments, such as pointer to u32. Signed-off-by: Marc Gonzalez Signed-off-by: Russell King --- arch/arm/include/asm/bitops.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index e943e6cee254..f308c8c40cb9 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -159,16 +159,16 @@ extern int _test_and_change_bit(int nr, volatile unsigned long * p); /* * Little endian assembly bitops. nr = 0 -> byte 0 bit 0. */ -extern int _find_first_zero_bit_le(const void * p, unsigned size); -extern int _find_next_zero_bit_le(const void * p, int size, int offset); +extern int _find_first_zero_bit_le(const unsigned long *p, unsigned size); +extern int _find_next_zero_bit_le(const unsigned long *p, int size, int offset); extern int _find_first_bit_le(const unsigned long *p, unsigned size); extern int _find_next_bit_le(const unsigned long *p, int size, int offset); /* * Big endian assembly bitops. nr = 0 -> byte 3 bit 0. */ -extern int _find_first_zero_bit_be(const void * p, unsigned size); -extern int _find_next_zero_bit_be(const void * p, int size, int offset); +extern int _find_first_zero_bit_be(const unsigned long *p, unsigned size); +extern int _find_next_zero_bit_be(const unsigned long *p, int size, int offset); extern int _find_first_bit_be(const unsigned long *p, unsigned size); extern int _find_next_bit_be(const unsigned long *p, int size, int offset); -- cgit v1.2.3 From fdfe7f4f9d856f98119132319512eba51cbee593 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 15 Feb 2017 11:15:20 +0100 Subject: ARM: dts: Add Actions Semi S500 and LeMaker Guitar MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Device Trees for Actions Semiconductor S500 SoC and LeMaker Guitar SoM and base board. Signed-off-by: Andreas Färber --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts | 26 ++++ arch/arm/boot/dts/owl-s500-guitar.dtsi | 22 ++++ arch/arm/boot/dts/owl-s500.dtsi | 176 +++++++++++++++++++++++++ 4 files changed, 226 insertions(+) create mode 100644 arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts create mode 100644 arch/arm/boot/dts/owl-s500-guitar.dtsi create mode 100644 arch/arm/boot/dts/owl-s500.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9c5e1d944d1c..9c19c3dd7a5a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -663,6 +663,8 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ orion5x-maxtor-shared-storage-2.dtb \ orion5x-netgear-wnr854t.dtb \ orion5x-rd88f5182-nas.dtb +dtb-$(CONFIG_ARCH_ACTIONS) += \ + owl-s500-guitar-bb-rev-b.dtb dtb-$(CONFIG_ARCH_PRIMA2) += \ prima2-evb.dtb dtb-$(CONFIG_ARCH_OXNAS) += \ diff --git a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts b/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts new file mode 100644 index 000000000000..521463d4cac6 --- /dev/null +++ b/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2016-2017 Andreas Färber + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include "owl-s500-guitar.dtsi" + +/ { + compatible = "lemaker,guitar-bb-rev-b", "lemaker,guitar", "actions,s500"; + model = "LeMaker Guitar Base Board rev. B"; + + aliases { + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/owl-s500-guitar.dtsi b/arch/arm/boot/dts/owl-s500-guitar.dtsi new file mode 100644 index 000000000000..079b2c02cc13 --- /dev/null +++ b/arch/arm/boot/dts/owl-s500-guitar.dtsi @@ -0,0 +1,22 @@ +/* + * LeMaker Guitar SoM + * + * Copyright (c) 2016-2017 Andreas Färber + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#include "owl-s500.dtsi" + +/ { + compatible = "lemaker,guitar", "actions,s500"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; +}; + +&timer { + clocks = <&hosc>; +}; diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi new file mode 100644 index 000000000000..fc9f71a4106a --- /dev/null +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -0,0 +1,176 @@ +/* + * Actions Semi S500 SoC + * + * Copyright (c) 2016-2017 Andreas Färber + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#include + +/ { + compatible = "actions,s500"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + }; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x1>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x3>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + hosc: hosc { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + scu: scu@b0020000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xb0020000 0x100>; + }; + + global_timer: timer@b0020200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xb0020200 0x100>; + interrupts = ; + status = "disabled"; + }; + + twd_timer: timer@b0020600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xb0020600 0x20>; + interrupts = ; + status = "disabled"; + }; + + twd_wdt: wdt@b0020620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0xb0020620 0xe0>; + interrupts = ; + status = "disabled"; + }; + + gic: interrupt-controller@b0021000 { + compatible = "arm,cortex-a9-gic"; + reg = <0xb0021000 0x1000>, + <0xb0020100 0x0100>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + l2: cache-controller@b0022000 { + compatible = "arm,pl310-cache"; + reg = <0xb0022000 0x1000>; + cache-unified; + cache-level = <2>; + interrupts = ; + arm,tag-latency = <3 3 2>; + arm,data-latency = <5 3 3>; + }; + + uart0: serial@b0120000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb0120000 0x2000>; + interrupts = ; + status = "disabled"; + }; + + uart1: serial@b0122000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb0122000 0x2000>; + interrupts = ; + status = "disabled"; + }; + + uart2: serial@b0124000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb0124000 0x2000>; + interrupts = ; + status = "disabled"; + }; + + uart3: serial@b0126000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb0126000 0x2000>; + interrupts = ; + status = "disabled"; + }; + + uart4: serial@b0128000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb0128000 0x2000>; + interrupts = ; + status = "disabled"; + }; + + uart5: serial@b012a000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb012a000 0x2000>; + interrupts = ; + status = "disabled"; + }; + + uart6: serial@b012c000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb012c000 0x2000>; + interrupts = ; + status = "disabled"; + }; + + timer: timer@b0168000 { + compatible = "actions,s500-timer"; + reg = <0xb0168000 0x8000>; + interrupts = , + , + , + ; + interrupt-names = "2hz0", "2hz1", "timer0", "timer1"; + }; + }; +}; -- cgit v1.2.3 From 4435f5dc5cf7b919c96ae0b283d3cca77d069682 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sun, 26 Feb 2017 12:07:00 +0900 Subject: ARM: prima2: remove redundant select CPU_V7 , Barry Song , linux-kernel@vger.kernel.org ARCH_ATLAS7 resides in "if ARCH_SIRF ... end", and ARCH_SIRF depends on ARCH_MULTI_V7, which selects CPU_V7. Signed-off-by: Masahiro Yamada Signed-off-by: Olof Johansson --- arch/arm/mach-prima2/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig index 85e874a97337..7426211bddaf 100644 --- a/arch/arm/mach-prima2/Kconfig +++ b/arch/arm/mach-prima2/Kconfig @@ -27,7 +27,6 @@ config ARCH_ATLAS7 bool "CSR SiRFSoC ATLAS7 ARM Cortex A7 Platform" default y select ARM_GIC - select CPU_V7 select ATLAS7_TIMER select HAVE_ARM_SCU if SMP select HAVE_SMP -- cgit v1.2.3 From d28bcd53fa90549e00f7dbcdfc885dfe8409e8a2 Mon Sep 17 00:00:00 2001 From: Alexandre TORGUE Date: Mon, 12 Jun 2017 14:22:45 +0200 Subject: ARM: stm32: Introduce MACH_STM32F469 flag This patch introduces the MACH_STM32F469 to make possible to only select STM32F469 pinctrl driver By default, all the MACH_STM32Fxxx flags will be set with STM32 defconfig. Signed-off-by: Alexandre TORGUE Signed-off-by: Olof Johansson --- arch/arm/mach-stm32/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index 2d1419eb0896..0d1889bbde58 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -15,6 +15,11 @@ config MACH_STM32F429 depends on ARCH_STM32 default y +config MACH_STM32F469 + bool "STMicrolectronics STM32F469" + depends on ARCH_STM32 + default y + config MACH_STM32F746 bool "STMicrolectronics STM32F746" depends on ARCH_STM32 -- cgit v1.2.3 From ad90c2bc1e67e43243376c981ab856a4134d5dcc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 26 Feb 2017 17:24:54 +0100 Subject: ARM: dts: owl-s500: Set CPU enable-method MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use a custom S500 enable-method for all CPUs. Signed-off-by: Andreas Färber --- arch/arm/boot/dts/owl-s500.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index fc9f71a4106a..6d6024027ee2 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -28,24 +28,28 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0x0>; + enable-method = "actions,s500-smp"; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0x1>; + enable-method = "actions,s500-smp"; }; cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0x2>; + enable-method = "actions,s500-smp"; }; cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0x3>; + enable-method = "actions,s500-smp"; }; }; -- cgit v1.2.3 From 740f6beb57b579ee69a3793dff1462a4020ec500 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 26 Feb 2017 04:08:53 +0100 Subject: ARM: dts: owl-s500: Add SPS node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Smart Power System node for PM domains. Signed-off-by: Andreas Färber --- arch/arm/boot/dts/owl-s500.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 6d6024027ee2..51a48741d4c0 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -176,5 +176,11 @@ ; interrupt-names = "2hz0", "2hz1", "timer0", "timer1"; }; + + sps: power-controller@b01b0100 { + compatible = "actions,s500-sps"; + reg = <0xb01b0100 0x100>; + #power-domain-cells = <1>; + }; }; }; -- cgit v1.2.3 From 868772d89d08a7743d24babbde33abea61022590 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Jun 2017 10:41:02 -0500 Subject: ARM: OMAP2+: DMA: Add slave map entries for 24xx external request lines The external request lines are used by tusb6010 on OMAP24xx platforms. Update the map so the driver can use dmaengine API to request the DMA channel. At the same time add temporary map containing only the external DMA request numbers for DT booted case on omap24xx since the tusb6010 stack is not yet supports DT boot. Signed-off-by: Peter Ujfalusi Acked-by: Tony Lindgren Signed-off-by: Bin Liu Signed-off-by: Greg Kroah-Hartman --- arch/arm/mach-omap2/dma.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index e58c13a9bea5..0b77a0176018 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -249,6 +249,24 @@ static const struct dma_slave_map omap24xx_sdma_map[] = { { "omap_uart.2", "rx", SDMA_FILTER_PARAM(54) }, { "omap_hsmmc.0", "tx", SDMA_FILTER_PARAM(61) }, { "omap_hsmmc.0", "rx", SDMA_FILTER_PARAM(62) }, + + /* external DMA requests when tusb6010 is used */ + { "musb-tusb", "dmareq0", SDMA_FILTER_PARAM(2) }, + { "musb-tusb", "dmareq1", SDMA_FILTER_PARAM(3) }, + { "musb-tusb", "dmareq2", SDMA_FILTER_PARAM(14) }, /* OMAP2420 only */ + { "musb-tusb", "dmareq3", SDMA_FILTER_PARAM(15) }, /* OMAP2420 only */ + { "musb-tusb", "dmareq4", SDMA_FILTER_PARAM(16) }, /* OMAP2420 only */ + { "musb-tusb", "dmareq5", SDMA_FILTER_PARAM(64) }, /* OMAP2420 only */ +}; + +static const struct dma_slave_map omap24xx_sdma_dt_map[] = { + /* external DMA requests when tusb6010 is used */ + { "musb-hdrc.1.auto", "dmareq0", SDMA_FILTER_PARAM(2) }, + { "musb-hdrc.1.auto", "dmareq1", SDMA_FILTER_PARAM(3) }, + { "musb-hdrc.1.auto", "dmareq2", SDMA_FILTER_PARAM(14) }, /* OMAP2420 only */ + { "musb-hdrc.1.auto", "dmareq3", SDMA_FILTER_PARAM(15) }, /* OMAP2420 only */ + { "musb-hdrc.1.auto", "dmareq4", SDMA_FILTER_PARAM(16) }, /* OMAP2420 only */ + { "musb-hdrc.1.auto", "dmareq5", SDMA_FILTER_PARAM(64) }, /* OMAP2420 only */ }; static const struct dma_slave_map omap3xxx_sdma_map[] = { @@ -346,6 +364,12 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) __func__); return -ENODEV; } + } else { + if (soc_is_omap24xx()) { + /* DMA slave map for drivers not yet converted to DT */ + p.slave_map = omap24xx_sdma_dt_map; + p.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map); + } } pdev = omap_device_build(name, 0, oh, &p, sizeof(p)); -- cgit v1.2.3 From ab723a6d9e22f5c1d82e34159c48c24febe79f77 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Fri, 9 Jun 2017 14:11:41 +0530 Subject: ARM: dts: omap3-overo: Remove "vqmmc-supply" property from MMC dt node commit 94647a30124e2c7 ("ARM: dts: omap3-overo: Enable WiFi/BT combo") while enabling WiFi/BT combo added regulator to trigger the nReset signal of the Bluetooth module in vqmmc-supply. However BT should be handled by UART. Moreover "vqmmc" is not a defined binding for omap_hsmmc. While "vqmmc" in mmc2 hasn't caused any issues so far, mmc2 will start to mis-behave once omap_hsmmc defines "vqmmc" binding. Remove "vqmmc-supply" property in mmc2 here. Signed-off-by: Kishon Vijay Abraham I Acked-by: Tony Lindgren Signed-off-by: Ulf Hansson --- arch/arm/boot/dts/omap3-overo-base.dtsi | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi index 401fae838fe9..cd220342a805 100644 --- a/arch/arm/boot/dts/omap3-overo-base.dtsi +++ b/arch/arm/boot/dts/omap3-overo-base.dtsi @@ -74,16 +74,6 @@ gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* gpio_16: WiFi nReset */ startup-delay-us = <10000>; }; - - /* Regulator to trigger the nReset signal of the Bluetooth module */ - w3cbw003c_bt_nreset: regulator-w3cbw003c-bt-nreset { - compatible = "regulator-fixed"; - regulator-name = "regulator-w3cbw003c-bt-nreset"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio_164: BT nReset */ - startup-delay-us = <10000>; - }; }; &omap3_pmx_core { @@ -191,7 +181,6 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; vmmc-supply = <&w3cbw003c_npoweron>; - vqmmc-supply = <&w3cbw003c_bt_nreset>; vmmc_aux-supply = <&w3cbw003c_wifi_nreset>; bus-width = <4>; cap-sdio-irq; -- cgit v1.2.3 From dceb1a6819ab2c8b5564354543447b1af4fccedd Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Sun, 21 May 2017 13:15:13 +0200 Subject: xen-swiotlb: consolidate xen_swiotlb_dma_ops ARM and x86 had duplicated versions of the dma_ops structure, the only difference is that x86 hasn't wired up the set_dma_mask, mmap, and get_sgtable ops yet. On x86 all of them are identical to the generic version, so they aren't needed but harmless. All the symbols used only for xen_swiotlb_dma_ops can now be marked static as well. Signed-off-by: Christoph Hellwig Reviewed-by: Konrad Rzeszutek Wilk --- arch/arm/xen/mm.c | 17 ----------------- 1 file changed, 17 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/xen/mm.c b/arch/arm/xen/mm.c index f0325d96b97a..785d2a562a23 100644 --- a/arch/arm/xen/mm.c +++ b/arch/arm/xen/mm.c @@ -185,23 +185,6 @@ EXPORT_SYMBOL_GPL(xen_destroy_contiguous_region); const struct dma_map_ops *xen_dma_ops; EXPORT_SYMBOL(xen_dma_ops); -static const struct dma_map_ops xen_swiotlb_dma_ops = { - .alloc = xen_swiotlb_alloc_coherent, - .free = xen_swiotlb_free_coherent, - .sync_single_for_cpu = xen_swiotlb_sync_single_for_cpu, - .sync_single_for_device = xen_swiotlb_sync_single_for_device, - .sync_sg_for_cpu = xen_swiotlb_sync_sg_for_cpu, - .sync_sg_for_device = xen_swiotlb_sync_sg_for_device, - .map_sg = xen_swiotlb_map_sg_attrs, - .unmap_sg = xen_swiotlb_unmap_sg_attrs, - .map_page = xen_swiotlb_map_page, - .unmap_page = xen_swiotlb_unmap_page, - .dma_supported = xen_swiotlb_dma_supported, - .set_dma_mask = xen_swiotlb_set_dma_mask, - .mmap = xen_swiotlb_dma_mmap, - .get_sgtable = xen_swiotlb_get_sgtable, -}; - int __init xen_mm_init(void) { struct gnttab_cache_flush cflush; -- cgit v1.2.3 From 1b3b22507e0d45dedc6a54b26d56e0b8c4d36875 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 16 Jun 2017 01:22:38 -0700 Subject: ARM/hw_breakpoint: Fix possible recursive locking for arch_hw_breakpoint_init Recent change to use cpuhp_setup_state_cpuslocked() with commit fe2a5cd8aa03 ("ARM/hw_breakpoint: Use cpuhp_setup_state_cpuslocked()") missed to change the related paired cpuhp_remove_state_nocalls_cpuslocked(). Now if arch_hw_breakpoint_init() fails, we get "WARNING: possible recursive locking detected" on the exit path. Fixes: fe2a5cd8aa03 ("ARM/hw_breakpoint: Use cpuhp_setup_state_cpuslocked()") Signed-off-by: Tony Lindgren Acked-by: Sebastian Andrzej Siewior Cc: Mark Rutland Cc: linux-omap@vger.kernel.org Cc: Peter Zijlstra Cc: Will Deacon Cc: Steven Rostedt Cc: Russell King Cc: "Paul E . McKenney" Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/20170616082238.15553-1-tony@atomide.com Signed-off-by: Thomas Gleixner --- arch/arm/kernel/hw_breakpoint.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index 63cb4c7c6593..af2a7f1e3103 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -1106,7 +1106,7 @@ static int __init arch_hw_breakpoint_init(void) core_num_brps = 0; core_num_wrps = 0; if (ret > 0) - cpuhp_remove_state_nocalls(ret); + cpuhp_remove_state_nocalls_cpuslocked(ret); cpus_read_unlock(); return 0; } -- cgit v1.2.3 From 280e87e98c09b85b617c7b2752c8b504c4ea98f6 Mon Sep 17 00:00:00 2001 From: Dmitry Safonov Date: Mon, 19 Jun 2017 17:32:42 +0100 Subject: ARM: 8683/1: ARM32: Support mremap() for sigpage/vDSO CRIU restores application mappings on the same place where they were before Checkpoint. That means, that we need to move vDSO and sigpage during restore on exactly the same place where they were before C/R. Make mremap() code update mm->context.{sigpage,vdso} pointers during VMA move. Sigpage is used for landing after handling a signal - if the pointer is not updated during moving, the application might crash on any signal after mremap(). vDSO pointer on ARM32 is used only for setting auxv at this moment, update it during mremap() in case of future usage. Without those updates, current work of CRIU on ARM32 is not reliable. Historically, we error Checkpointing if we find vDSO page on ARM32 and suggest user to disable CONFIG_VDSO. But that's not correct - it goes from x86 where signal processing is ended in vDSO blob. For arm32 it's sigpage, which is not disabled with `CONFIG_VDSO=n'. Looks like C/R was working by luck - because userspace on ARM32 at this moment always sets SA_RESTORER. Signed-off-by: Dmitry Safonov Acked-by: Andy Lutomirski Cc: linux-arm-kernel@lists.infradead.org Cc: Will Deacon Cc: Thomas Gleixner Cc: Cyrill Gorcunov Cc: Pavel Emelyanov Cc: Christopher Covington Signed-off-by: Russell King --- arch/arm/kernel/process.c | 8 ++++++++ arch/arm/kernel/vdso.c | 18 ++++++++++++++++++ 2 files changed, 26 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 151cece4a293..d96714e1858c 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -404,9 +404,17 @@ static unsigned long sigpage_addr(const struct mm_struct *mm, static struct page *signal_page; extern struct page *get_signal_page(void); +static int sigpage_mremap(const struct vm_special_mapping *sm, + struct vm_area_struct *new_vma) +{ + current->mm->context.sigpage = new_vma->vm_start; + return 0; +} + static const struct vm_special_mapping sigpage_mapping = { .name = "[sigpage]", .pages = &signal_page, + .mremap = sigpage_mremap, }; int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) diff --git a/arch/arm/kernel/vdso.c b/arch/arm/kernel/vdso.c index 53cf86cf2d1a..a4d6dc0f2427 100644 --- a/arch/arm/kernel/vdso.c +++ b/arch/arm/kernel/vdso.c @@ -54,8 +54,26 @@ static const struct vm_special_mapping vdso_data_mapping = { .pages = &vdso_data_page, }; +static int vdso_mremap(const struct vm_special_mapping *sm, + struct vm_area_struct *new_vma) +{ + unsigned long new_size = new_vma->vm_end - new_vma->vm_start; + unsigned long vdso_size; + + /* without VVAR page */ + vdso_size = (vdso_total_pages - 1) << PAGE_SHIFT; + + if (vdso_size != new_size) + return -EINVAL; + + current->mm->context.vdso = new_vma->vm_start; + + return 0; +} + static struct vm_special_mapping vdso_text_mapping __ro_after_init = { .name = "[vdso]", + .mremap = vdso_mremap, }; struct elfinfo { -- cgit v1.2.3 From a87027196803227dd9f4ee848f4aa2dbfe699c4c Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Thu, 20 Apr 2017 16:25:08 +0530 Subject: ARM: pxa: Use - instead of @ for DT OPP entries Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by: Krzysztof Kozlowski Reported-by: Masahiro Yamada Suggested-by: Mark Rutland Signed-off-by: Viresh Kumar Acked-by: Rob Herring Signed-off-by: Robert Jarzmik --- arch/arm/boot/dts/pxa25x.dtsi | 8 ++++---- arch/arm/boot/dts/pxa27x.dtsi | 14 +++++++------- 2 files changed, 11 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/pxa25x.dtsi b/arch/arm/boot/dts/pxa25x.dtsi index f9f4726396a0..95d59be97213 100644 --- a/arch/arm/boot/dts/pxa25x.dtsi +++ b/arch/arm/boot/dts/pxa25x.dtsi @@ -93,22 +93,22 @@ pxa250_opp_table: opp_table0 { compatible = "operating-points-v2"; - opp@99532800 { + opp-99532800 { opp-hz = /bits/ 64 <99532800>; opp-microvolt = <1000000 950000 1650000>; clock-latency-ns = <20>; }; - opp@199065600 { + opp-199065600 { opp-hz = /bits/ 64 <199065600>; opp-microvolt = <1000000 950000 1650000>; clock-latency-ns = <20>; }; - opp@298598400 { + opp-298598400 { opp-hz = /bits/ 64 <298598400>; opp-microvolt = <1100000 1045000 1650000>; clock-latency-ns = <20>; }; - opp@398131200 { + opp-398131200 { opp-hz = /bits/ 64 <398131200>; opp-microvolt = <1300000 1235000 1650000>; clock-latency-ns = <20>; diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi index e0fab48ba6fa..5f1d6da02a4c 100644 --- a/arch/arm/boot/dts/pxa27x.dtsi +++ b/arch/arm/boot/dts/pxa27x.dtsi @@ -141,37 +141,37 @@ pxa270_opp_table: opp_table0 { compatible = "operating-points-v2"; - opp@104000000 { + opp-104000000 { opp-hz = /bits/ 64 <104000000>; opp-microvolt = <900000 900000 1705000>; clock-latency-ns = <20>; }; - opp@156000000 { + opp-156000000 { opp-hz = /bits/ 64 <156000000>; opp-microvolt = <1000000 1000000 1705000>; clock-latency-ns = <20>; }; - opp@208000000 { + opp-208000000 { opp-hz = /bits/ 64 <208000000>; opp-microvolt = <1180000 1180000 1705000>; clock-latency-ns = <20>; }; - opp@312000000 { + opp-312000000 { opp-hz = /bits/ 64 <312000000>; opp-microvolt = <1250000 1250000 1705000>; clock-latency-ns = <20>; }; - opp@416000000 { + opp-416000000 { opp-hz = /bits/ 64 <416000000>; opp-microvolt = <1350000 1350000 1705000>; clock-latency-ns = <20>; }; - opp@520000000 { + opp-520000000 { opp-hz = /bits/ 64 <520000000>; opp-microvolt = <1450000 1450000 1705000>; clock-latency-ns = <20>; }; - opp@624000000 { + opp-624000000 { opp-hz = /bits/ 64 <624000000>; opp-microvolt = <1550000 1550000 1705000>; clock-latency-ns = <20>; -- cgit v1.2.3 From 139358be24e526bc8d050e319cdd4e2d1941503e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 9 May 2017 08:20:03 -0500 Subject: ARM: socfpga: Increase max number of GPIOs Increase the maximum number of GPIOs on SoCFPGA as this platform can have many GPIO controllers in the FPGA part. Signed-off-by: Marek Vasut Signed-off-by: Dinh Nguyen --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4c1a35f15838..108c203a8b29 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1460,6 +1460,7 @@ config ARM_PSCI # selected platforms. config ARCH_NR_GPIO int + default 2048 if ARCH_SOCFPGA default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \ ARCH_ZYNQ default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ -- cgit v1.2.3 From 6bb8536cba152edee005668bc57cfe6198b73f0f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 15 Feb 2017 11:03:22 +0100 Subject: ARM: Prepare Actions Semi S500 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add ARCH_ACTIONS and mach-actions/owl.c for "actions,s500". Signed-off-by: Andreas Färber --- arch/arm/Kconfig | 2 ++ arch/arm/Makefile | 1 + arch/arm/mach-actions/Kconfig | 15 +++++++++++++++ arch/arm/mach-actions/Makefile | 1 + arch/arm/mach-actions/owl.c | 28 ++++++++++++++++++++++++++++ 5 files changed, 47 insertions(+) create mode 100644 arch/arm/mach-actions/Kconfig create mode 100644 arch/arm/mach-actions/Makefile create mode 100644 arch/arm/mach-actions/owl.c (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4c1a35f15838..869c3f98f7a2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -711,6 +711,8 @@ config ARCH_VIRT # source "arch/arm/mach-mvebu/Kconfig" +source "arch/arm/mach-actions/Kconfig" + source "arch/arm/mach-alpine/Kconfig" source "arch/arm/mach-artpec/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 65f4e2a4eb94..47d3a1ab08d2 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -151,6 +151,7 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000 # Machine directory name. This list is sorted alphanumerically # by CONFIG_* macro name. +machine-$(CONFIG_ARCH_ACTIONS) += actions machine-$(CONFIG_ARCH_ALPINE) += alpine machine-$(CONFIG_ARCH_ARTPEC) += artpec machine-$(CONFIG_ARCH_AT91) += at91 diff --git a/arch/arm/mach-actions/Kconfig b/arch/arm/mach-actions/Kconfig new file mode 100644 index 000000000000..717adc1630a1 --- /dev/null +++ b/arch/arm/mach-actions/Kconfig @@ -0,0 +1,15 @@ +menuconfig ARCH_ACTIONS + bool "Actions Semi SoCs" + depends on ARCH_MULTI_V7 + select ARM_AMBA + select ARM_GIC + select ARM_GLOBAL_TIMER + select CACHE_L2X0 + select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK + select COMMON_CLK + select GENERIC_IRQ_CHIP + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if SMP + select OWL_TIMER + help + This enables support for the Actions Semiconductor S500 SoC family. diff --git a/arch/arm/mach-actions/Makefile b/arch/arm/mach-actions/Makefile new file mode 100644 index 000000000000..561b0f39e3f8 --- /dev/null +++ b/arch/arm/mach-actions/Makefile @@ -0,0 +1 @@ +obj-y += owl.o diff --git a/arch/arm/mach-actions/owl.c b/arch/arm/mach-actions/owl.c new file mode 100644 index 000000000000..4ac4a860f3d6 --- /dev/null +++ b/arch/arm/mach-actions/owl.c @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2017 Andreas Färber + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include + +static const char * const owl_dt_compat[] = { + "actions,s500", + NULL +}; + +DT_MACHINE_START(OWL, "Actions Semi Owl platform") + .dt_compat = owl_dt_compat, + .l2c_aux_val = 0, + .l2c_aux_mask = ~0, +MACHINE_END -- cgit v1.2.3 From 172067e0bc8721af3e8626596f91b03f691e88a8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 26 Feb 2017 17:25:21 +0100 Subject: ARM: owl: Implement CPU enable-method for S500 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Allow to bring up CPU1. Based on LeMaker linux-actions tree. Signed-off-by: Andreas Färber --- arch/arm/mach-actions/Makefile | 3 + arch/arm/mach-actions/headsmp.S | 68 ++++++++++++++++ arch/arm/mach-actions/platsmp.c | 166 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 237 insertions(+) create mode 100644 arch/arm/mach-actions/headsmp.S create mode 100644 arch/arm/mach-actions/platsmp.c (limited to 'arch/arm') diff --git a/arch/arm/mach-actions/Makefile b/arch/arm/mach-actions/Makefile index 561b0f39e3f8..eeb3896e4952 100644 --- a/arch/arm/mach-actions/Makefile +++ b/arch/arm/mach-actions/Makefile @@ -1 +1,4 @@ obj-y += owl.o +obj-${CONFIG_SMP} += platsmp.o headsmp.o + +AFLAGS_headsmp.o := -Wa,-march=armv7-a diff --git a/arch/arm/mach-actions/headsmp.S b/arch/arm/mach-actions/headsmp.S new file mode 100644 index 000000000000..dc4832fc101a --- /dev/null +++ b/arch/arm/mach-actions/headsmp.S @@ -0,0 +1,68 @@ +/* + * Copyright 2012 Actions Semi Inc. + * Author: Actions Semi, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +ENTRY(owl_v7_invalidate_l1) + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache + mcr p15, 2, r0, c0, c0, 0 + mrc p15, 1, r0, c0, c0, 0 + + ldr r1, =0x7fff + and r2, r1, r0, lsr #13 + + ldr r1, =0x3ff + + and r3, r1, r0, lsr #3 @ NumWays - 1 + add r2, r2, #1 @ NumSets + + and r0, r0, #0x7 + add r0, r0, #4 @ SetShift + + clz r1, r3 @ WayShift + add r4, r3, #1 @ NumWays +1: sub r2, r2, #1 @ NumSets-- + mov r3, r4 @ Temp = NumWays +2: subs r3, r3, #1 @ Temp-- + mov r5, r3, lsl r1 + mov r6, r2, lsl r0 + orr r5, r5, r6 @ Reg = (Temp< +#include +#include +#include +#include +#include +#include +#include + +#define OWL_CPU1_ADDR 0x50 +#define OWL_CPU1_FLAG 0x5c + +#define OWL_CPUx_FLAG_BOOT 0x55aa + +static void __iomem *scu_base_addr; +static void __iomem *timer_base_addr; +static int ncores; + +static DEFINE_SPINLOCK(boot_lock); + +static void write_pen_release(int val) +{ + pen_release = val; + smp_wmb(); + __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); +} + +static void s500_smp_secondary_init(unsigned int cpu) +{ + /* + * let the primary processor know we're out of the + * pen, then head off into the C entry point + */ + write_pen_release(-1); + + spin_lock(&boot_lock); + spin_unlock(&boot_lock); +} + +void owl_secondary_startup(void); + +static int s500_wakeup_secondary(unsigned int cpu) +{ + if (cpu > 3) + return -EINVAL; + + switch (cpu) { + case 2: + case 3: + /* CPU2/3 are power-gated */ + return -EINVAL; + } + + /* wait for CPUx to run to WFE instruction */ + udelay(200); + + writel(virt_to_phys(owl_secondary_startup), + timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4); + writel(OWL_CPUx_FLAG_BOOT, + timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4); + + dsb_sev(); + mb(); + + return 0; +} + +static int s500_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned long timeout; + int ret; + + ret = s500_wakeup_secondary(cpu); + if (ret) + return ret; + + udelay(10); + + spin_lock(&boot_lock); + + /* + * The secondary processor is waiting to be released from + * the holding pen - release it, then wait for it to flag + * that it has been released by resetting pen_release. + */ + write_pen_release(cpu_logical_map(cpu)); + smp_send_reschedule(cpu); + + timeout = jiffies + (1 * HZ); + while (time_before(jiffies, timeout)) { + if (pen_release == -1) + break; + } + + writel(0, timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4); + writel(0, timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4); + + spin_unlock(&boot_lock); + + return pen_release != -1 ? -ENOSYS : 0; +} + +static void __init s500_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *node; + + node = of_find_compatible_node(NULL, NULL, "actions,s500-timer"); + if (!node) { + pr_err("%s: missing timer\n", __func__); + return; + } + + timer_base_addr = of_iomap(node, 0); + if (!timer_base_addr) { + pr_err("%s: could not map timer registers\n", __func__); + return; + } + + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { + node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); + if (!node) { + pr_err("%s: missing scu\n", __func__); + return; + } + + scu_base_addr = of_iomap(node, 0); + if (!scu_base_addr) { + pr_err("%s: could not map scu registers\n", __func__); + return; + } + + /* + * While the number of cpus is gathered from dt, also get the + * number of cores from the scu to verify this value when + * booting the cores. + */ + ncores = scu_get_core_count(scu_base_addr); + pr_debug("%s: ncores %d\n", __func__, ncores); + + scu_enable(scu_base_addr); + } +} + +static const struct smp_operations s500_smp_ops __initconst = { + .smp_prepare_cpus = s500_smp_prepare_cpus, + .smp_secondary_init = s500_smp_secondary_init, + .smp_boot_secondary = s500_smp_boot_secondary, +}; +CPU_METHOD_OF_DECLARE(s500_smp, "actions,s500-smp", &s500_smp_ops); -- cgit v1.2.3 From ae3f4151737d2aad271e5b1f2553c5d56e52850c Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 9 Jun 2017 17:29:52 +0900 Subject: kbuild: replace genhdr-y with generated-y Originally, generated-y and genhdr-y had different meaning, like follows: - generated-y: generated headers (other than asm-generic wrappers) - header-y : headers to be exported - genhdr-y : generated headers to be exported (generated-y + header-y) Since commit fcc8487d477a ("uapi: export all headers under uapi directories"), headers under UAPI directories are all exported. So, there is no more difference between generated-y and genhdr-y. We see two users of genhdr-y, arch/{arm,x86}/include/uapi/asm/Kbuild. They generate some headers in arch/{arm,x86}/include/generated/uapi/asm directories, which are obviously exported. Replace them with generated-y, and abolish genhdr-y. Signed-off-by: Masahiro Yamada Acked-by: Nicolas Dichtel --- arch/arm/include/uapi/asm/Kbuild | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/uapi/asm/Kbuild b/arch/arm/include/uapi/asm/Kbuild index 607f702c2d62..424935e4515d 100644 --- a/arch/arm/include/uapi/asm/Kbuild +++ b/arch/arm/include/uapi/asm/Kbuild @@ -1,6 +1,6 @@ # UAPI Header export list include include/uapi/asm-generic/Kbuild.asm -genhdr-y += unistd-common.h -genhdr-y += unistd-oabi.h -genhdr-y += unistd-eabi.h +generated-y += unistd-common.h +generated-y += unistd-oabi.h +generated-y += unistd-eabi.h -- cgit v1.2.3 From 621f48e40ee9b0100a802531069166d7d94796e0 Mon Sep 17 00:00:00 2001 From: Tyler Baicar Date: Wed, 21 Jun 2017 12:17:14 -0600 Subject: arm/arm64: KVM: add guest SEA support Currently external aborts are unsupported by the guest abort handling. Add handling for SEAs so that the host kernel reports SEAs which occur in the guest kernel. When an SEA occurs in the guest kernel, the guest exits and is routed to kvm_handle_guest_abort(). Prior to this patch, a print message of an unsupported FSC would be printed and nothing else would happen. With this patch, the code gets routed to the APEI handling of SEAs in the host kernel to report the SEA information. Signed-off-by: Tyler Baicar Acked-by: Catalin Marinas Acked-by: Marc Zyngier Acked-by: Christoffer Dall Signed-off-by: Will Deacon --- arch/arm/include/asm/kvm_arm.h | 10 ++++++++++ arch/arm/include/asm/system_misc.h | 5 +++++ 2 files changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h index a3f0b3d50089..ebf020b02bc8 100644 --- a/arch/arm/include/asm/kvm_arm.h +++ b/arch/arm/include/asm/kvm_arm.h @@ -187,6 +187,16 @@ #define FSC_FAULT (0x04) #define FSC_ACCESS (0x08) #define FSC_PERM (0x0c) +#define FSC_SEA (0x10) +#define FSC_SEA_TTW0 (0x14) +#define FSC_SEA_TTW1 (0x15) +#define FSC_SEA_TTW2 (0x16) +#define FSC_SEA_TTW3 (0x17) +#define FSC_SECC (0x18) +#define FSC_SECC_TTW0 (0x1c) +#define FSC_SECC_TTW1 (0x1d) +#define FSC_SECC_TTW2 (0x1e) +#define FSC_SECC_TTW3 (0x1f) /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ #define HPFAR_MASK (~0xf) diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h index a3d61ad984af..8c4a89f5ce7d 100644 --- a/arch/arm/include/asm/system_misc.h +++ b/arch/arm/include/asm/system_misc.h @@ -22,6 +22,11 @@ extern void (*arm_pm_idle)(void); extern unsigned int user_debug; +static inline int handle_guest_sea(phys_addr_t addr, unsigned int esr) +{ + return -1; +} + #endif /* !__ASSEMBLY__ */ #endif /* __ASM_ARM_SYSTEM_MISC_H */ -- cgit v1.2.3 From b8d9b3e407d16ccdc7d256af449e7d250074b5f4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 9 May 2017 08:35:36 -0500 Subject: ARM: dts: socfpga: Fix the ethernet clock phandle The ethernet block clock phandle must point to the clock node which represents the clock which directly supply the ethernet block. This is emac_x_clk , not emacx_clk , so fix this. From: Pavel Machek Signed-off-by: Marek Vasut Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index b2674bdb8e6a..7e24dc8e82d4 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -557,7 +557,7 @@ interrupts = <0 115 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ - clocks = <&emac0_clk>; + clocks = <&emac_0_clk>; clock-names = "stmmaceth"; resets = <&rst EMAC0_RESET>; reset-names = "stmmaceth"; @@ -575,7 +575,7 @@ interrupts = <0 120 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ - clocks = <&emac1_clk>; + clocks = <&emac_1_clk>; clock-names = "stmmaceth"; resets = <&rst EMAC1_RESET>; reset-names = "stmmaceth"; -- cgit v1.2.3 From 79528279c0cc946d11c9920788391bcb24582991 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 9 May 2017 08:58:50 -0500 Subject: ARM: dts: socfpga: Enable QSPI support on VINING FPGA Enable the QSPI node and add the flash chips. Signed-off-by: Marek Vasut Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts index 893198049397..cb4bdbcf54ee 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts @@ -300,6 +300,44 @@ }; }; +&qspi { + status = "okay"; + + n25q128@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128"; + reg = <0>; /* chip select */ + spi-max-frequency = <100000000>; + m25p,fast-read; + + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; + + n25q00@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00"; + reg = <1>; /* chip select */ + spi-max-frequency = <100000000>; + m25p,fast-read; + + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; +}; + &usb0 { dr_mode = "host"; status = "okay"; -- cgit v1.2.3 From ff3d90decb64fd90598cca8244d2c67e452d793e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 9 May 2017 09:02:33 -0500 Subject: ARM: dts: socfpga: Remove I2C EEPROMs from VINING FPGA Remove the EEPROMs attached to the I2C expander ports which lead to the backplane slots from the main VIN|ING DTS file. These EEPROMs are bound using separate DTO files, which lets us handle both two-slot and six-slot configuration of the backplane. Signed-off-by: Marek Vasut Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 34 ++-------------------- 1 file changed, 2 insertions(+), 32 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts index cb4bdbcf54ee..268785ecb82a 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts @@ -203,69 +203,39 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; - eeprom@51 { - compatible = "at,24c01"; - pagesize = <8>; - reg = <0x51>; - }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; - eeprom@51 { - compatible = "at,24c01"; - pagesize = <8>; - reg = <0x51>; - }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; - eeprom@51 { - compatible = "at,24c01"; - pagesize = <8>; - reg = <0x51>; - }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; - eeprom@51 { - compatible = "at,24c01"; - pagesize = <8>; - reg = <0x51>; - }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; - eeprom@51 { - compatible = "at,24c01"; - pagesize = <8>; - reg = <0x51>; - }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; - eeprom@51 { - compatible = "at,24c01"; - pagesize = <8>; - reg = <0x51>; - }; }; - i2c@6 { + i2c@6 { /* Backplane EEPROM */ #address-cells = <1>; #size-cells = <0>; reg = <6>; @@ -276,7 +246,7 @@ }; }; - i2c@7 { + i2c@7 { /* Power board EEPROM */ #address-cells = <1>; #size-cells = <0>; reg = <7>; -- cgit v1.2.3 From 3ca65aa18f15c75677affcbc8654c86e5dc6d87f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 9 May 2017 09:06:06 -0500 Subject: ARM: dts: socfpga: Drop LED node from VINING FPGA Drop the LED node from VINing FPGA DT because the LED wiring is different on each mainboard revision. This wiring is therefore handled in mainboard DT Overlays. Signed-off-by: Marek Vasut Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 28 ---------------------- 1 file changed, 28 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts index 268785ecb82a..9195f11dacdc 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts @@ -71,34 +71,6 @@ ethernet0 = &gmac1; }; - leds { - compatible = "gpio-leds"; - - hps_led0 { - label = "hps:green:led0"; /* ALIVE_LED_GR */ - gpios = <&portb 19 0>; /* HPS_GPIO48 */ - linux,default-trigger = "heartbeat"; - }; - - hps_led1 { - label = "hps:red:led0"; /* ALIVE_LED_RD */ - gpios = <&portb 24 0>; /* HPS_GPIO53 */ - linux,default-trigger = "none"; - }; - - hps_led2 { - label = "hps:green:led1"; /* LINK2HOST_LED_GR */ - gpios = <&portb 25 0>; /* HPS_GPIO54 */ - linux,default-trigger = "heartbeat"; - }; - - hps_led3 { - label = "hps:red:led1"; /* LINK2HOST_LED_RD */ - gpios = <&portc 7 0>; /* HPS_GPIO65 */ - linux,default-trigger = "none"; - }; - }; - gpio-keys { compatible = "gpio-keys"; -- cgit v1.2.3 From 5b5ada57e4df56940d4855069754460b31666806 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 9 May 2017 09:07:57 -0500 Subject: ARM: dts: socfpga: Add second ethernet alias to VINING FPGA Add DT alias for the second ethernet present on mainboard rev 1.10. Signed-off-by: Marek Vasut Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts index 9195f11dacdc..655fe87e272d 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts @@ -69,6 +69,7 @@ * to be added to the gmac1 device tree blob. */ ethernet0 = &gmac1; + ethernet1 = &gmac0; }; gpio-keys { -- cgit v1.2.3 From 3c56909ec2672d74d30f32f1c0ed8cfd7d6e2b14 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 9 May 2017 09:21:08 -0500 Subject: ARM: dts: socfpga: set the i2c frequency Use 'clock-frequency' binding for the i2c node that will put the I2C driver into the standard operating mode. 'speed-mode' was not a valid binding for the I2C driver, remove it. Signed-off-by: Alan Tull Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 2 +- arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts | 2 +- arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 94e088473823..3a32de9ded3b 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -130,13 +130,13 @@ }; &i2c1 { - speed-mode = <0>; status = "okay"; /* * adjust the falling times to decrease the i2c frequency to 50Khz * because the LCD module does not work at the standard 100Khz */ + clock-frequency = <100000>; i2c-sda-falling-time-ns = <6000>; i2c-scl-falling-time-ns = <6000>; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts index 7b49395452b6..b280e6494193 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts @@ -86,7 +86,7 @@ &i2c0 { status = "okay"; - speed-mode = <0>; + clock-frequency = <100000>; adxl345: adxl345@0 { compatible = "adi,adxl345"; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts index 21e397287e29..c2eb88aab8b3 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts @@ -58,7 +58,7 @@ &i2c0 { status = "okay"; - speed-mode = <0>; + clock-frequency = <100000>; stmpe1: stmpe811@41 { compatible = "st,stmpe811"; -- cgit v1.2.3 From b6a0e18ca690c2398661c42b942187621ab77e36 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 28 Feb 2017 01:08:37 +0100 Subject: ARM: owl: smp: Implement SPS power-gating for CPU2 and CPU3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Bring up the two remaining CPUs by calling into PM domain code. Signed-off-by: Andreas Färber --- arch/arm/mach-actions/Kconfig | 1 + arch/arm/mach-actions/platsmp.c | 36 ++++++++++++++++++++++++++++++++++-- 2 files changed, 35 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-actions/Kconfig b/arch/arm/mach-actions/Kconfig index 717adc1630a1..ad9c5c89c683 100644 --- a/arch/arm/mach-actions/Kconfig +++ b/arch/arm/mach-actions/Kconfig @@ -10,6 +10,7 @@ menuconfig ARCH_ACTIONS select GENERIC_IRQ_CHIP select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP + select OWL_PM_DOMAINS_HELPER select OWL_TIMER help This enables support for the Actions Semiconductor S500 SoC family. diff --git a/arch/arm/mach-actions/platsmp.c b/arch/arm/mach-actions/platsmp.c index 9d3601ebe535..b4806ce0e9bb 100644 --- a/arch/arm/mach-actions/platsmp.c +++ b/arch/arm/mach-actions/platsmp.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -28,7 +29,13 @@ #define OWL_CPUx_FLAG_BOOT 0x55aa +#define OWL_SPS_PG_CTL_PWR_CPU2 BIT(5) +#define OWL_SPS_PG_CTL_PWR_CPU3 BIT(6) +#define OWL_SPS_PG_CTL_ACK_CPU2 BIT(21) +#define OWL_SPS_PG_CTL_ACK_CPU3 BIT(22) + static void __iomem *scu_base_addr; +static void __iomem *sps_base_addr; static void __iomem *timer_base_addr; static int ncores; @@ -58,14 +65,27 @@ void owl_secondary_startup(void); static int s500_wakeup_secondary(unsigned int cpu) { + int ret; + if (cpu > 3) return -EINVAL; + /* The generic PM domain driver is not available this early. */ switch (cpu) { case 2: + ret = owl_sps_set_pg(sps_base_addr, + OWL_SPS_PG_CTL_PWR_CPU2, + OWL_SPS_PG_CTL_ACK_CPU2, true); + if (ret) + return ret; + break; case 3: - /* CPU2/3 are power-gated */ - return -EINVAL; + ret = owl_sps_set_pg(sps_base_addr, + OWL_SPS_PG_CTL_PWR_CPU3, + OWL_SPS_PG_CTL_ACK_CPU3, true); + if (ret) + return ret; + break; } /* wait for CPUx to run to WFE instruction */ @@ -133,6 +153,18 @@ static void __init s500_smp_prepare_cpus(unsigned int max_cpus) return; } + node = of_find_compatible_node(NULL, NULL, "actions,s500-sps"); + if (!node) { + pr_err("%s: missing sps\n", __func__); + return; + } + + sps_base_addr = of_iomap(node, 0); + if (!sps_base_addr) { + pr_err("%s: could not map sps registers\n", __func__); + return; + } + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); if (!node) { -- cgit v1.2.3 From 7f794788dbf9e1a9ca9a5c1cc0a90642f3b4e4ce Mon Sep 17 00:00:00 2001 From: Bhushan Shah Date: Thu, 15 Jun 2017 11:45:21 +0530 Subject: ARM: qcom_defconfig: enable RPMSG_QCOM_SMD As of commit 5052de8deff56, QCOM_SMD_RPM and various other config options enabled in the qcom_defconfig depends on the RPMSG. If QCOM_SMD_RPM config option is not selected it disables the REGULATOR_QCOM_SMD_RPM and other essential config options. Signed-off-by: Bhushan Shah Signed-off-by: Andy Gross --- arch/arm/configs/qcom_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig index 33f248058284..cd7b9f02899b 100644 --- a/arch/arm/configs/qcom_defconfig +++ b/arch/arm/configs/qcom_defconfig @@ -174,6 +174,7 @@ CONFIG_LEDS_GPIO=y CONFIG_LEDS_PM8058=y CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_RPMSG_QCOM_SMD=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_PM8XXX=y CONFIG_DMADEVICES=y -- cgit v1.2.3 From cd83935be8f5c28ea099ad1efa6321c737e2e12a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=A9my=20Lefaure?= Date: Fri, 23 Jun 2017 11:21:43 +0100 Subject: ARM: 8684/1: NOMMU: Remove unused KTHREAD_SIZE definition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I didn't find any use of this macro in the current kernel tree (with git grep). KTHREAD_SIZE is no longer used for a very very long time. So let's remove this definition. Signed-off-by: Jérémy Lefaure Reviewed-by: Vladimir Murzin Signed-off-by: Russell King --- arch/arm/include/asm/page-nommu.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/page-nommu.h b/arch/arm/include/asm/page-nommu.h index 503f488053de..8f2c47bec375 100644 --- a/arch/arm/include/asm/page-nommu.h +++ b/arch/arm/include/asm/page-nommu.h @@ -11,12 +11,6 @@ #ifndef _ASMARM_PAGE_NOMMU_H #define _ASMARM_PAGE_NOMMU_H -#if !defined(CONFIG_SMALL_TASKS) && PAGE_SHIFT < 13 -#define KTHREAD_SIZE (8192) -#else -#define KTHREAD_SIZE PAGE_SIZE -#endif - #define clear_page(page) memset((page), 0, PAGE_SIZE) #define copy_page(to,from) memcpy((to), (from), PAGE_SIZE) -- cgit v1.2.3 From 9eef8b8cc26559fe5f2575daf7d08c6a17e81ff8 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Mon, 22 May 2017 10:53:03 +0200 Subject: arm: implement ->mapping_error DMA_ERROR_CODE is going to go away, so don't rely on it. Signed-off-by: Christoph Hellwig --- arch/arm/common/dmabounce.c | 13 +++++++++--- arch/arm/include/asm/dma-iommu.h | 2 ++ arch/arm/include/asm/dma-mapping.h | 1 - arch/arm/mm/dma-mapping.c | 41 ++++++++++++++++++++++++-------------- 4 files changed, 38 insertions(+), 19 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c index 9b1b7be2ec0e..4060378e0f14 100644 --- a/arch/arm/common/dmabounce.c +++ b/arch/arm/common/dmabounce.c @@ -33,6 +33,7 @@ #include #include +#include #undef STATS @@ -256,7 +257,7 @@ static inline dma_addr_t map_single(struct device *dev, void *ptr, size_t size, if (buf == NULL) { dev_err(dev, "%s: unable to map unsafe buffer %p!\n", __func__, ptr); - return DMA_ERROR_CODE; + return ARM_MAPPING_ERROR; } dev_dbg(dev, "%s: unsafe buffer %p (dma=%#x) mapped to %p (dma=%#x)\n", @@ -326,7 +327,7 @@ static dma_addr_t dmabounce_map_page(struct device *dev, struct page *page, ret = needs_bounce(dev, dma_addr, size); if (ret < 0) - return DMA_ERROR_CODE; + return ARM_MAPPING_ERROR; if (ret == 0) { arm_dma_ops.sync_single_for_device(dev, dma_addr, size, dir); @@ -335,7 +336,7 @@ static dma_addr_t dmabounce_map_page(struct device *dev, struct page *page, if (PageHighMem(page)) { dev_err(dev, "DMA buffer bouncing of HIGHMEM pages is not supported\n"); - return DMA_ERROR_CODE; + return ARM_MAPPING_ERROR; } return map_single(dev, page_address(page) + offset, size, dir, attrs); @@ -452,6 +453,11 @@ static int dmabounce_set_mask(struct device *dev, u64 dma_mask) return arm_dma_ops.set_dma_mask(dev, dma_mask); } +static int dmabounce_mapping_error(struct device *dev, dma_addr_t dma_addr) +{ + return arm_dma_ops.mapping_error(dev, dma_addr); +} + static const struct dma_map_ops dmabounce_ops = { .alloc = arm_dma_alloc, .free = arm_dma_free, @@ -466,6 +472,7 @@ static const struct dma_map_ops dmabounce_ops = { .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, .sync_sg_for_device = arm_dma_sync_sg_for_device, .set_dma_mask = dmabounce_set_mask, + .mapping_error = dmabounce_mapping_error, }; static int dmabounce_init_pool(struct dmabounce_pool *pool, struct device *dev, diff --git a/arch/arm/include/asm/dma-iommu.h b/arch/arm/include/asm/dma-iommu.h index 2ef282f96651..389a26a10ea3 100644 --- a/arch/arm/include/asm/dma-iommu.h +++ b/arch/arm/include/asm/dma-iommu.h @@ -9,6 +9,8 @@ #include #include +#define ARM_MAPPING_ERROR (~(dma_addr_t)0x0) + struct dma_iommu_mapping { /* iommu specific data */ struct iommu_domain *domain; diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 680d3f3889e7..52a8fd5a8edb 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -12,7 +12,6 @@ #include #include -#define DMA_ERROR_CODE (~(dma_addr_t)0x0) extern const struct dma_map_ops arm_dma_ops; extern const struct dma_map_ops arm_coherent_dma_ops; diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index bd83c531828a..8f2c5a8a98f0 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -180,6 +180,11 @@ static void arm_dma_sync_single_for_device(struct device *dev, __dma_page_cpu_to_dev(page, offset, size, dir); } +static int arm_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) +{ + return dma_addr == ARM_MAPPING_ERROR; +} + const struct dma_map_ops arm_dma_ops = { .alloc = arm_dma_alloc, .free = arm_dma_free, @@ -193,6 +198,7 @@ const struct dma_map_ops arm_dma_ops = { .sync_single_for_device = arm_dma_sync_single_for_device, .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, .sync_sg_for_device = arm_dma_sync_sg_for_device, + .mapping_error = arm_dma_mapping_error, }; EXPORT_SYMBOL(arm_dma_ops); @@ -211,6 +217,7 @@ const struct dma_map_ops arm_coherent_dma_ops = { .get_sgtable = arm_dma_get_sgtable, .map_page = arm_coherent_dma_map_page, .map_sg = arm_dma_map_sg, + .mapping_error = arm_dma_mapping_error, }; EXPORT_SYMBOL(arm_coherent_dma_ops); @@ -799,7 +806,7 @@ static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp &= ~(__GFP_COMP); args.gfp = gfp; - *handle = DMA_ERROR_CODE; + *handle = ARM_MAPPING_ERROR; allowblock = gfpflags_allow_blocking(gfp); cma = allowblock ? dev_get_cma_area(dev) : false; @@ -1254,7 +1261,7 @@ static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping, if (i == mapping->nr_bitmaps) { if (extend_iommu_mapping(mapping)) { spin_unlock_irqrestore(&mapping->lock, flags); - return DMA_ERROR_CODE; + return ARM_MAPPING_ERROR; } start = bitmap_find_next_zero_area(mapping->bitmaps[i], @@ -1262,7 +1269,7 @@ static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping, if (start > mapping->bits) { spin_unlock_irqrestore(&mapping->lock, flags); - return DMA_ERROR_CODE; + return ARM_MAPPING_ERROR; } bitmap_set(mapping->bitmaps[i], start, count); @@ -1445,7 +1452,7 @@ __iommu_create_mapping(struct device *dev, struct page **pages, size_t size, int i; dma_addr = __alloc_iova(mapping, size); - if (dma_addr == DMA_ERROR_CODE) + if (dma_addr == ARM_MAPPING_ERROR) return dma_addr; iova = dma_addr; @@ -1472,7 +1479,7 @@ __iommu_create_mapping(struct device *dev, struct page **pages, size_t size, fail: iommu_unmap(mapping->domain, dma_addr, iova-dma_addr); __free_iova(mapping, dma_addr, size); - return DMA_ERROR_CODE; + return ARM_MAPPING_ERROR; } static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size) @@ -1533,7 +1540,7 @@ static void *__iommu_alloc_simple(struct device *dev, size_t size, gfp_t gfp, return NULL; *handle = __iommu_create_mapping(dev, &page, size, attrs); - if (*handle == DMA_ERROR_CODE) + if (*handle == ARM_MAPPING_ERROR) goto err_mapping; return addr; @@ -1561,7 +1568,7 @@ static void *__arm_iommu_alloc_attrs(struct device *dev, size_t size, struct page **pages; void *addr = NULL; - *handle = DMA_ERROR_CODE; + *handle = ARM_MAPPING_ERROR; size = PAGE_ALIGN(size); if (coherent_flag == COHERENT || !gfpflags_allow_blocking(gfp)) @@ -1582,7 +1589,7 @@ static void *__arm_iommu_alloc_attrs(struct device *dev, size_t size, return NULL; *handle = __iommu_create_mapping(dev, pages, size, attrs); - if (*handle == DMA_ERROR_CODE) + if (*handle == ARM_MAPPING_ERROR) goto err_buffer; if (attrs & DMA_ATTR_NO_KERNEL_MAPPING) @@ -1732,10 +1739,10 @@ static int __map_sg_chunk(struct device *dev, struct scatterlist *sg, int prot; size = PAGE_ALIGN(size); - *handle = DMA_ERROR_CODE; + *handle = ARM_MAPPING_ERROR; iova_base = iova = __alloc_iova(mapping, size); - if (iova == DMA_ERROR_CODE) + if (iova == ARM_MAPPING_ERROR) return -ENOMEM; for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) { @@ -1775,7 +1782,7 @@ static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents, for (i = 1; i < nents; i++) { s = sg_next(s); - s->dma_address = DMA_ERROR_CODE; + s->dma_address = ARM_MAPPING_ERROR; s->dma_length = 0; if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) { @@ -1950,7 +1957,7 @@ static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *p int ret, prot, len = PAGE_ALIGN(size + offset); dma_addr = __alloc_iova(mapping, len); - if (dma_addr == DMA_ERROR_CODE) + if (dma_addr == ARM_MAPPING_ERROR) return dma_addr; prot = __dma_info_to_prot(dir, attrs); @@ -1962,7 +1969,7 @@ static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *p return dma_addr + offset; fail: __free_iova(mapping, dma_addr, len); - return DMA_ERROR_CODE; + return ARM_MAPPING_ERROR; } /** @@ -2056,7 +2063,7 @@ static dma_addr_t arm_iommu_map_resource(struct device *dev, size_t len = PAGE_ALIGN(size + offset); dma_addr = __alloc_iova(mapping, len); - if (dma_addr == DMA_ERROR_CODE) + if (dma_addr == ARM_MAPPING_ERROR) return dma_addr; prot = __dma_info_to_prot(dir, attrs) | IOMMU_MMIO; @@ -2068,7 +2075,7 @@ static dma_addr_t arm_iommu_map_resource(struct device *dev, return dma_addr + offset; fail: __free_iova(mapping, dma_addr, len); - return DMA_ERROR_CODE; + return ARM_MAPPING_ERROR; } /** @@ -2140,6 +2147,8 @@ const struct dma_map_ops iommu_ops = { .map_resource = arm_iommu_map_resource, .unmap_resource = arm_iommu_unmap_resource, + + .mapping_error = arm_dma_mapping_error, }; const struct dma_map_ops iommu_coherent_ops = { @@ -2156,6 +2165,8 @@ const struct dma_map_ops iommu_coherent_ops = { .map_resource = arm_iommu_map_resource, .unmap_resource = arm_iommu_unmap_resource, + + .mapping_error = arm_dma_mapping_error, }; /** -- cgit v1.2.3 From 418a7a7e4f05f36d6e4ab5b8548ea71f0b602140 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Mon, 22 May 2017 11:20:18 +0200 Subject: arm: remove arch specific dma_supported implementation And instead wire it up as method for all the dma_map_ops instances. Note that the code seems a little fishy for dmabounce and iommu, but for now I'd like to preserve the existing behavior 1:1. Signed-off-by: Christoph Hellwig --- arch/arm/common/dmabounce.c | 1 + arch/arm/include/asm/dma-iommu.h | 2 ++ arch/arm/include/asm/dma-mapping.h | 3 --- arch/arm/mm/dma-mapping.c | 7 +++++-- 4 files changed, 8 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c index 4060378e0f14..6ecd5be5d37e 100644 --- a/arch/arm/common/dmabounce.c +++ b/arch/arm/common/dmabounce.c @@ -473,6 +473,7 @@ static const struct dma_map_ops dmabounce_ops = { .sync_sg_for_device = arm_dma_sync_sg_for_device, .set_dma_mask = dmabounce_set_mask, .mapping_error = dmabounce_mapping_error, + .dma_supported = arm_dma_supported, }; static int dmabounce_init_pool(struct dmabounce_pool *pool, struct device *dev, diff --git a/arch/arm/include/asm/dma-iommu.h b/arch/arm/include/asm/dma-iommu.h index 389a26a10ea3..c090ec675eac 100644 --- a/arch/arm/include/asm/dma-iommu.h +++ b/arch/arm/include/asm/dma-iommu.h @@ -35,5 +35,7 @@ int arm_iommu_attach_device(struct device *dev, struct dma_iommu_mapping *mapping); void arm_iommu_detach_device(struct device *dev); +int arm_dma_supported(struct device *dev, u64 mask); + #endif /* __KERNEL__ */ #endif diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 52a8fd5a8edb..8dabcfdf4505 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -20,9 +20,6 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus) return &arm_dma_ops; } -#define HAVE_ARCH_DMA_SUPPORTED 1 -extern int dma_supported(struct device *dev, u64 mask); - #ifdef __arch_page_to_dma #error Please update to __arch_pfn_to_dma #endif diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 8f2c5a8a98f0..b9677ada421f 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -199,6 +199,7 @@ const struct dma_map_ops arm_dma_ops = { .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, .sync_sg_for_device = arm_dma_sync_sg_for_device, .mapping_error = arm_dma_mapping_error, + .dma_supported = arm_dma_supported, }; EXPORT_SYMBOL(arm_dma_ops); @@ -218,6 +219,7 @@ const struct dma_map_ops arm_coherent_dma_ops = { .map_page = arm_coherent_dma_map_page, .map_sg = arm_dma_map_sg, .mapping_error = arm_dma_mapping_error, + .dma_supported = arm_dma_supported, }; EXPORT_SYMBOL(arm_coherent_dma_ops); @@ -1184,11 +1186,10 @@ void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, * during bus mastering, then you would pass 0x00ffffff as the mask * to this function. */ -int dma_supported(struct device *dev, u64 mask) +int arm_dma_supported(struct device *dev, u64 mask) { return __dma_supported(dev, mask, false); } -EXPORT_SYMBOL(dma_supported); #define PREALLOC_DMA_DEBUG_ENTRIES 4096 @@ -2149,6 +2150,7 @@ const struct dma_map_ops iommu_ops = { .unmap_resource = arm_iommu_unmap_resource, .mapping_error = arm_dma_mapping_error, + .dma_supported = arm_dma_supported, }; const struct dma_map_ops iommu_coherent_ops = { @@ -2167,6 +2169,7 @@ const struct dma_map_ops iommu_coherent_ops = { .unmap_resource = arm_iommu_unmap_resource, .mapping_error = arm_dma_mapping_error, + .dma_supported = arm_dma_supported, }; /** -- cgit v1.2.3 From 64273a61b2e247e29c2647e83edc090fd01a118b Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Mon, 22 May 2017 11:53:36 +0200 Subject: arm: implement ->dma_supported instead of ->set_dma_mask Same behavior, less code duplication. Signed-off-by: Christoph Hellwig --- arch/arm/common/dmabounce.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c index 6ecd5be5d37e..9a92de63426f 100644 --- a/arch/arm/common/dmabounce.c +++ b/arch/arm/common/dmabounce.c @@ -445,12 +445,12 @@ static void dmabounce_sync_for_device(struct device *dev, arm_dma_ops.sync_single_for_device(dev, handle, size, dir); } -static int dmabounce_set_mask(struct device *dev, u64 dma_mask) +static int dmabounce_dma_supported(struct device *dev, u64 dma_mask) { if (dev->archdata.dmabounce) return 0; - return arm_dma_ops.set_dma_mask(dev, dma_mask); + return arm_dma_ops.dma_supported(dev, dma_mask); } static int dmabounce_mapping_error(struct device *dev, dma_addr_t dma_addr) @@ -471,9 +471,8 @@ static const struct dma_map_ops dmabounce_ops = { .unmap_sg = arm_dma_unmap_sg, .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, .sync_sg_for_device = arm_dma_sync_sg_for_device, - .set_dma_mask = dmabounce_set_mask, + .dma_supported = dmabounce_dma_supported, .mapping_error = dmabounce_mapping_error, - .dma_supported = arm_dma_supported, }; static int dmabounce_init_pool(struct dmabounce_pool *pool, struct device *dev, -- cgit v1.2.3 From 97ad2bdcbe8598a69ee1f372ed6c0fbdb2869218 Mon Sep 17 00:00:00 2001 From: Lorenzo Pieralisi Date: Wed, 28 Jun 2017 15:13:55 -0500 Subject: ARM/PCI: Convert PCI scan API to pci_scan_root_bus_bridge() The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert ARM bios32 code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: Lorenzo Pieralisi [bhelgaas: fold in warning fix from Arnd Bergmann : http://lkml.kernel.org/r/20170621215323.3921382-1-arnd@arndb.de] [bhelgaas: set bridge->ops for mv78xx0] [bhelgaas: fold in fixes from Lorenzo Pieralisi : http://lkml.kernel.org/r/20170701135457.GB8977@red-moon] Signed-off-by: Bjorn Helgaas Cc: Jason Cooper Cc: Russell King Cc: Andrew Lunn --- arch/arm/include/asm/mach/pci.h | 3 ++- arch/arm/kernel/bios32.c | 39 +++++++++++++++++++++++++-------------- arch/arm/mach-dove/pcie.c | 17 ++++++++++++----- arch/arm/mach-iop13xx/pci.c | 31 ++++++++++++++++++++----------- arch/arm/mach-iop13xx/pci.h | 3 ++- arch/arm/mach-mv78xx0/pcie.c | 16 +++++++++++----- arch/arm/mach-orion5x/common.h | 3 ++- arch/arm/mach-orion5x/pci.c | 25 +++++++++++++++++-------- 8 files changed, 91 insertions(+), 46 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index 2d88af5be45f..233b4b50eff3 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -16,6 +16,7 @@ struct pci_sys_data; struct pci_ops; struct pci_bus; +struct pci_host_bridge; struct device; struct hw_pci { @@ -25,7 +26,7 @@ struct hw_pci { unsigned int io_optional:1; void **private_data; int (*setup)(int nr, struct pci_sys_data *); - struct pci_bus *(*scan)(int nr, struct pci_sys_data *); + int (*scan)(int nr, struct pci_host_bridge *); void (*preinit)(void); void (*postinit)(void); u8 (*swizzle)(struct pci_dev *dev, u8 *pin); diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index b259956365a0..4c7621ac389c 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -458,10 +458,14 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, int nr, busnr; for (nr = busnr = 0; nr < hw->nr_controllers; nr++) { - sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL); - if (WARN(!sys, "PCI: unable to allocate sys data!")) + struct pci_host_bridge *bridge; + + bridge = pci_alloc_host_bridge(sizeof(struct pci_sys_data)); + if (WARN(!bridge, "PCI: unable to allocate bridge!")) break; + sys = pci_host_bridge_priv(bridge); + sys->busnr = busnr; sys->swizzle = hw->swizzle; sys->map_irq = hw->map_irq; @@ -473,7 +477,6 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, ret = hw->setup(nr, sys); if (ret > 0) { - struct pci_host_bridge *host_bridge; ret = pcibios_init_resource(nr, sys, hw->io_optional); if (ret) { @@ -482,25 +485,33 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, } if (hw->scan) - sys->bus = hw->scan(nr, sys); - else - sys->bus = pci_scan_root_bus_msi(parent, - sys->busnr, hw->ops, sys, - &sys->resources, hw->msi_ctrl); + ret = hw->scan(nr, bridge); + else { + list_splice_init(&sys->resources, + &bridge->windows); + bridge->dev.parent = parent; + bridge->sysdata = sys; + bridge->busnr = sys->busnr; + bridge->ops = hw->ops; + bridge->msi = hw->msi_ctrl; + bridge->align_resource = + hw->align_resource; + + ret = pci_scan_root_bus_bridge(bridge); + } - if (WARN(!sys->bus, "PCI: unable to scan bus!")) { - kfree(sys); + if (WARN(ret < 0, "PCI: unable to scan bus!")) { + pci_free_host_bridge(bridge); break; } + sys->bus = bridge->bus; + busnr = sys->bus->busn_res.end + 1; list_add(&sys->node, head); - - host_bridge = pci_find_host_bridge(sys->bus); - host_bridge->align_resource = hw->align_resource; } else { - kfree(sys); + pci_free_host_bridge(bridge); if (ret < 0) break; } diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c index 91fe97144570..dfb62f3f5dcf 100644 --- a/arch/arm/mach-dove/pcie.c +++ b/arch/arm/mach-dove/pcie.c @@ -152,16 +152,23 @@ static void rc_pci_fixup(struct pci_dev *dev) } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); -static struct pci_bus __init * -dove_pcie_scan_bus(int nr, struct pci_sys_data *sys) +static int __init +dove_pcie_scan_bus(int nr, struct pci_host_bridge *bridge) { + struct pci_sys_data *sys = pci_host_bridge_priv(bridge); + if (nr >= num_pcie_ports) { BUG(); - return NULL; + return -EINVAL; } - return pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, - &sys->resources); + list_splice_init(&sys->resources, &bridge->windows); + bridge->dev.parent = NULL; + bridge->sysdata = sys; + bridge->busnr = sys->busnr; + bridge->ops = &pcie_ops; + + return pci_scan_root_bus_bridge(bridge); } static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c index 204eb4460271..070d92ae1b6f 100644 --- a/arch/arm/mach-iop13xx/pci.c +++ b/arch/arm/mach-iop13xx/pci.c @@ -504,10 +504,10 @@ iop13xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) /* Scan an IOP13XX PCI bus. nr selects which ATU we use. */ -struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys) +int iop13xx_scan_bus(int nr, struct pci_host_bridge *bridge) { - int which_atu; - struct pci_bus *bus = NULL; + int which_atu, ret; + struct pci_sys_data *sys = pci_host_bridge_priv(bridge); switch (init_atu) { case IOP13XX_INIT_ATU_ATUX: @@ -525,9 +525,14 @@ struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys) if (!which_atu) { BUG(); - return NULL; + return -ENODEV; } + list_splice_init(&sys->resources, &bridge->windows); + bridge->dev.parent = NULL; + bridge->sysdata = sys; + bridge->busnr = sys->busnr; + switch (which_atu) { case IOP13XX_INIT_ATU_ATUX: if (time_after_eq(jiffies + msecs_to_jiffies(1000), @@ -535,18 +540,22 @@ struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys) while(time_before(jiffies, atux_trhfa_timeout)) udelay(100); - bus = pci_bus_atux = pci_scan_root_bus(NULL, sys->busnr, - &iop13xx_atux_ops, - sys, &sys->resources); + bridge->ops = &iop13xx_atux_ops; + ret = pci_scan_root_bus_bridge(bridge); + if (!ret) + pci_bus_atux = bridge->bus; break; case IOP13XX_INIT_ATU_ATUE: - bus = pci_bus_atue = pci_scan_root_bus(NULL, sys->busnr, - &iop13xx_atue_ops, - sys, &sys->resources); + bridge->ops = &iop13xx_atue_ops; + ret = pci_scan_root_bus_bridge(bridge); + if (!ret) + pci_bus_atue = bridge->bus; break; + default: + ret = -EINVAL; } - return bus; + return ret; } /* This function is called from iop13xx_pci_init() after assigning valid diff --git a/arch/arm/mach-iop13xx/pci.h b/arch/arm/mach-iop13xx/pci.h index 71b9c57e1fde..8dc343cb887a 100644 --- a/arch/arm/mach-iop13xx/pci.h +++ b/arch/arm/mach-iop13xx/pci.h @@ -11,9 +11,10 @@ extern size_t iop13xx_atue_mem_size; extern size_t iop13xx_atux_mem_size; struct pci_sys_data; +struct pci_host_bridge; struct hw_pci; int iop13xx_pci_setup(int nr, struct pci_sys_data *sys); -struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *); +int iop13xx_scan_bus(int nr, struct pci_host_bridge *bridge); void iop13xx_atu_select(struct hw_pci *plat_pci); void iop13xx_pci_init(void); void iop13xx_map_pci_memory(void); diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index 81ff4327a962..636d84b40466 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c @@ -194,16 +194,22 @@ static void rc_pci_fixup(struct pci_dev *dev) } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); -static struct pci_bus __init * -mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys) +static int __init mv78xx0_pcie_scan_bus(int nr, struct pci_host_bridge *bridge) { + struct pci_sys_data *sys = pci_host_bridge_priv(bridge); + if (nr >= num_pcie_ports) { BUG(); - return NULL; + return -EINVAL; } - return pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, - &sys->resources); + list_splice_init(&sys->resources, &bridge->windows); + bridge->dev.parent = NULL; + bridge->sysdata = sys; + bridge->busnr = sys->busnr; + bridge->ops = &pcie_ops; + + return pci_scan_root_bus_bridge(bridge); } static int __init mv78xx0_pcie_map_irq(const struct pci_dev *dev, u8 slot, diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index efeffc6b4ebb..4c0c7de665c3 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -54,6 +54,7 @@ void orion5x_restart(enum reboot_mode, const char *); * PCIe/PCI functions. */ struct pci_bus; +struct pci_host_bridge; struct pci_sys_data; struct pci_dev; @@ -61,7 +62,7 @@ void orion5x_pcie_id(u32 *dev, u32 *rev); void orion5x_pci_disable(void); void orion5x_pci_set_cardbus_mode(void); int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys); -struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); +int orion5x_pci_sys_scan_bus(int nr, struct pci_host_bridge *bridge); int orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); struct tag; diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index ecb998e7f8dc..76951bfbacf5 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -555,18 +555,27 @@ int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) return 0; } -struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) +int __init orion5x_pci_sys_scan_bus(int nr, struct pci_host_bridge *bridge) { - if (nr == 0) - return pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, - &sys->resources); + struct pci_sys_data *sys = pci_host_bridge_priv(bridge); - if (nr == 1 && !orion5x_pci_disabled) - return pci_scan_root_bus(NULL, sys->busnr, &pci_ops, sys, - &sys->resources); + list_splice_init(&sys->resources, &bridge->windows); + bridge->dev.parent = NULL; + bridge->sysdata = sys; + bridge->busnr = sys->busnr; + + if (nr == 0) { + bridge->ops = &pcie_ops; + return pci_scan_root_bus_bridge(bridge); + } + + if (nr == 1 && !orion5x_pci_disabled) { + bridge->ops = &pci_ops; + return pci_scan_root_bus_bridge(bridge); + } BUG(); - return NULL; + return -ENODEV; } int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -- cgit v1.2.3 From a3cc999959fc9b492f3ddb48add2be6d872c16c7 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 21 Jun 2017 07:42:39 -0400 Subject: multi_v7_defconfig: Enable OMAP MTD and DM816 AHCI A wide variety of TI platforms support NAND via the CONFIG_MTD_NAND_OMAP2 driver (and related BCH options), so enable this. In addition, multi_v7_defconfig supports the dm8168-evm and that supports root being on a SATA drive, so build the DM816 AHCI driver into the resulting kernel as well. Cc: Russell King Cc: Arnd Bergmann Cc: Mihail Grigorov Signed-off-by: Tom Rini Acked-by: Tony Lindgren Signed-off-by: Arnd Bergmann --- arch/arm/configs/multi_v7_defconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 705d908e004a..4d19c1b4b8e7 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -202,6 +202,8 @@ CONFIG_MTD_BLOCK=y CONFIG_MTD_M25P80=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_DENALI_DT=y +CONFIG_MTD_NAND_OMAP2=y +CONFIG_MTD_NAND_OMAP_BCH=y CONFIG_MTD_NAND_ATMEL=y CONFIG_MTD_NAND_BRCMNAND=y CONFIG_MTD_NAND_VF610_NFC=y @@ -229,6 +231,7 @@ CONFIG_ATA=y CONFIG_SATA_AHCI=y CONFIG_SATA_AHCI_PLATFORM=y CONFIG_AHCI_BRCM=y +CONFIG_AHCI_DM816=y CONFIG_AHCI_ST=y CONFIG_AHCI_IMX=y CONFIG_AHCI_SUNXI=y -- cgit v1.2.3 From 1c51c429f30ea10428337f3a33c12059ba59f668 Mon Sep 17 00:00:00 2001 From: Vladimir Murzin Date: Wed, 24 May 2017 11:24:30 +0100 Subject: ARM: NOMMU: Introduce dma operations for noMMU R/M classes of cpus can have memory covered by MPU which in turn might configure RAM as Normal i.e. bufferable and cacheable. It breaks dma_alloc_coherent() and friends, since data can stuck in caches now or be buffered. This patch factors out DMA support for NOMMU configuration into separate entity which provides dedicated dma_ops. We have to handle there several cases: - configurations with MMU/MPU setup - configurations without MMU/MPU setup - special case for M-class, since caches and MPU there are optional In general we rely on default DMA area for coherent allocations or/and per-device memory reserves suitable for coherent DMA, so if such regions are set coherent allocations go from there. In case MMU/MPU was not setup we fallback to normal page allocator for DMA memory allocation. In case we run M-class cpus, for configuration without cache support (like Cortex-M3/M4) dma operations are forced to be coherent and wired with dma-noop (such decision is made based on cacheid global variable); however, if caches are detected there and no DMA coherent region is given (either default or per-device), dma is disallowed even MPU is not set - it is because M-class implement system memory map which defines part of address space as Normal memory. Reported-by: Alexandre Torgue Reported-by: Andras Szemzo Tested-by: Benjamin Gaignard Tested-by: Andras Szemzo Tested-by: Alexandre TORGUE Reviewed-by: Robin Murphy Signed-off-by: Vladimir Murzin Acked-by: Arnd Bergmann Acked-by: Russell King [hch: removed the dma_supported() implementation that isn't required anymore] Signed-off-by: Christoph Hellwig --- arch/arm/Kconfig | 1 + arch/arm/include/asm/dma-mapping.h | 2 +- arch/arm/mm/Makefile | 5 +- arch/arm/mm/dma-mapping-nommu.c | 228 +++++++++++++++++++++++++++++++++++++ 4 files changed, 232 insertions(+), 4 deletions(-) create mode 100644 arch/arm/mm/dma-mapping-nommu.c (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4c1a35f15838..8a94f2c7606c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -22,6 +22,7 @@ config ARM select CLONE_BACKWARDS select CPU_PM if (SUSPEND || CPU_IDLE) select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS + select DMA_NOOP_OPS if !MMU select EDAC_SUPPORT select EDAC_ATOMIC_SCRUB select GENERIC_ALLOCATOR diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 8dabcfdf4505..4e0285a66ef8 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -17,7 +17,7 @@ extern const struct dma_map_ops arm_coherent_dma_ops; static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus) { - return &arm_dma_ops; + return IS_ENABLED(CONFIG_MMU) ? &arm_dma_ops : &dma_noop_ops; } #ifdef __arch_page_to_dma diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index b3dea80715b4..950d19babb5f 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -2,9 +2,8 @@ # Makefile for the linux arm-specific parts of the memory manager. # -obj-y := dma-mapping.o extable.o fault.o init.o \ - iomap.o - +obj-y := extable.o fault.o init.o iomap.o +obj-y += dma-mapping$(MMUEXT).o obj-$(CONFIG_MMU) += fault-armv.o flush.o idmap.o ioremap.o \ mmap.o pgd.o mmu.o pageattr.o diff --git a/arch/arm/mm/dma-mapping-nommu.c b/arch/arm/mm/dma-mapping-nommu.c new file mode 100644 index 000000000000..90ee354d803e --- /dev/null +++ b/arch/arm/mm/dma-mapping-nommu.c @@ -0,0 +1,228 @@ +/* + * Based on linux/arch/arm/mm/dma-mapping.c + * + * Copyright (C) 2000-2004 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "dma.h" + +/* + * dma_noop_ops is used if + * - MMU/MPU is off + * - cpu is v7m w/o cache support + * - device is coherent + * otherwise arm_nommu_dma_ops is used. + * + * arm_nommu_dma_ops rely on consistent DMA memory (please, refer to + * [1] on how to declare such memory). + * + * [1] Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + */ + +static void *arm_nommu_dma_alloc(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t gfp, + unsigned long attrs) + +{ + const struct dma_map_ops *ops = &dma_noop_ops; + + /* + * We are here because: + * - no consistent DMA region has been defined, so we can't + * continue. + * - there is no space left in consistent DMA region, so we + * only can fallback to generic allocator if we are + * advertised that consistency is not required. + */ + + if (attrs & DMA_ATTR_NON_CONSISTENT) + return ops->alloc(dev, size, dma_handle, gfp, attrs); + + WARN_ON_ONCE(1); + return NULL; +} + +static void arm_nommu_dma_free(struct device *dev, size_t size, + void *cpu_addr, dma_addr_t dma_addr, + unsigned long attrs) +{ + const struct dma_map_ops *ops = &dma_noop_ops; + + if (attrs & DMA_ATTR_NON_CONSISTENT) + ops->free(dev, size, cpu_addr, dma_addr, attrs); + else + WARN_ON_ONCE(1); + + return; +} + +static void __dma_page_cpu_to_dev(phys_addr_t paddr, size_t size, + enum dma_data_direction dir) +{ + dmac_map_area(__va(paddr), size, dir); + + if (dir == DMA_FROM_DEVICE) + outer_inv_range(paddr, paddr + size); + else + outer_clean_range(paddr, paddr + size); +} + +static void __dma_page_dev_to_cpu(phys_addr_t paddr, size_t size, + enum dma_data_direction dir) +{ + if (dir != DMA_TO_DEVICE) { + outer_inv_range(paddr, paddr + size); + dmac_unmap_area(__va(paddr), size, dir); + } +} + +static dma_addr_t arm_nommu_dma_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction dir, + unsigned long attrs) +{ + dma_addr_t handle = page_to_phys(page) + offset; + + __dma_page_cpu_to_dev(handle, size, dir); + + return handle; +} + +static void arm_nommu_dma_unmap_page(struct device *dev, dma_addr_t handle, + size_t size, enum dma_data_direction dir, + unsigned long attrs) +{ + __dma_page_dev_to_cpu(handle, size, dir); +} + + +static int arm_nommu_dma_map_sg(struct device *dev, struct scatterlist *sgl, + int nents, enum dma_data_direction dir, + unsigned long attrs) +{ + int i; + struct scatterlist *sg; + + for_each_sg(sgl, sg, nents, i) { + sg_dma_address(sg) = sg_phys(sg); + sg_dma_len(sg) = sg->length; + __dma_page_cpu_to_dev(sg_dma_address(sg), sg_dma_len(sg), dir); + } + + return nents; +} + +static void arm_nommu_dma_unmap_sg(struct device *dev, struct scatterlist *sgl, + int nents, enum dma_data_direction dir, + unsigned long attrs) +{ + struct scatterlist *sg; + int i; + + for_each_sg(sgl, sg, nents, i) + __dma_page_dev_to_cpu(sg_dma_address(sg), sg_dma_len(sg), dir); +} + +static void arm_nommu_dma_sync_single_for_device(struct device *dev, + dma_addr_t handle, size_t size, enum dma_data_direction dir) +{ + __dma_page_cpu_to_dev(handle, size, dir); +} + +static void arm_nommu_dma_sync_single_for_cpu(struct device *dev, + dma_addr_t handle, size_t size, enum dma_data_direction dir) +{ + __dma_page_cpu_to_dev(handle, size, dir); +} + +static void arm_nommu_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sgl, + int nents, enum dma_data_direction dir) +{ + struct scatterlist *sg; + int i; + + for_each_sg(sgl, sg, nents, i) + __dma_page_cpu_to_dev(sg_dma_address(sg), sg_dma_len(sg), dir); +} + +static void arm_nommu_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sgl, + int nents, enum dma_data_direction dir) +{ + struct scatterlist *sg; + int i; + + for_each_sg(sgl, sg, nents, i) + __dma_page_dev_to_cpu(sg_dma_address(sg), sg_dma_len(sg), dir); +} + +const struct dma_map_ops arm_nommu_dma_ops = { + .alloc = arm_nommu_dma_alloc, + .free = arm_nommu_dma_free, + .map_page = arm_nommu_dma_map_page, + .unmap_page = arm_nommu_dma_unmap_page, + .map_sg = arm_nommu_dma_map_sg, + .unmap_sg = arm_nommu_dma_unmap_sg, + .sync_single_for_device = arm_nommu_dma_sync_single_for_device, + .sync_single_for_cpu = arm_nommu_dma_sync_single_for_cpu, + .sync_sg_for_device = arm_nommu_dma_sync_sg_for_device, + .sync_sg_for_cpu = arm_nommu_dma_sync_sg_for_cpu, +}; +EXPORT_SYMBOL(arm_nommu_dma_ops); + +static const struct dma_map_ops *arm_nommu_get_dma_map_ops(bool coherent) +{ + return coherent ? &dma_noop_ops : &arm_nommu_dma_ops; +} + +void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, + const struct iommu_ops *iommu, bool coherent) +{ + const struct dma_map_ops *dma_ops; + + if (IS_ENABLED(CONFIG_CPU_V7M)) { + /* + * Cache support for v7m is optional, so can be treated as + * coherent if no cache has been detected. Note that it is not + * enough to check if MPU is in use or not since in absense of + * MPU system memory map is used. + */ + dev->archdata.dma_coherent = (cacheid) ? coherent : true; + } else { + /* + * Assume coherent DMA in case MMU/MPU has not been set up. + */ + dev->archdata.dma_coherent = (get_cr() & CR_M) ? coherent : true; + } + + dma_ops = arm_nommu_get_dma_map_ops(dev->archdata.dma_coherent); + + set_dma_ops(dev, dma_ops); +} + +void arch_teardown_dma_ops(struct device *dev) +{ +} + +#define PREALLOC_DMA_DEBUG_ENTRIES 4096 + +static int __init dma_debug_do_init(void) +{ + dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); + return 0; +} +core_initcall(dma_debug_do_init); -- cgit v1.2.3 From 1b11d39e6a6864a9dfb64e2c3ac03090e3b34399 Mon Sep 17 00:00:00 2001 From: Vladimir Murzin Date: Wed, 24 May 2017 11:24:31 +0100 Subject: ARM: NOMMU: Set ARM_DMA_MEM_BUFFERABLE for M-class cpus Now, we have dedicated non-cacheable region for consistent DMA operations. However, that region can still be marked as bufferable by MPU, so it'd be safer to have barriers by default. M-class machines that didn't need it until now also likely won't need it in the future, therefore, we offer this as an option. Tested-by: Benjamin Gaignard Tested-by: Andras Szemzo Tested-by: Alexandre TORGUE Reviewed-by: Robin Murphy Signed-off-by: Vladimir Murzin Acked-by: Russell King Signed-off-by: Christoph Hellwig --- arch/arm/mm/Kconfig | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index c6c4c9c8824b..877a0e3fd17d 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -1045,8 +1045,8 @@ config ARM_L1_CACHE_SHIFT default 5 config ARM_DMA_MEM_BUFFERABLE - bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7 - default y if CPU_V6 || CPU_V6K || CPU_V7 + bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K || CPU_V7M) && !CPU_V7 + default y if CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M help Historically, the kernel has used strongly ordered mappings to provide DMA coherent memory. With the advent of ARMv7, mapping @@ -1061,6 +1061,10 @@ config ARM_DMA_MEM_BUFFERABLE and therefore turning this on may result in unpredictable driver behaviour. Therefore, we offer this as an option. + On some of the beefier ARMv7-M machines (with DMA and write + buffers) you likely want this enabled, while those that + didn't need it until now also won't need it in the future. + You are recommended say 'Y' here and debug any affected drivers. config ARM_HEAVY_MB -- cgit v1.2.3 From 1655cf8829d82d367d8fdb5cb58e5885d7d2a391 Mon Sep 17 00:00:00 2001 From: Vladimir Murzin Date: Wed, 24 May 2017 11:24:32 +0100 Subject: ARM: dma-mapping: Remove traces of NOMMU code DMA operations for NOMMU case have been just factored out into separate compilation unit, so don't keep dead code. Tested-by: Benjamin Gaignard Tested-by: Andras Szemzo Tested-by: Alexandre TORGUE Signed-off-by: Vladimir Murzin Acked-by: Arnd Bergmann Acked-by: Russell King Signed-off-by: Christoph Hellwig --- arch/arm/mm/dma-mapping.c | 29 ++--------------------------- 1 file changed, 2 insertions(+), 27 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index b9677ada421f..e7380bafbfa6 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -353,8 +353,6 @@ static void __dma_free_buffer(struct page *page, size_t size) } } -#ifdef CONFIG_MMU - static void *__alloc_from_contiguous(struct device *dev, size_t size, pgprot_t prot, struct page **ret_page, const void *caller, bool want_vaddr, @@ -656,22 +654,6 @@ static inline pgprot_t __get_dma_pgprot(unsigned long attrs, pgprot_t prot) return prot; } -#define nommu() 0 - -#else /* !CONFIG_MMU */ - -#define nommu() 1 - -#define __get_dma_pgprot(attrs, prot) __pgprot(0) -#define __alloc_remap_buffer(dev, size, gfp, prot, ret, c, wv) NULL -#define __alloc_from_pool(size, ret_page) NULL -#define __alloc_from_contiguous(dev, size, prot, ret, c, wv, coherent_flag, gfp) NULL -#define __free_from_pool(cpu_addr, size) do { } while (0) -#define __free_from_contiguous(dev, page, cpu_addr, size, wv) do { } while (0) -#define __dma_free_remap(cpu_addr, size) do { } while (0) - -#endif /* CONFIG_MMU */ - static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp, struct page **ret_page) { @@ -814,7 +796,7 @@ static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, if (cma) buf->allocator = &cma_allocator; - else if (nommu() || is_coherent) + else if (is_coherent) buf->allocator = &simple_allocator; else if (allowblock) buf->allocator = &remap_allocator; @@ -863,8 +845,7 @@ static int __arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, void *cpu_addr, dma_addr_t dma_addr, size_t size, unsigned long attrs) { - int ret = -ENXIO; -#ifdef CONFIG_MMU + int ret; unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; unsigned long pfn = dma_to_pfn(dev, dma_addr); @@ -879,10 +860,6 @@ static int __arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, vma->vm_end - vma->vm_start, vma->vm_page_prot); } -#else - ret = vm_iomap_memory(vma, vma->vm_start, - (vma->vm_end - vma->vm_start)); -#endif /* CONFIG_MMU */ return ret; } @@ -901,9 +878,7 @@ int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, void *cpu_addr, dma_addr_t dma_addr, size_t size, unsigned long attrs) { -#ifdef CONFIG_MMU vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); -#endif /* CONFIG_MMU */ return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs); } -- cgit v1.2.3 From ffa47aa678cfaa9b88e8a26cfb115b4768325121 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 30 Jun 2017 18:03:59 +0200 Subject: ARM: Prepare for randomized task_struct With the new task struct randomization, we can run into a build failure for certain random seeds, which will place fields beyond the allow immediate size in the assembly: arch/arm/kernel/entry-armv.S: Assembler messages: arch/arm/kernel/entry-armv.S:803: Error: bad immediate value for offset (4096) Only two constants in asm-offset.h are affected, and I'm changing both of them here to work correctly in all configurations. One more macro has the problem, but is currently unused, so this removes it instead of adding complexity. Suggested-by: Ard Biesheuvel Signed-off-by: Arnd Bergmann [kees: Adjust commit log slightly] Signed-off-by: Kees Cook --- arch/arm/include/asm/assembler.h | 2 ++ arch/arm/kernel/entry-armv.S | 5 ++++- arch/arm/mm/proc-macros.S | 10 ++++------ 3 files changed, 10 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 68b06f9c65de..ad301f107dd2 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -87,6 +87,8 @@ #define CALGN(code...) #endif +#define IMM12_MASK 0xfff + /* * Enable and disable interrupts */ diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 9f157e7c51e7..c731f0d2b2af 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -797,7 +797,10 @@ ENTRY(__switch_to) #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) ldr r7, [r2, #TI_TASK] ldr r8, =__stack_chk_guard - ldr r7, [r7, #TSK_STACK_CANARY] + .if (TSK_STACK_CANARY > IMM12_MASK) + add r7, r7, #TSK_STACK_CANARY & ~IMM12_MASK + .endif + ldr r7, [r7, #TSK_STACK_CANARY & IMM12_MASK] #endif #ifdef CONFIG_CPU_USE_DOMAINS mcr p15, 0, r6, c3, c0, 0 @ Set domain register diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index 0d40c285bd86..f944836da8a2 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -25,11 +25,6 @@ ldr \rd, [\rn, #VMA_VM_FLAGS] .endm - .macro tsk_mm, rd, rn - ldr \rd, [\rn, #TI_TASK] - ldr \rd, [\rd, #TSK_ACTIVE_MM] - .endm - /* * act_mm - get current->active_mm */ @@ -37,7 +32,10 @@ bic \rd, sp, #8128 bic \rd, \rd, #63 ldr \rd, [\rd, #TI_TASK] - ldr \rd, [\rd, #TSK_ACTIVE_MM] + .if (TSK_ACTIVE_MM > IMM12_MASK) + add \rd, \rd, #TSK_ACTIVE_MM & ~IMM12_MASK + .endif + ldr \rd, [\rd, #TSK_ACTIVE_MM & IMM12_MASK] .endm /* -- cgit v1.2.3 From 8acdf5055974e49d337d51ac7011449cfd7b7d05 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Fri, 28 Oct 2016 00:45:16 -0700 Subject: randstruct: opt-out externally exposed function pointer structs Some function pointer structures are used externally to the kernel, like the paravirt structures. These should never be randomized, so mark them as such, in preparation for enabling randstruct's automatic selection of all-function-pointer structures. These markings are verbatim from Brad Spengler/PaX Team's code in the last public patch of grsecurity/PaX based on my understanding of the code. Changes or omissions from the original code are mine and don't reflect the original grsecurity/PaX code. Signed-off-by: Kees Cook --- arch/arm/include/asm/cacheflush.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index d69bebf697e7..74504b154256 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -116,7 +116,7 @@ struct cpu_cache_fns { void (*dma_unmap_area)(const void *, size_t, int); void (*dma_flush_range)(const void *, const void *); -}; +} __no_randomize_layout; /* * Select the calling method -- cgit v1.2.3 From 16508469c0f3198a63923aaec08efa1c63f5fbcc Mon Sep 17 00:00:00 2001 From: Lorenzo Pieralisi Date: Wed, 28 Jun 2017 15:14:04 -0500 Subject: ARM/PCI: Remove pci_fixup_irqs() call for bios32 host controllers Legacy PCI host controllers (ie host controllers that set-up the PCI bus through the ARM pci_common_init() API) are currently relying on pci_fixup_irqs() to assign legacy PCI irqs to devices. This is not ideal in that pci_fixup_irqs() assigns IRQs for all PCI devices present in a given system some of which may well be enabled by the time pci_fixup_irqs() is called (ie a system with multiple host controllers). With the introduction of struct pci_host_bridge.(*map_irq) pointer it is possible to assign IRQs for all devices originating from a PCI host bridge at probe time; this is implemented through pci_assign_irq() that relies on the struct pci_host_bridge.map_irq pointer to map IRQ for a given device. The benefits this brings are twofold: - the IRQ for a device is assigned once at probe time - the IRQ assignment works also for hotplugged devices Remove pci_fixup_irqs() call from bios32 code and rely on pci_assign_irq() to carry out the IRQ mapping at device probe time. The map_irq() and swizzle_irq() struct pci_host_bridge callbacks are set-up in the struct pci_host_bridge created in the bios32 pcibios_init_hw() function and mach-* code paths (for PCI mach implementations that require a specific struct hw_pci.(*scan) function callback). Signed-off-by: Lorenzo Pieralisi [bhelgaas: folded in fixes from Lorenzo: http://lkml.kernel.org/r/20170701140629.GC8977@red-moon] Signed-off-by: Bjorn Helgaas Cc: Jason Cooper Cc: Russell King Cc: Andrew Lunn --- arch/arm/kernel/bios32.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index 4c7621ac389c..56dc1a3a33b4 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -484,6 +484,9 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, break; } + bridge->map_irq = pcibios_map_irq; + bridge->swizzle_irq = pcibios_swizzle; + if (hw->scan) ret = hw->scan(nr, bridge); else { @@ -530,8 +533,6 @@ void pci_common_init_dev(struct device *parent, struct hw_pci *hw) if (hw->postinit) hw->postinit(); - pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq); - list_for_each_entry(sys, &head, node) { struct pci_bus *bus = sys->bus; -- cgit v1.2.3 From eb3827457ab0e151b79798b07072c70f5c83809d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sat, 1 Jul 2017 23:41:00 +0200 Subject: ARM: owl: Drop custom machine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rely on the fallback to "Generic DT based system". This change is visible in /proc/cpuinfo. Cc: Arnd Bergmann Signed-off-by: Andreas Färber Signed-off-by: Arnd Bergmann --- arch/arm/mach-actions/Makefile | 1 - arch/arm/mach-actions/owl.c | 28 ---------------------------- 2 files changed, 29 deletions(-) delete mode 100644 arch/arm/mach-actions/owl.c (limited to 'arch/arm') diff --git a/arch/arm/mach-actions/Makefile b/arch/arm/mach-actions/Makefile index eeb3896e4952..c0f116241da7 100644 --- a/arch/arm/mach-actions/Makefile +++ b/arch/arm/mach-actions/Makefile @@ -1,4 +1,3 @@ -obj-y += owl.o obj-${CONFIG_SMP} += platsmp.o headsmp.o AFLAGS_headsmp.o := -Wa,-march=armv7-a diff --git a/arch/arm/mach-actions/owl.c b/arch/arm/mach-actions/owl.c deleted file mode 100644 index 4ac4a860f3d6..000000000000 --- a/arch/arm/mach-actions/owl.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (C) 2017 Andreas Färber - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - */ - -#include -#include - -static const char * const owl_dt_compat[] = { - "actions,s500", - NULL -}; - -DT_MACHINE_START(OWL, "Actions Semi Owl platform") - .dt_compat = owl_dt_compat, - .l2c_aux_val = 0, - .l2c_aux_mask = ~0, -MACHINE_END -- cgit v1.2.3 From 18cfd9429d8a82c49add8f3ca9d366599bfcac45 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sat, 1 Jul 2017 23:29:30 +0200 Subject: ARM: owl: smp: Drop bogus holding pen MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The S500 SoC can start secondary CPUs without busy-looping for pen_release, so simplify the SMP code compared to the LeMaker kernel tree. Fixes: 172067e0bc87 ("ARM: owl: Implement CPU enable-method for S500") Suggested-by: Arnd Bergmann Cc: David Liu Signed-off-by: Andreas Färber Signed-off-by: Arnd Bergmann --- arch/arm/mach-actions/headsmp.S | 20 ++------------------ arch/arm/mach-actions/platsmp.c | 29 +---------------------------- 2 files changed, 3 insertions(+), 46 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-actions/headsmp.S b/arch/arm/mach-actions/headsmp.S index dc4832fc101a..65f53bdb69e7 100644 --- a/arch/arm/mach-actions/headsmp.S +++ b/arch/arm/mach-actions/headsmp.S @@ -2,6 +2,8 @@ * Copyright 2012 Actions Semi Inc. * Author: Actions Semi, Inc. * + * Copyright (c) 2017 Andreas Färber + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -46,23 +48,5 @@ ENTRY(owl_v7_invalidate_l1) ENDPROC(owl_v7_invalidate_l1) ENTRY(owl_secondary_startup) - mrc p15, 0, r0, c0, c0, 5 - and r0, r0, #0xf - adr r4, 1f - ldmia r4, {r5, r6} - sub r4, r4, r5 - add r6, r6, r4 -pen: - ldr r7, [r6] - cmp r7, r0 - bne pen - - /* - * we've been released from the holding pen: secondary_stack - * should now contain the SVC stack for this core - */ bl owl_v7_invalidate_l1 b secondary_startup - -1: .long . - .long pen_release diff --git a/arch/arm/mach-actions/platsmp.c b/arch/arm/mach-actions/platsmp.c index b4806ce0e9bb..12a9e331b432 100644 --- a/arch/arm/mach-actions/platsmp.c +++ b/arch/arm/mach-actions/platsmp.c @@ -41,26 +41,6 @@ static int ncores; static DEFINE_SPINLOCK(boot_lock); -static void write_pen_release(int val) -{ - pen_release = val; - smp_wmb(); - __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); - outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); -} - -static void s500_smp_secondary_init(unsigned int cpu) -{ - /* - * let the primary processor know we're out of the - * pen, then head off into the C entry point - */ - write_pen_release(-1); - - spin_lock(&boot_lock); - spin_unlock(&boot_lock); -} - void owl_secondary_startup(void); static int s500_wakeup_secondary(unsigned int cpu) @@ -115,12 +95,6 @@ static int s500_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) spin_lock(&boot_lock); - /* - * The secondary processor is waiting to be released from - * the holding pen - release it, then wait for it to flag - * that it has been released by resetting pen_release. - */ - write_pen_release(cpu_logical_map(cpu)); smp_send_reschedule(cpu); timeout = jiffies + (1 * HZ); @@ -134,7 +108,7 @@ static int s500_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) spin_unlock(&boot_lock); - return pen_release != -1 ? -ENOSYS : 0; + return 0; } static void __init s500_smp_prepare_cpus(unsigned int max_cpus) @@ -192,7 +166,6 @@ static void __init s500_smp_prepare_cpus(unsigned int max_cpus) static const struct smp_operations s500_smp_ops __initconst = { .smp_prepare_cpus = s500_smp_prepare_cpus, - .smp_secondary_init = s500_smp_secondary_init, .smp_boot_secondary = s500_smp_boot_secondary, }; CPU_METHOD_OF_DECLARE(s500_smp, "actions,s500-smp", &s500_smp_ops); -- cgit v1.2.3 From 468138d78510688fb5476f98d23f11ac6a63229a Mon Sep 17 00:00:00 2001 From: Al Viro Date: Tue, 2 May 2017 19:52:17 -0400 Subject: binfmt_flat: flat_{get,put}_addr_from_rp() should be able to fail on MMU targets EFAULT is possible here. Make both return 0 or error, passing what used to be the return value of flat_get_addr_from_rp() by reference. Signed-off-by: Al Viro --- arch/arm/include/asm/flat.h | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/flat.h b/arch/arm/include/asm/flat.h index acf1d14b89a6..29d3a1524bce 100644 --- a/arch/arm/include/asm/flat.h +++ b/arch/arm/include/asm/flat.h @@ -5,12 +5,31 @@ #ifndef __ARM_FLAT_H__ #define __ARM_FLAT_H__ +#include + #define flat_argvp_envp_on_stack() 1 #define flat_old_ram_flag(flags) (flags) #define flat_reloc_valid(reloc, size) ((reloc) <= (size)) -#define flat_get_addr_from_rp(rp, relval, flags, persistent) \ - ({ unsigned long __val; __get_user_unaligned(__val, rp); __val; }) -#define flat_put_addr_at_rp(rp, val, relval) __put_user_unaligned(val, rp) + +static inline int flat_get_addr_from_rp(u32 __user *rp, u32 relval, u32 flags, + u32 *addr, u32 *persistent) +{ +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + return copy_from_user(addr, rp, 4) ? -EFAULT : 0; +#else + return get_user(*addr, rp); +#endif +} + +static inline int flat_put_addr_at_rp(u32 __user *rp, u32 addr, u32 rel) +{ +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + return copy_to_user(rp, &addr, 4) ? -EFAULT : 0; +#else + return put_user(addr, rp); +#endif +} + #define flat_get_relocate_addr(rel) (rel) #define flat_set_persistent(relval, p) 0 -- cgit v1.2.3 From 3170d8d226c2053355f3946b4b5ded4c006fe6d4 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Tue, 2 May 2017 20:06:33 -0400 Subject: kill {__,}{get,put}_user_unaligned() no users left Signed-off-by: Al Viro --- arch/arm/include/asm/uaccess.h | 7 ------- 1 file changed, 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index 2577405d082d..0726091a8964 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -17,13 +17,6 @@ #include #include -#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS -#include -#else -#define __get_user_unaligned __get_user -#define __put_user_unaligned __put_user -#endif - #include /* -- cgit v1.2.3 From ae884913ac1a76366f84561a5e89f483365c0fb7 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 10 Jul 2017 03:32:37 +0900 Subject: ARM: move generic-y of exported headers to uapi/asm/Kbuild Since commit fcc8487d477a ("uapi: export all headers under uapi directories"), all (and only) headers under uapi directories are exported, but asm-generic wrappers are still exceptions. To complete de-coupling the uapi from kernel headers, move generic-y of exported headers to uapi/asm/Kbuild. With this change, "make headers_install" will just need to parse uapi/asm/Kbuild to build up exported headers. Signed-off-by: Masahiro Yamada --- arch/arm/include/asm/Kbuild | 16 ---------------- arch/arm/include/uapi/asm/Kbuild | 14 ++++++++++++++ 2 files changed, 14 insertions(+), 16 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild index d8360501c082..721ab5ecfb9b 100644 --- a/arch/arm/include/asm/Kbuild +++ b/arch/arm/include/asm/Kbuild @@ -1,39 +1,23 @@ - - -generic-y += bitsperlong.h generic-y += clkdev.h generic-y += current.h generic-y += early_ioremap.h generic-y += emergency-restart.h -generic-y += errno.h generic-y += exec.h generic-y += extable.h -generic-y += ioctl.h -generic-y += ipcbuf.h generic-y += irq_regs.h generic-y += kdebug.h generic-y += local.h generic-y += local64.h generic-y += mm-arch-hooks.h -generic-y += msgbuf.h generic-y += msi.h -generic-y += param.h generic-y += parport.h -generic-y += poll.h generic-y += preempt.h -generic-y += resource.h generic-y += rwsem.h generic-y += seccomp.h generic-y += segment.h -generic-y += sembuf.h generic-y += serial.h -generic-y += shmbuf.h generic-y += simd.h generic-y += sizes.h -generic-y += socket.h -generic-y += sockios.h -generic-y += termbits.h -generic-y += termios.h generic-y += timex.h generic-y += trace_clock.h generic-y += unaligned.h diff --git a/arch/arm/include/uapi/asm/Kbuild b/arch/arm/include/uapi/asm/Kbuild index 5fb3368e70cb..8e17fe80b55b 100644 --- a/arch/arm/include/uapi/asm/Kbuild +++ b/arch/arm/include/uapi/asm/Kbuild @@ -5,4 +5,18 @@ generated-y += unistd-common.h generated-y += unistd-oabi.h generated-y += unistd-eabi.h +generic-y += bitsperlong.h +generic-y += errno.h +generic-y += ioctl.h +generic-y += ipcbuf.h +generic-y += msgbuf.h +generic-y += param.h +generic-y += poll.h +generic-y += resource.h +generic-y += sembuf.h +generic-y += shmbuf.h generic-y += siginfo.h +generic-y += socket.h +generic-y += sockios.h +generic-y += termbits.h +generic-y += termios.h -- cgit v1.2.3 From f01fc4177352614743ce3fe289687387fcf9e6c6 Mon Sep 17 00:00:00 2001 From: Lorenzo Pieralisi Date: Mon, 10 Jul 2017 13:34:08 +0100 Subject: ARM/PCI: Fix pcibios_init_resource() struct pci_host_bridge leak Since commit 97ad2bdcbe85 ("ARM/PCI: Convert PCI scan API to pci_scan_root_bus_bridge()") the space for struct pci_sys_data is allocated by pci_alloc_host_bridge() as part of the struct pci_host_bridge. Therefore, failure paths must deallocate the entire pci_host_bridge by using pci_free_host_bridge(). Fixes: 97ad2bdcbe85 ("ARM/PCI: Convert PCI scan API to pci_scan_root_bus_bridge()") Signed-off-by: Lorenzo Pieralisi [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas Cc: Jason Cooper Cc: Russell King Cc: Andrew Lunn --- arch/arm/kernel/bios32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index 56dc1a3a33b4..c1809fb549dd 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -480,7 +480,7 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, ret = pcibios_init_resource(nr, sys, hw->io_optional); if (ret) { - kfree(sys); + pci_free_host_bridge(bridge); break; } -- cgit v1.2.3 From 287f3ca563d8ba0ede4ac0cec84218a1ea5e848f Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Mon, 10 Jul 2017 15:51:10 -0700 Subject: ARM: fix rd_size declaration The global variable 'rd_size' is declared as 'int' in source file arch/arm/kernel/atags_parse.c and as 'unsigned long' in drivers/block/brd.c. Fix this inconsistency. Additionally, remove the declarations of rd_image_start, rd_prompt and rd_doload from parse_tag_ramdisk() since these duplicate existing declarations in . Link: http://lkml.kernel.org/r/20170627065024.12347-1-bart.vanassche@wdc.com Signed-off-by: Bart Van Assche Acked-by: Russell King Cc: Jens Axboe Cc: Jan Kara Cc: Jason Yan Cc: Zhaohongjiang Cc: Miao Xie Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/arm/kernel/atags_parse.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/atags_parse.c b/arch/arm/kernel/atags_parse.c index 68c6ae0b9e4c..98fbfd235ac8 100644 --- a/arch/arm/kernel/atags_parse.c +++ b/arch/arm/kernel/atags_parse.c @@ -18,6 +18,7 @@ */ #include +#include #include #include #include @@ -91,8 +92,6 @@ __tagtable(ATAG_VIDEOTEXT, parse_tag_videotext); #ifdef CONFIG_BLK_DEV_RAM static int __init parse_tag_ramdisk(const struct tag *tag) { - extern int rd_size, rd_image_start, rd_prompt, rd_doload; - rd_image_start = tag->u.ramdisk.start; rd_doload = (tag->u.ramdisk.flags & 1) == 0; rd_prompt = (tag->u.ramdisk.flags & 2) == 0; -- cgit v1.2.3 From 2c6deb01525ac11cc03c44fe31e3f45ce2cadaf9 Mon Sep 17 00:00:00 2001 From: Matthew Wilcox Date: Mon, 10 Jul 2017 15:51:35 -0700 Subject: bitmap: use memcmp optimisation in more situations Commit 7dd968163f7c ("bitmap: bitmap_equal memcmp optimization") was rather more restrictive than necessary; we can use memcmp() to implement bitmap_equal() as long as the number of bits can be proved to be a multiple of 8. And architectures other than s390 may be able to make good use of this optimisation. [arnd@arndb.de: fix build: add a memcmp() declaration] Link: http://lkml.kernel.org/r/20170630153908.3439707-1-arnd@arndb.de Link: http://lkml.kernel.org/r/20170628153221.11322-5-willy@infradead.org Signed-off-by: Matthew Wilcox Signed-off-by: Arnd Bergmann Acked-by: Rasmus Villemoes Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/arm/boot/compressed/decompress.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c index ea7832702a8f..f3a4bedd1afc 100644 --- a/arch/arm/boot/compressed/decompress.c +++ b/arch/arm/boot/compressed/decompress.c @@ -33,6 +33,7 @@ extern void error(char *); /* Not needed, but used in some headers pulled in by decompressors */ extern char * strstr(const char * s1, const char *s2); extern size_t strlen(const char *s); +extern int memcmp(const void *cs, const void *ct, size_t count); #ifdef CONFIG_KERNEL_GZIP #include "../../../../lib/decompress_inflate.c" -- cgit v1.2.3 From 6a9af90a3bcde217a1c053e135f5f43e5d5fafbd Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Mon, 10 Jul 2017 15:52:40 -0700 Subject: arm: move ELF_ET_DYN_BASE to 4MB Now that explicitly executed loaders are loaded in the mmap region, we have more freedom to decide where we position PIE binaries in the address space to avoid possible collisions with mmap or stack regions. 4MB is chosen here mainly to have parity with x86, where this is the traditional minimum load location, likely to avoid historically requiring a 4MB page table entry when only a portion of the first 4MB would be used (since the NULL address is avoided). For ARM the position could be 0x8000, the standard ET_EXEC load address, but that is needlessly close to the NULL address, and anyone running PIE on 32-bit ARM will have an MMU, so the tight mapping is not needed. Link: http://lkml.kernel.org/r/1498154792-49952-2-git-send-email-keescook@chromium.org Signed-off-by: Kees Cook Cc: Russell King Cc: Catalin Marinas Cc: Will Deacon Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: Michael Ellerman Cc: Martin Schwidefsky Cc: Heiko Carstens Cc: James Hogan Cc: Pratyush Anand Cc: Ingo Molnar Cc: "H. Peter Anvin" Cc: Alexander Viro Cc: Andy Lutomirski Cc: Daniel Micay Cc: Dmitry Safonov Cc: Grzegorz Andrejczuk Cc: Kees Cook Cc: Masahiro Yamada Cc: Qualys Security Advisory Cc: Rik van Riel Cc: Thomas Gleixner Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/arm/include/asm/elf.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h index d2315ffd8f12..f13ae153fb24 100644 --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h @@ -112,12 +112,8 @@ int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs); #define CORE_DUMP_USE_REGSET #define ELF_EXEC_PAGESIZE 4096 -/* This is the location that an ET_DYN program is loaded if exec'ed. Typical - use of this is to invoke "./ld.so someprog" to test out a new version of - the loader. We need to make sure that it is out of the way of the program - that it will "exec", and that there is sufficient room for the brk. */ - -#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2) +/* This is the base location for PIE (ET_DYN with INTERP) loads. */ +#define ELF_ET_DYN_BASE 0x400000UL /* When the program starts, a1 contains a pointer to a function to be registered with atexit, as per the SVR4 ABI. A value of 0 means we -- cgit v1.2.3 From ead9fba6b8e9a81107807f5a221576cb01206a6e Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 12 Jul 2017 14:37:05 -0700 Subject: ARM: KVM: move asmlinkage before type asmlinkage is either 'extern "C"' or blank. Move the uses of asmlinkage before the return types to be similar to the rest of the kernel. Link: http://lkml.kernel.org/r/005b8e120650c6a13b541e420f4e3605603fe9e6.1499284835.git.joe@perches.com Signed-off-by: Joe Perches Cc: Christoffer Dall Cc: Marc Zyngier Cc: Paolo Bonzini Cc: Radim Krcmar Cc: Russell King Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/arm/include/asm/kvm_hyp.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/kvm_hyp.h b/arch/arm/include/asm/kvm_hyp.h index 58508900c4bb..14b5903f0224 100644 --- a/arch/arm/include/asm/kvm_hyp.h +++ b/arch/arm/include/asm/kvm_hyp.h @@ -110,8 +110,8 @@ void __sysreg_restore_state(struct kvm_cpu_context *ctxt); void __vgic_v3_save_state(struct kvm_vcpu *vcpu); void __vgic_v3_restore_state(struct kvm_vcpu *vcpu); -void asmlinkage __vfp_save_state(struct vfp_hard_struct *vfp); -void asmlinkage __vfp_restore_state(struct vfp_hard_struct *vfp); +asmlinkage void __vfp_save_state(struct vfp_hard_struct *vfp); +asmlinkage void __vfp_restore_state(struct vfp_hard_struct *vfp); static inline bool __vfp_enabled(void) { return !(read_sysreg(HCPTR) & (HCPTR_TCP(11) | HCPTR_TCP(10))); @@ -120,8 +120,8 @@ static inline bool __vfp_enabled(void) void __hyp_text __banked_save_state(struct kvm_cpu_context *ctxt); void __hyp_text __banked_restore_state(struct kvm_cpu_context *ctxt); -int asmlinkage __guest_enter(struct kvm_vcpu *vcpu, +asmlinkage int __guest_enter(struct kvm_vcpu *vcpu, struct kvm_cpu_context *host); -int asmlinkage __hyp_do_panic(const char *, int, u32); +asmlinkage int __hyp_do_panic(const char *, int, u32); #endif /* __ARM_KVM_HYP_H__ */ -- cgit v1.2.3 From 1e90d0ed327a289c6fee4f36b25f67d3d7864a43 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 12 Jul 2017 14:37:08 -0700 Subject: ARM: HP Jornada 7XX: move inline before return type Convert 'u8 inline' to 'inline u8' to be the same style used by the rest of the kernel. Miscellanea: jornada_ssp_reverse is an odd function. It is declared inline but is also EXPORT_SYMBOL. It is also apparently only used by jornada720_ssp.c Likely the EXPORT_SYMBOL could be removed and the function converted to static. The addition of static and removal of EXPORT_SYMBOL was not done. Link: http://lkml.kernel.org/r/5bd3b2bf39c6c9caf773949f18158f8f5ec08582.1499284835.git.joe@perches.com Signed-off-by: Joe Perches Cc: Russell King Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/arm/mach-sa1100/jornada720_ssp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c index b143c4659346..7fc11a3c17b4 100644 --- a/arch/arm/mach-sa1100/jornada720_ssp.c +++ b/arch/arm/mach-sa1100/jornada720_ssp.c @@ -33,7 +33,7 @@ static unsigned long jornada_ssp_flags; * we need to reverse all data we receive from the mcu due to its physical location * returns : 01110111 -> 11101110 */ -u8 inline jornada_ssp_reverse(u8 byte) +inline u8 jornada_ssp_reverse(u8 byte) { return ((0x80 & byte) >> 7) | -- cgit v1.2.3 From 325cdacd03c12629aa5f9ee2ace49b1f3dc184a8 Mon Sep 17 00:00:00 2001 From: Josh Poimboeuf Date: Sat, 15 Jul 2017 00:10:58 -0500 Subject: debug: Fix WARN_ON_ONCE() for modules Mike Galbraith reported a situation where a WARN_ON_ONCE() call in DRM code turned into an oops. As it turns out, WARN_ON_ONCE() seems to be completely broken when called from a module. The bug was introduced with the following commit: 19d436268dde ("debug: Add _ONCE() logic to report_bug()") That commit changed WARN_ON_ONCE() to move its 'once' logic into the bug trap handler. It requires a writable bug table so that the BUGFLAG_DONE bit can be written to the flags to indicate the first warning has occurred. The bug table was made writable for vmlinux, which relies on vmlinux.lds.S and vmlinux.lds.h for laying out the sections. However, it wasn't made writable for modules, which rely on the ELF section header flags. Reported-by: Mike Galbraith Tested-by: Masami Hiramatsu Signed-off-by: Josh Poimboeuf Acked-by: Peter Zijlstra (Intel) Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Fixes: 19d436268dde ("debug: Add _ONCE() logic to report_bug()") Link: http://lkml.kernel.org/r/a53b04235a65478dd9afc51f5b329fdc65c84364.1500095401.git.jpoimboe@redhat.com Signed-off-by: Ingo Molnar --- arch/arm/include/asm/bug.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/bug.h b/arch/arm/include/asm/bug.h index 4e6e88a6b2f4..2244a94ed9c9 100644 --- a/arch/arm/include/asm/bug.h +++ b/arch/arm/include/asm/bug.h @@ -37,7 +37,7 @@ do { \ ".pushsection .rodata.str, \"aMS\", %progbits, 1\n" \ "2:\t.asciz " #__file "\n" \ ".popsection\n" \ - ".pushsection __bug_table,\"a\"\n" \ + ".pushsection __bug_table,\"aw\"\n" \ ".align 2\n" \ "3:\t.word 1b, 2b\n" \ "\t.hword " #__line ", 0\n" \ -- cgit v1.2.3 From ac8b4d3ed1a1e995ce821064ce54a22c24d88294 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 17 Jul 2017 09:28:20 +0100 Subject: ARM: 8688/1: pm: add missing types include Add missing types.h include to make the suspend header self-contained and avoid compilation breakage due to include-directive ordering. Acked-by: Pavel Machek Signed-off-by: Johan Hovold Signed-off-by: Russell King --- arch/arm/include/asm/suspend.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/suspend.h b/arch/arm/include/asm/suspend.h index 6c7182f32cef..a61905c86732 100644 --- a/arch/arm/include/asm/suspend.h +++ b/arch/arm/include/asm/suspend.h @@ -1,6 +1,8 @@ #ifndef __ASM_ARM_SUSPEND_H #define __ASM_ARM_SUSPEND_H +#include + struct sleep_save_sp { u32 *save_ptr_stash; u32 save_ptr_stash_phys; -- cgit v1.2.3 From fed3c15531a225d95ec9b0aba4ff01c38de7a1b9 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 17 Jul 2017 09:28:19 +0100 Subject: ARM: 8689/1: scu: add missing errno include Add missing errno include to make the header self-contained and avoid compilation breakage when compiling shared code without CONFIG_HAVE_ARM_SCU. Signed-off-by: Johan Hovold Signed-off-by: Russell King --- arch/arm/include/asm/smp_scu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h index bfe163c40024..5983f6bc62d5 100644 --- a/arch/arm/include/asm/smp_scu.h +++ b/arch/arm/include/asm/smp_scu.h @@ -7,6 +7,7 @@ #ifndef __ASSEMBLER__ +#include #include static inline bool scu_a9_has_base(void) -- cgit v1.2.3 From 309ee04257d473ce87f2c7e99f6d69e933d307e3 Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 24 Mar 2017 16:15:45 +0000 Subject: ARM: use aliases for registers in entry-common Use aliases for the saved (and preserved) PSR and PC values so that we can control which registers are used. Signed-off-by: Russell King --- arch/arm/kernel/entry-common.S | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index eb5cd77bf1d8..9abe47a206d9 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -27,6 +27,8 @@ #include "entry-header.S" +saved_psr .req r8 +saved_pc .req lr .align 5 #if !(IS_ENABLED(CONFIG_TRACE_IRQFLAGS) || IS_ENABLED(CONFIG_CONTEXT_TRACKING)) @@ -141,9 +143,9 @@ ENTRY(vector_swi) ARM( stmdb r8, {sp, lr}^ ) @ Calling sp, lr THUMB( mov r8, sp ) THUMB( store_user_sp_lr r8, r10, S_SP ) @ calling sp, lr - mrs r8, spsr @ called from non-FIQ mode, so ok. - str lr, [sp, #S_PC] @ Save calling PC - str r8, [sp, #S_PSR] @ Save CPSR + mrs saved_psr, spsr @ called from non-FIQ mode, so ok. + str saved_pc, [sp, #S_PC] @ Save calling PC + str saved_psr, [sp, #S_PSR] @ Save CPSR str r0, [sp, #S_OLD_R0] @ Save OLD_R0 #endif zero_fp @@ -163,11 +165,11 @@ ENTRY(vector_swi) * value to determine if it is an EABI or an old ABI call. */ #ifdef CONFIG_ARM_THUMB - tst r8, #PSR_T_BIT + tst saved_psr, #PSR_T_BIT movne r10, #0 @ no thumb OABI emulation - USER( ldreq r10, [lr, #-4] ) @ get SWI instruction + USER( ldreq r10, [saved_pc, #-4] ) @ get SWI instruction #else - USER( ldr r10, [lr, #-4] ) @ get SWI instruction + USER( ldr r10, [saved_pc, #-4] ) @ get SWI instruction #endif ARM_BE8(rev r10, r10) @ little endian instruction @@ -178,15 +180,17 @@ ENTRY(vector_swi) */ #elif defined(CONFIG_ARM_THUMB) /* Legacy ABI only, possibly thumb mode. */ - tst r8, #PSR_T_BIT @ this is SPSR from save_user_regs + tst saved_psr, #PSR_T_BIT @ this is SPSR from save_user_regs addne scno, r7, #__NR_SYSCALL_BASE @ put OS number in - USER( ldreq scno, [lr, #-4] ) + USER( ldreq scno, [saved_pc, #-4] ) #else /* Legacy ABI only. */ - USER( ldr scno, [lr, #-4] ) @ get SWI instruction + USER( ldr scno, [saved_pc, #-4] ) @ get SWI instruction #endif + /* saved_psr and saved_pc are now dead */ + uaccess_disable tbl adr tbl, sys_call_table @ load syscall table pointer @@ -234,7 +238,7 @@ local_restart: * current task. */ 9001: - sub lr, lr, #4 + sub lr, saved_pc, #4 str lr, [sp, #S_PC] b ret_fast_syscall #endif -- cgit v1.2.3 From da594e3fff398a164c77dd728d9fbfc6880881e6 Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 24 Mar 2017 16:19:12 +0000 Subject: ARM: obtain thread info structure later Obtain the thread info structure later in the syscall processing, so that we free up a register for earlier code. Signed-off-by: Russell King --- arch/arm/kernel/entry-common.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 9abe47a206d9..374c28723547 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -152,7 +152,6 @@ ENTRY(vector_swi) alignment_trap r10, ip, __cr_alignment enable_irq ct_user_exit - get_thread_info tsk /* * Get the system call number. @@ -209,6 +208,7 @@ ENTRY(vector_swi) bic scno, scno, #0xff000000 @ mask off SWI op-code eor scno, scno, #__NR_SYSCALL_BASE @ check OS number #endif + get_thread_info tsk local_restart: ldr r10, [tsk, #TI_FLAGS] @ check for syscall tracing @@ -240,6 +240,7 @@ local_restart: 9001: sub lr, saved_pc, #4 str lr, [sp, #S_PC] + get_thread_info tsk b ret_fast_syscall #endif ENDPROC(vector_swi) -- cgit v1.2.3 From fcea45236d3ffcd317296d75612eb163bf734407 Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 24 Mar 2017 16:22:10 +0000 Subject: ARM: move PC value into r9 Move the saved PC value into r9, thereby moving it into a caller-saved register for functions that we may call during the entry to a syscall. Signed-off-by: Russell King --- arch/arm/kernel/entry-common.S | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 374c28723547..1b3fc79d0e8b 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -28,7 +28,13 @@ #include "entry-header.S" saved_psr .req r8 +#if defined(CONFIG_TRACE_IRQFLAGS) || defined(CONFIG_CONTEXT_TRACKING) +saved_pc .req r9 +#define TRACE(x...) x +#else saved_pc .req lr +#define TRACE(x...) +#endif .align 5 #if !(IS_ENABLED(CONFIG_TRACE_IRQFLAGS) || IS_ENABLED(CONFIG_CONTEXT_TRACKING)) @@ -144,6 +150,7 @@ ENTRY(vector_swi) THUMB( mov r8, sp ) THUMB( store_user_sp_lr r8, r10, S_SP ) @ calling sp, lr mrs saved_psr, spsr @ called from non-FIQ mode, so ok. + TRACE( mov saved_pc, lr ) str saved_pc, [sp, #S_PC] @ Save calling PC str saved_psr, [sp, #S_PSR] @ Save CPSR str r0, [sp, #S_OLD_R0] @ Save OLD_R0 -- cgit v1.2.3 From dca778c5bbf3f1cfcf7f6ef6cadf5a7e5c5d972f Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 24 Mar 2017 16:23:25 +0000 Subject: ARM: avoid saving and restoring registers unnecessarily Avoid repeatedly saving and restoring registers around the calls to trace_hardirqs_on() and context_tracking_user_exit(). With the previous changes, we no longer need to preserve "lr" across these calls, and if we re-load r0-r3 later, we can avoid preserving these regsiters too. Signed-off-by: Russell King --- arch/arm/kernel/entry-common.S | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 1b3fc79d0e8b..0b60adf4a5d9 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -157,8 +157,9 @@ ENTRY(vector_swi) #endif zero_fp alignment_trap r10, ip, __cr_alignment - enable_irq - ct_user_exit + asm_trace_hardirqs_on save=0 + enable_irq_notrace + ct_user_exit save=0 /* * Get the system call number. @@ -216,6 +217,11 @@ ENTRY(vector_swi) eor scno, scno, #__NR_SYSCALL_BASE @ check OS number #endif get_thread_info tsk + /* + * Reload the registers that may have been corrupted on entry to + * the syscall assembly (by tracing or context tracking.) + */ + TRACE( ldmia sp, {r0 - r3} ) local_restart: ldr r10, [tsk, #TI_FLAGS] @ check for syscall tracing -- cgit v1.2.3 From 494609701e06a0040c0f4042c80fac4e8b5f0ab8 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 14 Jun 2017 10:25:18 +0100 Subject: ARM: always enable AEABI for ARMv6+ Always enable AEABI for ARMv6+, as these use the double-word exclusives which must be passed an even register to avoid errors such as: /tmp/ccG2rCwe.s:905: Error: even register required -- `ldrexd r5,r6,[r7]' /tmp/ccG2rCwe.s:909: Error: even register required -- `strexd sl,r3,r4,[r7]' Signed-off-by: Russell King --- arch/arm/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a208bfe367b5..1cd85410a89a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1531,7 +1531,6 @@ config THUMB2_KERNEL bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K default y if CPU_THUMBONLY - select AEABI select ARM_ASM_UNIFIED select ARM_UNWIND help @@ -1594,7 +1593,8 @@ config ARM_PATCH_IDIV code to do integer division. config AEABI - bool "Use the ARM EABI to compile the kernel" + bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K + default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K help This option allows for the kernel to be compiled using the latest ARM ABI (aka EABI). This is only useful if you are using a user -- cgit v1.2.3 From 9a3dc3186fc3795e076a4122da9e0258651a9631 Mon Sep 17 00:00:00 2001 From: Dustin Brown Date: Mon, 7 Aug 2017 19:44:01 +0100 Subject: ARM: 8691/1: Export save_stack_trace_tsk() The kernel watchdog is a great debugging tool for finding tasks that consume a disproportionate amount of CPU time in contiguous chunks. One can imagine building a similar watchdog for arbitrary driver threads using save_stack_trace_tsk() and print_stack_trace(). However, this is not viable for dynamically loaded driver modules on ARM platforms because save_stack_trace_tsk() is not exported for those architectures. Export save_stack_trace_tsk() for the ARM architecture to align with x86 and support various debugging use cases such as arbitrary driver thread watchdog timers. Signed-off-by: Dustin Brown Signed-off-by: Russell King --- arch/arm/kernel/stacktrace.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c index 3a2fa203637a..65228bf4c6df 100644 --- a/arch/arm/kernel/stacktrace.c +++ b/arch/arm/kernel/stacktrace.c @@ -171,6 +171,7 @@ void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace) { __save_stack_trace(tsk, trace, 1); } +EXPORT_SYMBOL(save_stack_trace_tsk); void save_stack_trace(struct stack_trace *trace) { -- cgit v1.2.3