From b4d1e231fcdc343fb48d76c48b7518f89f3b7350 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 29 Dec 2020 23:17:16 +0200 Subject: arm: dts: owl-s500: Add Clock Management Unit Add Clock Management Unit for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/owl-s500.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 1dbe4e8b38ac..5d5ad9db549b 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -5,6 +5,7 @@ * Copyright (c) 2016-2017 Andreas Färber */ +#include #include #include @@ -70,6 +71,12 @@ #clock-cells = <0>; }; + losc: losc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -169,6 +176,13 @@ status = "disabled"; }; + cmu: clock-controller@b0160000 { + compatible = "actions,s500-cmu"; + reg = <0xb0160000 0x8000>; + clocks = <&hosc>, <&losc>; + #clock-cells = <1>; + }; + timer: timer@b0168000 { compatible = "actions,s500-timer"; reg = <0xb0168000 0x8000>; -- cgit v1.2.3 From 11bc96ba758bf05a8048522d477c5953176132c9 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 29 Dec 2020 23:17:17 +0200 Subject: arm: dts: owl-s500: Set CMU clocks for UARTs Set Clock Management Unit clocks for the UART nodes of Actions Semi S500 SoCs and remove the dummy "uart2_clk" and "uart3_clk" fixed clocks. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/owl-s500-cubieboard6.dts | 7 ------- arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts | 7 ------- arch/arm/boot/dts/owl-s500-labrador-base-m.dts | 7 ------- arch/arm/boot/dts/owl-s500-roseapplepi.dts | 7 ------- arch/arm/boot/dts/owl-s500-sparky.dts | 7 ------- arch/arm/boot/dts/owl-s500.dtsi | 7 +++++++ 6 files changed, 7 insertions(+), 35 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/owl-s500-cubieboard6.dts b/arch/arm/boot/dts/owl-s500-cubieboard6.dts index 7c96c59b610d..c2b02895910c 100644 --- a/arch/arm/boot/dts/owl-s500-cubieboard6.dts +++ b/arch/arm/boot/dts/owl-s500-cubieboard6.dts @@ -25,12 +25,6 @@ device_type = "memory"; reg = <0x0 0x80000000>; }; - - uart3_clk: uart3-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &timer { @@ -39,5 +33,4 @@ &uart3 { status = "okay"; - clocks = <&uart3_clk>; }; diff --git a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts b/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts index e610d49395d2..7ae34a23e320 100644 --- a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts +++ b/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts @@ -18,15 +18,8 @@ chosen { stdout-path = "serial3:115200n8"; }; - - uart3_clk: uart3-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &uart3 { status = "okay"; - clocks = <&uart3_clk>; }; diff --git a/arch/arm/boot/dts/owl-s500-labrador-base-m.dts b/arch/arm/boot/dts/owl-s500-labrador-base-m.dts index c92f8bdcb331..1585e33f703b 100644 --- a/arch/arm/boot/dts/owl-s500-labrador-base-m.dts +++ b/arch/arm/boot/dts/owl-s500-labrador-base-m.dts @@ -21,15 +21,8 @@ chosen { stdout-path = "serial3:115200n8"; }; - - uart3_clk: uart3-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &uart3 { status = "okay"; - clocks = <&uart3_clk>; }; diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts index a2087e617cb2..800edf5d2d12 100644 --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts @@ -25,12 +25,6 @@ device_type = "memory"; reg = <0x0 0x80000000>; /* 2GB */ }; - - uart2_clk: uart2-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &twd_timer { @@ -43,5 +37,4 @@ &uart2 { status = "okay"; - clocks = <&uart2_clk>; }; diff --git a/arch/arm/boot/dts/owl-s500-sparky.dts b/arch/arm/boot/dts/owl-s500-sparky.dts index c665ce8b88b4..9d8f7336bec0 100644 --- a/arch/arm/boot/dts/owl-s500-sparky.dts +++ b/arch/arm/boot/dts/owl-s500-sparky.dts @@ -25,12 +25,6 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1 or 2 GiB */ }; - - uart3_clk: uart3-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &timer { @@ -39,5 +33,4 @@ &uart3 { status = "okay"; - clocks = <&uart3_clk>; }; diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 5d5ad9db549b..ac3d04c75dd5 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -131,6 +131,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0120000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART0>; status = "disabled"; }; @@ -138,6 +139,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0122000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART1>; status = "disabled"; }; @@ -145,6 +147,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0124000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART2>; status = "disabled"; }; @@ -152,6 +155,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0126000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART3>; status = "disabled"; }; @@ -159,6 +163,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0128000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART4>; status = "disabled"; }; @@ -166,6 +171,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb012a000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART5>; status = "disabled"; }; @@ -173,6 +179,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb012c000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART6>; status = "disabled"; }; -- cgit v1.2.3 From 0c2e4ecb12ce7c7f600089c1b211858672eebb80 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 29 Dec 2020 23:17:18 +0200 Subject: arm: dts: owl-s500: Add Reset controller Add reset controller property and bindings header for the Actions Semi S500 SoC DTS. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/owl-s500.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index ac3d04c75dd5..a57ce7d6d745 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { compatible = "actions,s500"; @@ -188,6 +189,7 @@ reg = <0xb0160000 0x8000>; clocks = <&hosc>, <&losc>; #clock-cells = <1>; + #reset-cells = <1>; }; timer: timer@b0168000 { -- cgit v1.2.3 From 2cfb1b3f251e41ab7316762585e376a9b3b348cd Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 29 Dec 2020 23:17:21 +0200 Subject: arm: dts: owl-s500: Add DMA controller Add DMA controller node for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/owl-s500.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index a57ce7d6d745..449e9807c4ec 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -207,5 +207,19 @@ reg = <0xb01b0100 0x100>; #power-domain-cells = <1>; }; + + dma: dma-controller@b0260000 { + compatible = "actions,s500-dma"; + reg = <0xb0260000 0xd00>; + interrupts = , + , + , + ; + #dma-cells = <1>; + dma-channels = <12>; + dma-requests = <46>; + clocks = <&cmu CLK_DMAC>; + power-domains = <&sps S500_PD_DMA>; + }; }; }; -- cgit v1.2.3 From b846f3febbb3fd3623d8c6a0942934a1d527ef7e Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 29 Dec 2020 23:17:22 +0200 Subject: arm: dts: owl-s500: Add pinctrl & GPIO support Add pinctrl node for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/owl-s500.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 449e9807c4ec..b16172615db0 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -208,6 +209,25 @@ #power-domain-cells = <1>; }; + pinctrl: pinctrl@b01b0000 { + compatible = "actions,s500-pinctrl"; + reg = <0xb01b0000 0x40>, /* GPIO */ + <0xb01b0040 0x10>, /* Multiplexing Control */ + <0xb01b0060 0x18>, /* PAD Control */ + <0xb01b0080 0xc>; /* PAD Drive Capacity */ + clocks = <&cmu CLK_GPIO>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 132>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , /* GPIOA */ + , /* GPIOB */ + , /* GPIOC */ + , /* GPIOD */ + ; /* GPIOE */ + }; + dma: dma-controller@b0260000 { compatible = "actions,s500-dma"; reg = <0xb0260000 0xd00>; -- cgit v1.2.3 From 481c640596bca29703ae290880eda3a3420dd4d1 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 29 Dec 2020 23:17:23 +0200 Subject: arm: dts: owl-s500: Add MMC support Add MMC controller nodes for Actions Semi S500 SoC, in order to facilitate access to SD/EMMC/SDIO cards. Signed-off-by: Cristian Ciocaltea Reviewed-by: Ulf Hansson Reviewed-by: Manivannan Sadhasivam Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/owl-s500.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index b16172615db0..7af7c9e1119d 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -241,5 +241,38 @@ clocks = <&cmu CLK_DMAC>; power-domains = <&sps S500_PD_DMA>; }; + + mmc0: mmc@b0230000 { + compatible = "actions,s500-mmc", "actions,owl-mmc"; + reg = <0xb0230000 0x38>; + interrupts = ; + clocks = <&cmu CLK_SD0>; + resets = <&cmu RESET_SD0>; + dmas = <&dma 2>; + dma-names = "mmc"; + status = "disabled"; + }; + + mmc1: mmc@b0234000 { + compatible = "actions,s500-mmc", "actions,owl-mmc"; + reg = <0xb0234000 0x38>; + interrupts = ; + clocks = <&cmu CLK_SD1>; + resets = <&cmu RESET_SD1>; + dmas = <&dma 3>; + dma-names = "mmc"; + status = "disabled"; + }; + + mmc2: mmc@b0238000 { + compatible = "actions,s500-mmc", "actions,owl-mmc"; + reg = <0xb0238000 0x38>; + interrupts = ; + clocks = <&cmu CLK_SD2>; + resets = <&cmu RESET_SD2>; + dmas = <&dma 4>; + dma-names = "mmc"; + status = "disabled"; + }; }; }; -- cgit v1.2.3 From 83ba46e312a1e22c63ae3ca01f91d94ac6b3d70c Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 29 Dec 2020 23:17:24 +0200 Subject: arm: dts: owl-s500: Add I2C support Add I2C controller nodes for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/owl-s500.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 7af7c9e1119d..55f8b8c2e149 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -193,6 +193,46 @@ #reset-cells = <1>; }; + i2c0: i2c@b0170000 { + compatible = "actions,s500-i2c"; + reg = <0xb0170000 0x4000>; + clocks = <&cmu CLK_I2C0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@b0174000 { + compatible = "actions,s500-i2c"; + reg = <0xb0174000 0x4000>; + clocks = <&cmu CLK_I2C1>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@b0178000 { + compatible = "actions,s500-i2c"; + reg = <0xb0178000 0x4000>; + clocks = <&cmu CLK_I2C2>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@b017c000 { + compatible = "actions,s500-i2c"; + reg = <0xb017c000 0x4000>; + clocks = <&cmu CLK_I2C3>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + timer: timer@b0168000 { compatible = "actions,s500-timer"; reg = <0xb0168000 0x8000>; -- cgit v1.2.3 From 3f435fba46c812129253a651004b3bce8ea20f25 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 29 Dec 2020 23:17:25 +0200 Subject: arm: dts: owl-s500: Add SIRQ controller Add SIRQ controller node for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/owl-s500.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 55f8b8c2e149..cd635f222d26 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -233,6 +233,16 @@ status = "disabled"; }; + sirq: interrupt-controller@b01b0200 { + compatible = "actions,s500-sirq"; + reg = <0xb01b0200 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , /* SIRQ0 */ + , /* SIRQ1 */ + ; /* SIRQ2 */ + }; + timer: timer@b0168000 { compatible = "actions,s500-timer"; reg = <0xb0168000 0x8000>; -- cgit v1.2.3 From 8e23902d12433bf19be7e261eb02d64c27384901 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 29 Dec 2020 23:17:26 +0200 Subject: arm: dts: owl-s500-roseapplepi: Add uSD support Add uSD support for RoseapplePi SBC using a fixed regulator as a temporary solution until PMIC support becomes available. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/owl-s500-roseapplepi.dts | 50 ++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts index 800edf5d2d12..fe9ae3619422 100644 --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts @@ -14,6 +14,7 @@ model = "Roseapple Pi"; aliases { + mmc0 = &mmc0; serial2 = &uart2; }; @@ -25,6 +26,55 @@ device_type = "memory"; reg = <0x0 0x80000000>; /* 2GB */ }; + + /* Fixed regulator used in the absence of PMIC */ + sd_vcc: sd-vcc { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.1V"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + }; +}; + +&pinctrl { + mmc0_pins: mmc0-pins { + pinmux { + groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp", + "sd0_cmd_mfp", "sd0_clk_mfp"; + function = "sd0"; + }; + + drv-pinconf { + groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv"; + drive-strength = <8>; + }; + + bias0-pinconf { + pins = "sd0_d0", "sd0_d1", "sd0_d2", + "sd0_d3", "sd0_cmd"; + bias-pull-up; + }; + + bias1-pinconf { + pins = "sd0_clk"; + bias-pull-down; + }; + }; +}; + +/* uSD */ +&mmc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + no-sdio; + no-mmc; + no-1-8-v; + cd-gpios = <&pinctrl 117 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <&sd_vcc>; + vqmmc-supply = <&sd_vcc>; }; &twd_timer { -- cgit v1.2.3 From 7b69552264aca925e8550324027e4f10f8bf8c4f Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 29 Dec 2020 23:17:27 +0200 Subject: arm: dts: owl-s500-roseapplepi: Add I2C pinctrl configuration Add pinctrl definitions for the I2C controllers used in RoseapplePi SBC. For the moment enable only I2C0, which is used by the ATC2603C PMIC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/owl-s500-roseapplepi.dts | 44 ++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts index fe9ae3619422..ff91561ca99c 100644 --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts @@ -37,7 +37,51 @@ }; }; +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +}; + +&i2c1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&i2c2 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; +}; + &pinctrl { + i2c0_pins: i2c0-pins { + pinmux { + groups = "i2c0_mfp"; + function = "i2c0"; + }; + + pinconf { + pins = "i2c0_sclk", "i2c0_sdata"; + bias-pull-up; + }; + }; + + i2c1_pins: i2c1-pins { + pinconf { + pins = "i2c1_sclk", "i2c1_sdata"; + bias-pull-up; + }; + }; + + i2c2_pins: i2c2-pins { + pinconf { + pins = "i2c2_sclk", "i2c2_sdata"; + bias-pull-up; + }; + }; + mmc0_pins: mmc0-pins { pinmux { groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp", -- cgit v1.2.3