From 2c5e596524e7c4a6c56d7d116607b10964be658b Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Sat, 3 Sep 2016 14:53:45 +0200 Subject: ARM: dts: Add MDM9615 dtsi In order to support the Qualcomm MDM9615 SoC, add the SoC dtsi. Signed-off-by: Neil Armstrong Reviewed-by: Stephen Boyd Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-mdm9615.dtsi | 557 ++++++++++++++++++++++++++++++++++++ 1 file changed, 557 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-mdm9615.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi new file mode 100644 index 000000000000..5ae4ec59e6ea --- /dev/null +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -0,0 +1,557 @@ +/* + * Device Tree Source for Qualcomm MDM9615 SoC + * + * Copyright (C) 2016 BayLibre, SAS. + * Author : Neil Armstrong + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +/include/ "skeleton.dtsi" + +#include +#include +#include +#include +#include + +/ { + model = "Qualcomm MDM9615"; + compatible = "qcom,mdm9615"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a5"; + device_type = "cpu"; + next-level-cache = <&L2>; + }; + }; + + cpu-pmu { + compatible = "arm,cortex-a5-pmu"; + interrupts = ; + }; + + clocks { + cxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + }; + + regulators { + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + L2: l2-cache@2040000 { + compatible = "arm,pl310-cache"; + reg = <0x02040000 0x1000>; + arm,data-latency = <2 2 0>; + cache-unified; + cache-level = <2>; + }; + + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x02000000 0x1000>, + <0x02002000 0x1000>; + }; + + timer@200a000 { + compatible = "qcom,kpss-timer", "qcom,msm-timer"; + interrupts = , + , + ; + reg = <0x0200a000 0x100>; + clock-frequency = <27000000>, + <32768>; + cpu-offset = <0x80000>; + }; + + msmgpio: pinctrl@800000 { + compatible = "qcom,mdm9615-pinctrl"; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x800000 0x4000>; + }; + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-mdm9615"; + #clock-cells = <1>; + #reset-cells = <1>; + reg = <0x900000 0x4000>; + }; + + lcc: clock-controller@28000000 { + compatible = "qcom,lcc-mdm9615"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + l2cc: clock-controller@2011000 { + compatible = "syscon"; + reg = <0x02011000 0x1000>; + }; + + rng@1a500000 { + compatible = "qcom,prng"; + reg = <0x1a500000 0x200>; + clocks = <&gcc PRNG_CLK>; + clock-names = "core"; + assigned-clocks = <&gcc PRNG_CLK>; + assigned-clock-rates = <32000000>; + }; + + gsbi2: gsbi@16100000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <2>; + reg = <0x16100000 0x100>; + clocks = <&gcc GSBI2_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gsbi2_i2c: i2c@16180000 { + compatible = "qcom,i2c-qup-v1.1.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x16180000 0x1000>; + interrupts = ; + + clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + gsbi3: gsbi@16200000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <3>; + reg = <0x16200000 0x100>; + clocks = <&gcc GSBI3_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gsbi3_spi: spi@16280000 { + compatible = "qcom,spi-qup-v1.1.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x16280000 0x1000>; + interrupts = ; + spi-max-frequency = <24000000>; + + clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + gsbi4: gsbi@16300000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <4>; + reg = <0x16300000 0x100>; + clocks = <&gcc GSBI4_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi4_serial: serial@16340000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16340000 0x1000>, + <0x16300000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + gsbi5: gsbi@16400000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <5>; + reg = <0x16400000 0x100>; + clocks = <&gcc GSBI5_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi5_i2c: i2c@16480000 { + compatible = "qcom,i2c-qup-v1.1.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x16480000 0x1000>; + interrupts = ; + + /* QUP clock is not initialized, set rate */ + assigned-clocks = <&gcc GSBI5_QUP_CLK>; + assigned-clock-rates = <24000000>; + + clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi5_serial: serial@16440000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16440000 0x1000>, + <0x16400000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + + pmicintc: pmic@0 { + compatible = "qcom,pm8018", "qcom,pm8921"; + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + + pwrkey@1c { + compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey"; + reg = <0x1c>; + interrupt-parent = <&pmicintc>; + interrupts = <50 IRQ_TYPE_EDGE_RISING>, + <51 IRQ_TYPE_EDGE_RISING>; + debounce = <15625>; + pull-up; + }; + + pmicmpp: mpp@50 { + compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp"; + interrupt-parent = <&pmicintc>; + interrupts = <24 IRQ_TYPE_NONE>, + <25 IRQ_TYPE_NONE>, + <26 IRQ_TYPE_NONE>, + <27 IRQ_TYPE_NONE>, + <28 IRQ_TYPE_NONE>, + <29 IRQ_TYPE_NONE>; + reg = <0x50>; + gpio-controller; + #gpio-cells = <2>; + }; + + rtc@11d { + compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc"; + interrupt-parent = <&pmicintc>; + interrupts = <39 IRQ_TYPE_EDGE_RISING>; + reg = <0x11d>; + allow-set-time; + }; + + pmicgpio: gpio@150 { + compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio"; + interrupt-parent = <&pmicintc>; + interrupts = <24 IRQ_TYPE_NONE>, + <25 IRQ_TYPE_NONE>, + <26 IRQ_TYPE_NONE>, + <27 IRQ_TYPE_NONE>, + <28 IRQ_TYPE_NONE>, + <29 IRQ_TYPE_NONE>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; + + sdcc1bam: dma@12182000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x8000>; + interrupts = ; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + sdcc2bam: dma@12142000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x12142000 0x8000>; + interrupts = ; + clocks = <&gcc SDC2_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + sdcc1: sdcc@12180000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12180000 0x2000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + assigned-clocks = <&gcc SDC1_CLK>; + assigned-clock-rates = <400000>; + }; + + sdcc2: sdcc@12140000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12140000 0x2000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <48000000>; + no-1-8-v; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc2bam 2>, <&sdcc2bam 1>; + dma-names = "tx", "rx"; + assigned-clocks = <&gcc SDC2_CLK>; + assigned-clock-rates = <400000>; + }; + }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-mdm9615", "syscon"; + reg = <0x1a400000 0x100>; + }; + + rpm: rpm@108000 { + compatible = "qcom,rpm-mdm9615"; + reg = <0x108000 0x1000>; + + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = , + , + ; + interrupt-names = "ack", "err", "wakeup"; + + regulators { + compatible = "qcom,rpm-pm8018-regulators"; + + vin_lvs1-supply = <&pm8018_s3>; + + vdd_l7-supply = <&pm8018_s4>; + vdd_l8-supply = <&pm8018_s3>; + vdd_l9_l10_l11_l12-supply = <&pm8018_s5>; + + /* Buck SMPS */ + pm8018_s1: s1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s2: s2 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s3: s3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s4: s4 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2200000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s5: s5 { + regulator-always-on; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + /* PMOS LDO */ + pm8018_l2: l2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8018_l3: l3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8018_l4: l4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + pm8018_l5: l5 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + pm8018_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + pm8018_l7: l7 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; + + pm8018_l8: l8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8018_l9: l9 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + + pm8018_l10: l10 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8018_l11: l11 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8018_l12: l12 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8018_l13: l13 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8018_l14: l14 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + /* Low Voltage Switch */ + pm8018_lvs1: lvs1 { + bias-pull-down; + }; + }; + }; + }; +}; -- cgit v1.2.3 From 3106dba69640cf7003ca8b9de41e6d655ac408c9 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 23 Aug 2016 13:39:05 +0200 Subject: ARM: dts: Add Sierra Wireless WP8548 dtsi In order to support the Sierra Wireless WP8548 module based on the Qualcomm MDM9615 SoC, add a dtsi file. Signed-off-by: Neil Armstrong Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi | 170 +++++++++++++++++++++++++++++ 1 file changed, 170 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi new file mode 100644 index 000000000000..7869898e392d --- /dev/null +++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi @@ -0,0 +1,170 @@ +/* + * Device Tree Source for Sierra Wireless WP8548 Module + * + * Copyright (C) 2016 BayLibre, SAS. + * Author : Neil Armstrong + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "qcom-mdm9615.dtsi" + +/ { + model = "Sierra Wireless WP8548 Module"; + compatible = "swir,wp8548", "qcom,mdm9615"; + + memory { + reg = <0x48000000 0x7F00000>; + }; +}; + +&msmgpio { + pinctrl-0 = <&reset_out_pins>; + pinctrl-names = "default"; + + gsbi3_pins: gsbi3_pins { + mux { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "gsbi3"; + drive-strength = <8>; + bias-disable; + }; + }; + + gsbi4_pins: gsbi4_pins { + mux { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "gsbi4"; + drive-strength = <8>; + bias-disable; + }; + }; + + gsbi5_i2c_pins: gsbi5_i2c_pins { + pin16 { + pins = "gpio16"; + function = "gsbi5_i2c"; + drive-strength = <8>; + bias-disable; + }; + + pin17 { + pins = "gpio17"; + function = "gsbi5_i2c"; + drive-strength = <2>; + bias-disable; + }; + }; + + gsbi5_uart_pins: gsbi5_uart_pins { + mux { + pins = "gpio18", "gpio19"; + function = "gsbi5_uart"; + drive-strength = <8>; + bias-disable; + }; + }; + + reset_out_pins: reset_out_pins { + pins { + pins = "gpio66"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-high; + }; + }; +}; + +&pmicgpio { + usb_vbus_5v_pins: usb_vbus_5v_pins { + pins = "gpio4"; + function = "normal"; + output-high; + bias-disable; + qcom,drive-strength = <1>; + power-source = <2>; + }; +}; + +&gsbi3 { + status = "ok"; + qcom,mode = ; +}; + +&gsbi3_spi { + status = "ok"; + pinctrl-0 = <&gsbi3_pins>; + pinctrl-names = "default"; + assigned-clocks = <&gcc GSBI3_QUP_CLK>; + assigned-clock-rates = <24000000>; +}; + +&gsbi4 { + status = "ok"; + qcom,mode = ; +}; + +&gsbi4_serial { + status = "ok"; + pinctrl-0 = <&gsbi4_pins>; + pinctrl-names = "default"; +}; + +&gsbi5 { + status = "ok"; + qcom,mode = ; +}; + +&gsbi5_i2c { + status = "ok"; + clock-frequency = <200000>; + pinctrl-0 = <&gsbi5_i2c_pins>; + pinctrl-names = "default"; +}; + +&gsbi5_serial { + status = "ok"; + pinctrl-0 = <&gsbi5_uart_pins>; + pinctrl-names = "default"; +}; + +&sdcc1 { + status = "ok"; +}; -- cgit v1.2.3 From 8ab8a8c3945baef7d0c69501590c2bed0cab95d8 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 23 Aug 2016 13:39:06 +0200 Subject: ARM: dts: Add WP8548 based MangOH Green board DTS Add support for the Sierra Wireless MangOH Green board with the Sierra Wireless WP8548 Module. Signed-off-by: Neil Armstrong Signed-off-by: Andy Gross --- arch/arm/boot/dts/Makefile | 3 +- .../boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts | 281 +++++++++++++++++++++ 2 files changed, 283 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index befcd2619902..c7f482d634f0 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -620,7 +620,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-msm8660-surf.dtb \ qcom-msm8960-cdp.dtb \ qcom-msm8974-lge-nexus5-hammerhead.dtb \ - qcom-msm8974-sony-xperia-honami.dtb + qcom-msm8974-sony-xperia-honami.dtb \ + qcom-mdm9615-wp8548-mangoh-green.dtb dtb-$(CONFIG_ARCH_REALVIEW) += \ arm-realview-pb1176.dtb \ arm-realview-pb11mp.dtb \ diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts new file mode 100644 index 000000000000..26160c324802 --- /dev/null +++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts @@ -0,0 +1,281 @@ +/* + * Device Tree Source for mangOH Green Board with WP8548 Module + * + * Copyright (C) 2016 BayLibre, SAS. + * Author : Neil Armstrong + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +#include "qcom-mdm9615-wp8548.dtsi" +#include +#include + +/ { + model = "MangOH Green with WP8548 Module"; + compatible = "swir,mangoh-green-wp8548", "swir,wp8548", "qcom,mdm9615"; + + aliases { + spi0 = &gsbi3_spi; + serial0 = &gsbi4_serial; + serial1 = &gsbi5_serial; + i2c0 = &gsbi5_i2c; + mmc0 = &sdcc1; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; +}; + +&msmgpio { + /* MangOH GPIO Mapping : + * - 2 : GPIOEXP_INT2 + * - 7 : IOT1_GPIO2 + * - 8 : IOT0_GPIO4 + * - 13: IOT0_GPIO3 + * - 21: IOT1_GPIO4 + * - 22: IOT2_GPIO1 + * - 23: IOT2_GPIO2 + * - 24: IOT2_GPIO3 + * - 25: IOT1_GPIO1 + * - 32: IOT1_GPIO3 + * - 33: IOT0_GPIO2 + * - 42: IOT0_GPIO1 and SD Card Detect + */ + + gpioext1_pins: gpioext1_pins { + pins { + pins = "gpio2"; + function = "gpio"; + input-enable; + bias-disable; + }; + }; + + sdc_cd_pins: sdc_cd_pins { + pins { + pins = "gpio42"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&gsbi3_spi { + spi@0 { + compatible = "swir,mangoh-iotport-spi", "spidev"; + spi-max-frequency = <24000000>; + reg = <0>; + }; +}; + +&gsbi5_i2c { + mux@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + i2c_iot0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_iot1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_iot2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + usbhub: hub@8 { + compatible = "smsc,usb3503a"; + reg = <0x8>; + connect-gpios = <&gpioext2 1 GPIO_ACTIVE_HIGH>; + intn-gpios = <&gpioext2 0 GPIO_ACTIVE_LOW>; + initial-mode = <1>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + gpioext0: gpio@3e { + /* GPIO Expander 0 Mapping : + * - 0: ARDUINO_RESET_Level shift + * - 1: BattChrgr_PG_N + * - 2: BattGauge_GPIO + * - 3: LED_ON (out active high) + * - 4: ATmega_reset_GPIO + * - 5: X + * - 6: PCM_ANALOG_SELECT (out active high) + * - 7: X + * - 8: Board_rev_res1 (in) + * - 9: Board_rev_res2 (in) + * - 10: UART_EXP1_ENn (out active low / pull-down) + * - 11: UART_EXP1_IN (out pull-down) + * - 12: UART_EXP2_IN (out pull-down) + * - 13: SDIO_SEL (out pull-down) + * - 14: SPI_EXP1_ENn (out active low / pull-down) + * - 15: SPI_EXP1_IN (out pull-down) + */ + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1509q"; + reg = <0x3e>; + interrupt-parent = <&gpioext1>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + + probe-reset; + + gpio-controller; + interrupt-controller; + }; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + gpioext1: gpio@3f { + /* GPIO Expander 1 Mapping : + * - 0: GPIOEXP_INT1 + * - 1: Battery detect + * - 2: GPIO_SCF3_RESET + * - 3: LED_CARD_DETECT_IOT0 (in) + * - 4: LED_CARD_DETECT_IOT1 (in) + * - 5: LED_CARD_DETECT_IOT2 (in) + * - 6: UIM2_PWM_SELECT + * - 7: UIM2_M2_S_SELECT + * - 8: TP900 + * - 9: SENSOR_INT1 (in) + * - 10: SENSOR_INT2 (in) + * - 11: CARD_DETECT_IOT0 (in pull-up) + * - 12: CARD_DETECT_IOT2 (in pull-up) + * - 13: CARD_DETECT_IOT1 (in pull-up) + * - 14: GPIOEXP_INT3 (in active low / pull-up) + * - 15: BattChrgr_INT_N + */ + pinctrl-0 = <&gpioext1_pins>; + pinctrl-names = "default"; + + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1509q"; + reg = <0x3f>; + interrupt-parent = <&msmgpio>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + + probe-reset; + + gpio-controller; + interrupt-controller; + }; + }; + + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + + gpioext2: gpio@70 { + /* GPIO Expander 2 Mapping : + * - 0: USB_HUB_INTn + * - 1: HUB_CONNECT + * - 2: GPIO_IOT2_RESET (out active low / pull-up) + * - 3: GPIO_IOT1_RESET (out active low / pull-up) + * - 4: GPIO_IOT0_RESET (out active low / pull-up) + * - 5: TP901 + * - 6: TP902 + * - 7: TP903 + * - 8: UART_EXP2_ENn (out active low / pull-down) + * - 9: PCM_EXP1_ENn (out active low) + * - 10: PCM_EXP1_SEL (out) + * - 11: ARD_FTDI + * - 12: TP904 + * - 13: TP905 + * - 14: TP906 + * - 15: RS232_Enable (out active high / pull-up) + */ + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1509q"; + reg = <0x70>; + interrupt-parent = <&gpioext1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + + probe-reset; + + gpio-controller; + interrupt-controller; + }; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&sdcc1 { + pinctrl-0 = <&sdc_cd_pins>; + pinctrl-names = "default"; + disable-wp; + cd-gpios = <&msmgpio 42 GPIO_ACTIVE_LOW>; /* Active low CD */ +}; -- cgit v1.2.3 From a511e97c495f70bdcc9459d23e259f22c985896a Mon Sep 17 00:00:00 2001 From: Bhushan Shah Date: Wed, 20 Jul 2016 11:56:10 +0530 Subject: ARM: dts: qcom: msm8974-hammerhead: Add sdhci1 node This introduces the eMMC sdhci node and its pinctrl state Signed-off-by: Bhushan Shah Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- .../dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index c0fb4a698c56..382bcc3231a9 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -224,6 +224,35 @@ status = "ok"; }; + pinctrl@fd510000 { + sdhc1_pin_a: sdhc1-pin-active { + clk { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + }; + + sdhci@f9824900 { + status = "ok"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + bus-width = <8>; + non-removable; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc1_pin_a>; + }; + gpio-keys { compatible = "gpio-keys"; input-name = "gpio-keys"; -- cgit v1.2.3 From e77a3a7841f58cae5249e69db8521a04d8be6f25 Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Fri, 23 Sep 2016 12:03:06 +0530 Subject: arm: dts: qcom: apq8064: Add display DT nodes APQ8064 contains a MDP4 based display controller. It contains a HDMI, LVDS and 2 DSI outputs. Add display DT nodes for MDP4, HDMI TX and HDMI PHY. MDP4 based display blocks have a flat device hierarchy. Nodes for other outputs will be added later. Cc: devicetree@vger.kernel.org Tested-by: John Stultz Signed-off-by: Archit Taneja Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8064.dtsi | 91 +++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 1dbe697b2e90..5b3aaaa7a588 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1095,6 +1095,97 @@ reset-names = "axi", "ahb", "por", "pci", "phy"; status = "disabled"; }; + + hdmi: hdmi-tx@4a00000 { + compatible = "qcom,hdmi-tx-8960"; + reg = <0x04a00000 0x2f0>; + reg-names = "core_physical"; + interrupts = ; + clocks = <&mmcc HDMI_APP_CLK>, + <&mmcc HDMI_M_AHB_CLK>, + <&mmcc HDMI_S_AHB_CLK>; + clock-names = "core_clk", + "master_iface_clk", + "slave_iface_clk"; + + phys = <&hdmi_phy>; + phy-names = "hdmi-phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hdmi_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + hdmi_out: endpoint { + }; + }; + }; + }; + + hdmi_phy: hdmi-phy@4a00400 { + compatible = "qcom,hdmi-phy-8960"; + reg = <0x4a00400 0x60>, + <0x4a00500 0x100>; + reg-names = "hdmi_phy", + "hdmi_pll"; + + clocks = <&mmcc HDMI_S_AHB_CLK>; + clock-names = "slave_iface_clk"; + }; + + mdp: mdp@5100000 { + compatible = "qcom,mdp4"; + reg = <0x05100000 0xf0000>; + interrupts = ; + clocks = <&mmcc MDP_CLK>, + <&mmcc MDP_AHB_CLK>, + <&mmcc MDP_AXI_CLK>, + <&mmcc MDP_LUT_CLK>, + <&mmcc HDMI_TV_CLK>, + <&mmcc MDP_TV_CLK>; + clock-names = "core_clk", + "iface_clk", + "bus_clk", + "lut_clk", + "hdmi_clk", + "tv_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp_lvds_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + mdp_dsi1_out: endpoint { + }; + }; + + port@2 { + reg = <2>; + mdp_dsi2_out: endpoint { + }; + }; + + port@3 { + reg = <3>; + mdp_dtv_out: endpoint { + }; + }; + }; + }; }; }; #include "qcom-apq8064-pins.dtsi" -- cgit v1.2.3 From c809801d4ceb5185b1c670562a94aef6defe9a70 Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Fri, 23 Sep 2016 12:03:07 +0530 Subject: arm: dts: qcom: apq8064-ifc6410: Add HDMI support Add HDMI support on IFC6410. Populate the regulators required by HDMI-TX and PHY. Establish the link between the MDP4 DTV encoder and HDMI. Create a generic micro HDMI connector DT node. The msm drm driver doesn't parse for HDMI connectors in DT, but it will do so later. Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 74 ++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 2eeb0904eaa7..3d37cab3b9a9 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -43,6 +43,17 @@ }; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + }; + soc { pinctrl@800000 { card_detect: card_detect { @@ -64,6 +75,25 @@ bias-disable; }; }; + + hdmi_pinctrl: hdmi-pinctrl { + mux { + pins = "gpio70", "gpio71", "gpio72"; + function = "hdmi"; + }; + + pinconf_ddc { + pins = "gpio70", "gpio71"; + bias-pull-up; + drive-strength = <2>; + }; + + pinconf_hpd { + pins = "gpio72"; + bias-pull-down; + drive-strength = <16>; + }; + }; }; rpm@108000 { @@ -329,5 +359,49 @@ mmc-pwrseq = <&sdcc4_pwrseq>; }; }; + + hdmi-tx@4a00000 { + status = "okay"; + + core-vdda-supply = <&pm8921_hdmi_switch>; + hdmi-mux-supply = <&ext_3p3v>; + + hpd-gpios = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pinctrl>; + + ports { + port@0 { + endpoint { + remote-endpoint = <&mdp_dtv_out>; + }; + }; + + port@1 { + endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-phy@4a00400 { + status = "okay"; + + core-vdda-supply = <&pm8921_hdmi_switch>; + }; + + mdp@5100000 { + status = "okay"; + + ports { + port@3 { + endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; + }; }; }; -- cgit v1.2.3 From f078eac68e8da3689385d96262caa10ca1ff0e0a Mon Sep 17 00:00:00 2001 From: John Stultz Date: Fri, 23 Sep 2016 17:01:04 -0700 Subject: arm: dts: qcom: apq8064: Add dsi, gpu and iommu nodes Adds the core gpu, and dsi nodes for the apq8064 needed to get graphics working on the nexus7 and other devices. These apply on top of Archit's patch set that enables HDMI for IFC6410 Feedback would be greatly appreciated! Cc: Archit Taneja Cc: vinay simha Cc: andy.gross@linaro.org Cc: robdclark@gmail.com Cc: linux-arm-msm@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: John Stultz Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8064.dtsi | 230 ++++++++++++++++++++++++++++++++++++ 1 file changed, 230 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 5b3aaaa7a588..268bd470c865 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1060,6 +1060,231 @@ reg = <0x1a400000 0x100>; }; + gpu: adreno-3xx@4300000 { + compatible = "qcom,adreno-3xx"; + reg = <0x04300000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = ; + interrupt-names = "kgsl_3d0_irq"; + clock-names = + "core_clk", + "iface_clk", + "mem_clk", + "mem_iface_clk"; + clocks = + <&mmcc GFX3D_CLK>, + <&mmcc GFX3D_AHB_CLK>, + <&mmcc GFX3D_AXI_CLK>, + <&mmcc MMSS_IMEM_AHB_CLK>; + qcom,chipid = <0x03020002>; + + iommus = <&gfx3d 0 + &gfx3d 1 + &gfx3d 2 + &gfx3d 3 + &gfx3d 4 + &gfx3d 5 + &gfx3d 6 + &gfx3d 7 + &gfx3d 8 + &gfx3d 9 + &gfx3d 10 + &gfx3d 11 + &gfx3d 12 + &gfx3d 13 + &gfx3d 14 + &gfx3d 15 + &gfx3d 16 + &gfx3d 17 + &gfx3d 18 + &gfx3d 19 + &gfx3d 20 + &gfx3d 21 + &gfx3d 22 + &gfx3d 23 + &gfx3d 24 + &gfx3d 25 + &gfx3d 26 + &gfx3d 27 + &gfx3d 28 + &gfx3d 29 + &gfx3d 30 + &gfx3d 31 + &gfx3d1 0 + &gfx3d1 1 + &gfx3d1 2 + &gfx3d1 3 + &gfx3d1 4 + &gfx3d1 5 + &gfx3d1 6 + &gfx3d1 7 + &gfx3d1 8 + &gfx3d1 9 + &gfx3d1 10 + &gfx3d1 11 + &gfx3d1 12 + &gfx3d1 13 + &gfx3d1 14 + &gfx3d1 15 + &gfx3d1 16 + &gfx3d1 17 + &gfx3d1 18 + &gfx3d1 19 + &gfx3d1 20 + &gfx3d1 21 + &gfx3d1 22 + &gfx3d1 23 + &gfx3d1 24 + &gfx3d1 25 + &gfx3d1 26 + &gfx3d1 27 + &gfx3d1 28 + &gfx3d1 29 + &gfx3d1 30 + &gfx3d1 31>; + + qcom,gpu-pwrlevels { + compatible = "qcom,gpu-pwrlevels"; + qcom,gpu-pwrlevel@0 { + qcom,gpu-freq = <450000000>; + }; + qcom,gpu-pwrlevel@1 { + qcom,gpu-freq = <27000000>; + }; + }; + }; + + mmss_sfpb: syscon@5700000 { + compatible = "syscon"; + reg = <0x5700000 0x70>; + }; + + dsi0: mdss_dsi@4700000 { + compatible = "qcom,mdss-dsi-ctrl"; + label = "MDSS DSI CTRL->0"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + reg = <0x04700000 0x200>; + reg-names = "dsi_ctrl"; + + clocks = <&mmcc DSI_M_AHB_CLK>, + <&mmcc DSI_S_AHB_CLK>, + <&mmcc AMP_AHB_CLK>, + <&mmcc DSI_CLK>, + <&mmcc DSI1_BYTE_CLK>, + <&mmcc DSI_PIXEL_CLK>, + <&mmcc DSI1_ESC_CLK>; + clock-names = "iface_clk", "bus_clk", "core_mmss_clk", + "src_clk", "byte_clk", "pixel_clk", + "core_clk"; + + assigned-clocks = <&mmcc DSI1_BYTE_SRC>, + <&mmcc DSI1_ESC_SRC>, + <&mmcc DSI_SRC>, + <&mmcc DSI_PIXEL_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi0_phy 1>; + syscon-sfpb = <&mmss_sfpb>; + phys = <&dsi0_phy>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + + dsi0_phy: dsi-phy@4700200 { + compatible = "qcom,dsi-phy-28nm-8960"; + #clock-cells = <1>; + + reg = <0x04700200 0x100>, + <0x04700300 0x200>, + <0x04700500 0x5c>; + reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; + clock-names = "iface_clk"; + clocks = <&mmcc DSI_M_AHB_CLK>; + }; + + + mdp_port0: iommu@7500000 { + compatible = "qcom,apq8064-iommu"; + #iommu-cells = <1>; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc MDP_AXI_CLK>; + reg = <0x07500000 0x100000>; + interrupts = + , + ; + qcom,ncb = <2>; + }; + + mdp_port1: iommu@7600000 { + compatible = "qcom,apq8064-iommu"; + #iommu-cells = <1>; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc MDP_AXI_CLK>; + reg = <0x07600000 0x100000>; + interrupts = + , + ; + qcom,ncb = <2>; + }; + + gfx3d: iommu@7c00000 { + compatible = "qcom,apq8064-iommu"; + #iommu-cells = <1>; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc GFX3D_AXI_CLK>; + reg = <0x07c00000 0x100000>; + interrupts = + , + ; + qcom,ncb = <3>; + }; + + gfx3d1: iommu@7d00000 { + compatible = "qcom,apq8064-iommu"; + #iommu-cells = <1>; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc GFX3D_AXI_CLK>; + reg = <0x07d00000 0x100000>; + interrupts = + , + ; + qcom,ncb = <3>; + }; + pcie: pci@1b500000 { compatible = "qcom,pcie-apq8064", "snps,dw-pcie"; reg = <0x1b500000 0x1000 @@ -1157,6 +1382,11 @@ "hdmi_clk", "tv_clk"; + iommus = <&mdp_port0 0 + &mdp_port0 2 + &mdp_port1 0 + &mdp_port1 2>; + ports { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From a3e6e13addee8335926e4e5ea4e8f5caf98e783c Mon Sep 17 00:00:00 2001 From: John Stultz Date: Fri, 23 Sep 2016 17:01:05 -0700 Subject: arm: dts: qcom: apq8064-nexus7: Add DSI and panel nodes Add DSI and panel nodes to get graphics up and running on the Nexus7. This still depends on the panel driver being present along with the rpmclk code. Feedback would be greatly appreciated! Cc: Archit Taneja Cc: vinay simha Cc: andy.gross@linaro.org Cc: robdclark@gmail.com Cc: linux-arm-msm@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: John Stultz Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 63 +++++++++++++++++++++- 1 file changed, 61 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts index b72e09506448..4225652aa880 100644 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts @@ -99,6 +99,7 @@ l2 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; + regulator-always-on; }; /* msm_otg-HSUSB_3p3 */ @@ -133,13 +134,14 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; bias-pull-down; + regulator-always-on; }; /* pwm_power for backlight */ l17 { regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3600000>; - bias-pull-down; + regulator-max-microvolt = <3000000>; + regulator-always-on; }; /* camera, qdsp6 */ @@ -184,6 +186,63 @@ }; }; + mdp@5100000 { + status = "okay"; + ports { + port@1 { + mdp_dsi1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + + dsi0: mdss_dsi@4700000 { + status = "okay"; + vdda-supply = <&pm8921_l2>;/*VDD_MIPI1 to 4*/ + vdd-supply = <&pm8921_l8>; + vddio-supply = <&pm8921_lvs7>; + avdd-supply = <&pm8921_l11>; + vcss-supply = <&ext_3p3v>; + + panel@0 { + reg = <0>; + compatible = "jdi,lt070me05000"; + + vddp-supply = <&pm8921_l17>; + iovcc-supply = <&pm8921_lvs7>; + + enable-gpios = <&pm8921_gpio 36 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm_pinmux 54 GPIO_ACTIVE_LOW>; + dcdc-en-gpios = <&pm8921_gpio 23 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + ports { + port@0 { + dsi0_in: endpoint { + remote-endpoint = <&mdp_dsi1_out>; + }; + }; + + port@1 { + dsi0_out: endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; + }; + + dsi-phy@4700200 { + status = "okay"; + vddio-supply = <&pm8921_lvs7>;/*VDD_PLL2_1 to 7*/ + }; + gsbi@16200000 { status = "okay"; qcom,mode = ; -- cgit v1.2.3 From 663286e7e63caaed74718d1919500646fd2ceb1b Mon Sep 17 00:00:00 2001 From: John Stultz Date: Fri, 23 Sep 2016 17:13:33 -0700 Subject: arm: dts: qcom: apq8064-nexus7: Add pstore support to nexus7 Add pstore support for the nexus7. This was useful in debugging a crash where the cpus were getting stuck with irqs off and serial output wasn't reliably working. Cc: Kees Cook Cc: Bjorn Andersson Cc: Rob Clark Cc: Stephen Boyd Cc: Andy Gross Cc: Vinay Simha Cc: Archit Taneja Cc: linux-arm-msm@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: John Stultz Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts index 4225652aa880..e39440a86739 100644 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts @@ -15,6 +15,20 @@ stdout-path = "serial0:115200n8"; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@88d00000{ + compatible = "ramoops"; + reg = <0x88d00000 0x100000>; + record-size = <0x00020000>; + console-size = <0x00020000>; + ftrace-size = <0x00020000>; + }; + }; + ext_3p3v: regulator-fixed@1 { compatible = "regulator-fixed"; regulator-min-microvolt = <3300000>; -- cgit v1.2.3 From e3770594c4c8db041b1d385234aaa911734dd0b8 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 25 Oct 2016 00:22:12 +0200 Subject: ARM: dts: add EBI2 to the Qualcomm MSM8660 DTSI This adds the external bus interface EBI2 to the MSM8660 device tree, albeit with status = "disabled" so that devices actually using EBI2 can turn it on if needed. Signed-off-by: Linus Walleij Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-msm8660.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 8c65e0d82559..4d828f810746 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -141,6 +141,23 @@ }; }; + external-bus@1a100000 { + compatible = "qcom,msm8660-ebi2"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x0 0x1a800000 0x00800000>, + <1 0x0 0x1b000000 0x00800000>, + <2 0x0 0x1b800000 0x00800000>, + <3 0x0 0x1d000000 0x08000000>, + <4 0x0 0x1c800000 0x00800000>, + <5 0x0 0x1c000000 0x00800000>; + reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>; + reg-names = "ebi2", "xmem"; + clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>; + clock-names = "ebi2x", "ebi2"; + status = "disabled"; + }; + qcom,ssbi@500000 { compatible = "qcom,ssbi"; reg = <0x500000 0x1000>; -- cgit v1.2.3 From 4c52ffc708c90b2985f941db5490145530e4df69 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 25 Oct 2016 00:22:20 +0200 Subject: ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard The SMSC9112 ethernet controller is connected to chip select 2 on the EBI2 bus on the APQ8060 Dragonboard. We set this up by activating EBI2, creating a chipselect entry as a subnode, and then putting the ethernet controller in a subnode of the chipselect. After the chipselect is configured, the SMSC device will be instantiated. Signed-off-by: Linus Walleij Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8060-dragonboard.dts | 119 +++++++++++++++++++++++++ 1 file changed, 119 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index 6c0038398ef2..4b8872cc8bf9 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -51,6 +51,29 @@ regulator-boot-on; }; + /* GPIO controlled ethernet power regulator */ + dragon_veth: xc622a331mrg { + compatible = "regulator-fixed"; + regulator-name = "XC6222A331MR-G"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vph>; + gpio = <&pm8058_gpio 40 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_veth_gpios>; + regulator-always-on; + }; + + /* VDDvario fixed regulator */ + dragon_vario: nds332p { + compatible = "regulator-fixed"; + regulator-name = "NDS332P"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&pm8058_s3>; + }; + /* This is a levelshifter for SDCC5 */ dragon_vio_txb: txb0104rgyr { compatible = "regulator-fixed"; @@ -167,6 +190,36 @@ bias-pull-up; }; }; + + dragon_ebi2_pins: ebi2 { + /* + * Pins used by EBI2 on the Dragonboard, actually only + * CS2 is used by a real peripheral. CS0 is just + * routed to a test point. + */ + mux0 { + pins = + /* "gpio39", CS1A_N this is not good to mux */ + "gpio40", /* CS2A_N */ + "gpio134"; /* CS0_N testpoint TP29 */ + function = "ebi2cs"; + }; + mux1 { + pins = + /* EBI2_ADDR_7 downto EBI2_ADDR_0 address bus */ + "gpio123", "gpio124", "gpio125", "gpio126", + "gpio127", "gpio128", "gpio129", "gpio130", + /* EBI2_DATA_15 downto EBI2_DATA_0 data bus */ + "gpio135", "gpio136", "gpio137", "gpio138", + "gpio139", "gpio140", "gpio141", "gpio142", + "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", + "gpio151", /* EBI2_OE_N */ + "gpio153", /* EBI2_ADV */ + "gpio157"; /* EBI2_WE_N */ + function = "ebi2"; + }; + }; }; qcom,ssbi@500000 { @@ -201,6 +254,15 @@ }; gpio@150 { + dragon_ethernet_gpios: ethernet-gpios { + pinconf { + pins = "gpio7"; + function = "normal"; + input-enable; + bias-disable; + power-source = ; + }; + }; dragon_bmp085_gpios: bmp085-gpios { pinconf { pins = "gpio16"; @@ -238,6 +300,14 @@ power-source = ; }; }; + dragon_veth_gpios: veth-gpios { + pinconf { + pins = "gpio40"; + function = "normal"; + bias-disable; + drive-push-pull; + }; + }; }; led@48 { @@ -322,6 +392,55 @@ }; }; + external-bus@1a100000 { + /* The EBI2 will instantiate first, then populate its children */ + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_ebi2_pins>; + + /* + * An on-board SMSC LAN9221 chip for "debug ethernet", + * which is actually just an ordinary ethernet on the + * EBI2. This has a 25MHz chrystal next to it, so no + * clocking is needed. + */ + ethernet-ebi2@2,0 { + compatible = "smsc,lan9221", "smsc,lan9115"; + reg = <2 0x0 0x100>; + /* + * GPIO7 has interrupt 198 on the PM8058 + * The second interrupt is the PME interrupt + * for network wakeup, connected to the TLMM. + */ + interrupts-extended = <&pmicintc 198 IRQ_TYPE_EDGE_FALLING>, + <&tlmm 29 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; + vdd33a-supply = <&dragon_veth>; + vddvario-supply = <&dragon_vario>; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_ethernet_gpios>; + phy-mode = "mii"; + reg-io-width = <2>; + smsc,force-external-phy; + /* IRQ on edge falling = active low */ + smsc,irq-active-low; + smsc,irq-push-pull; + + /* + * SLOW chipselect config + * Delay 9 cycles (140ns@64MHz) between SMSC + * LAN9221 Ethernet controller reads and writes + * on CS2. + */ + qcom,xmem-recovery-cycles = <0>; + qcom,xmem-write-hold-cycles = <3>; + qcom,xmem-write-delta-cycles = <31>; + qcom,xmem-read-delta-cycles = <28>; + qcom,xmem-write-wait-cycles = <9>; + qcom,xmem-read-wait-cycles = <9>; + }; + }; + rpm@104000 { /* * Set up of the PMIC RPM regulators for this board -- cgit v1.2.3