From e4bfde13e323f9ee5f2f38aa5cac0676dd656f8e Mon Sep 17 00:00:00 2001 From: Shunqian Zheng Date: Fri, 3 Apr 2020 13:15:37 -0300 Subject: arm64: dts: rockchip: add rx0 mipi-phy for rk3399 Designware MIPI D-PHY, used for ISP0 in rk3399. Verified with: make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml Signed-off-by: Shunqian Zheng Signed-off-by: Jacob Chen Signed-off-by: Helen Koike Link: https://lore.kernel.org/r/20200403161538.1375908-9-helen.koike@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 781b5c2cdb4d..f2ef0d8ba54b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1397,6 +1397,17 @@ status = "disabled"; }; + mipi_dphy_rx0: mipi-dphy-rx0 { + compatible = "rockchip,rk3399-mipi-dphy-rx0"; + clocks = <&cru SCLK_MIPIDPHY_REF>, + <&cru SCLK_DPHY_RX0_CFG>, + <&cru PCLK_VIO_GRF>; + clock-names = "dphy-ref", "dphy-cfg", "grf"; + power-domains = <&power RK3399_PD_VIO>; + #phy-cells = <0>; + status = "disabled"; + }; + u2phy0: usb2-phy@e450 { compatible = "rockchip,rk3399-usb2phy"; reg = <0xe450 0x10>; -- cgit v1.2.3