From 8abef06b63e639b910d202319be9e8151ac3a1ed Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 24 Sep 2014 15:16:01 +0200 Subject: ARM: zynq: DT: Add missing address for L2 pl310 By in sync with others node and add also baseaddr to the node name. Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-7000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 1836a60444fa..772381fe07bb 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -136,7 +136,7 @@ <0xF8F00100 0x100>; }; - L2: cache-controller { + L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; arm,data-latency = <3 2 2>; -- cgit v1.2.3