From 49727d30ea34e9721e226596f809cbcbdba78898 Mon Sep 17 00:00:00 2001 From: Sean Paul Date: Tue, 9 Sep 2014 15:58:46 -0400 Subject: ARM: tegra: Add APB_MISC_GP as a MIPI pad control bank This patch adds the APB_MISC_GP_MIPI_PAD_CTRL_0 as a pin-control bank on Tegra124 so the new MIPI pad control group can be muxed between CSI and DSI_B. Signed-off-by: Sean Paul Acked-by: Stephen Warren Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/tegra124.dtsi') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 478c555ebd96..af2eace5eb63 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -275,7 +275,8 @@ pinmux: pinmux@0,70000868 { compatible = "nvidia,tegra124-pinmux"; reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ - <0x0 0x70003000 0x0 0x434>; /* Mux registers */ + <0x0 0x70003000 0x0 0x434>, /* Mux registers */ + <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ }; /* -- cgit v1.2.3 From b26ea06babf5026f68d5da98edfc164f8aee7346 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 16 Apr 2014 09:09:34 +0200 Subject: ARM: tegra: Add memory controller support for Tegra124 Add the memory controller and wire up the interrupt that is used to report errors. Provide a reference to the memory controller clock and mark the device as being an IOMMU by adding an #iommu-cells property. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm/boot/dts/tegra124.dtsi') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index af2eace5eb63..5fcc6e704faa 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -552,6 +552,17 @@ reset-names = "fuse"; }; + mc: memory-controller@0,70019000 { + compatible = "nvidia,tegra124-mc"; + reg = <0x0 0x70019000 0x0 0x1000>; + clocks = <&tegra_car TEGRA124_CLK_MC>; + clock-names = "mc"; + + interrupts = ; + + #iommu-cells = <1>; + }; + sata@0,70020000 { compatible = "nvidia,tegra124-ahci"; -- cgit v1.2.3 From 5b605d4426e1dc38b6572bd42c151ad247359e3a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 26 Jun 2014 21:22:46 +0200 Subject: ARM: tegra: Enable IOMMU for display controllers on Tegra124 Add iommus properties to the device tree nodes for the two display controllers found on Tegra124. This will allow the display controllers to map physically non-contiguous buffers to I/O virtual contiguous address spaces so that they can be used for scan-out. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts/tegra124.dtsi') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 5fcc6e704faa..a9f3a3e1afc4 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -1,5 +1,6 @@ #include #include +#include #include #include #include @@ -102,6 +103,8 @@ resets = <&tegra_car 27>; reset-names = "dc"; + iommus = <&mc TEGRA_SWGROUP_DC>; + nvidia,head = <0>; }; @@ -115,6 +118,8 @@ resets = <&tegra_car 26>; reset-names = "dc"; + iommus = <&mc TEGRA_SWGROUP_DCB>; + nvidia,head = <1>; }; -- cgit v1.2.3