From 9232fcc99948e39d5be04fc1c1025bd4f7998739 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Wed, 8 Apr 2009 14:49:38 -0700 Subject: davinci: add default Kconfig, add HAVE_IDE Signed-off-by: Kevin Hilman --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/Kconfig') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e02b893fb909..bb57f35e7683 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -585,6 +585,7 @@ config ARCH_DAVINCI select ARCH_REQUIRE_GPIOLIB select HAVE_CLK select ZONE_DMA + select HAVE_IDE help Support for TI's DaVinci platform. -- cgit v1.2.3 From c5b736d093217890245a33e9a98fe92d6f3529bf Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Fri, 20 Mar 2009 17:29:01 -0700 Subject: davinci: major rework of clock, PLL, PSC infrastructure This is a significant rework of the low-level clock, PLL and Power Sleep Controller (PSC) implementation for the DaVinci family. The primary goal is to have better modeling if the hardware clocks and features with the aim of DVFS functionality. Highlights: - model PLLs and all PLL-derived clocks - model parent/child relationships of PLLs and clocks - convert to new clkdev layer - view clock frequency and refcount via /proc/davinci_clocks Special thanks to significant contributions and testing by David Brownell. Cc: David Brownell Signed-off-by: Kevin Hilman --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/Kconfig') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index bb57f35e7683..cfd99649ad85 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -586,6 +586,7 @@ config ARCH_DAVINCI select HAVE_CLK select ZONE_DMA select HAVE_IDE + select COMMON_CLKDEV help Support for TI's DaVinci platform. -- cgit v1.2.3 From fd87e081723089cba99df0b3d6f36ae2235c700a Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 16 Apr 2009 11:23:08 +0200 Subject: [ARM] pxa: remove duplicate select statements from Kconfig ARCH_PXA selects HAVE_CLK and COMMON_CLKDEV twice in arch/arm/Kconfig. Remove the second entry. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Eric Miao --- arch/arm/Kconfig | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm/Kconfig') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e02b893fb909..9909a93ec7fd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -486,8 +486,6 @@ config ARCH_PXA select HAVE_CLK select COMMON_CLKDEV select ARCH_REQUIRE_GPIOLIB - select HAVE_CLK - select COMMON_CLKDEV select GENERIC_TIME select GENERIC_CLOCKEVENTS select TICK_ONESHOT -- cgit v1.2.3 From 36b5437f33fb95196bef2345dede39fdcab3e431 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Fri, 17 Apr 2009 11:37:10 +0200 Subject: [ARM] pxa: remove unused CPU_FREQ_PXA Kconfig symbol cpufreq drivers for pxa2xx/3xx are now built-in automatically as soon as CPU_FREQ is enabled. Signed-off-by: Philipp Zabel Signed-off-by: Eric Miao --- arch/arm/Kconfig | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch/arm/Kconfig') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9909a93ec7fd..fb667cd43f70 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1169,12 +1169,6 @@ config CPU_FREQ_IMX If in doubt, say N. -config CPU_FREQ_PXA - bool - depends on CPU_FREQ && ARCH_PXA && PXA25x - default y - select CPU_FREQ_DEFAULT_GOV_USERSPACE - endif source "drivers/cpuidle/Kconfig" -- cgit v1.2.3 From 9cba3ccc8fe77b67aff2db8f5827d7cb752ce11f Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Thu, 30 Apr 2009 17:06:03 +0100 Subject: [ARM] 5488/1: ARM errata: Invalidation of the Instruction Cache operation can fail This patch implements the recommended workaround for erratum 411920 (ARM1136, ARM1156, ARM1176). Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/Kconfig') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 99875dd06f50..e28a76bd1793 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -740,6 +740,15 @@ if !MMU source "arch/arm/Kconfig-nommu" endif +config ARM_ERRATA_411920 + bool "ARM errata: Invalidation of the Instruction Cache operation can fail" + depends on CPU_V6 && !SMP + help + Invalidation of the Instruction Cache operation can + fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. + It does not affect the MPCore. This option enables the ARM Ltd. + recommended workaround. + endmenu source "arch/arm/common/Kconfig" -- cgit v1.2.3 From 7ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Thu, 30 Apr 2009 17:06:09 +0100 Subject: [ARM] 5487/1: ARM errata: Stale prediction on replaced interworking branch This patch adds the workaround for the 430973 Cortex-A8 (r1p0..r1p2) erratum. The BTAC/BTB is now flushed at every context switch. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/Kconfig | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm/Kconfig') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e28a76bd1793..84e4816362b3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -749,6 +749,22 @@ config ARM_ERRATA_411920 It does not affect the MPCore. This option enables the ARM Ltd. recommended workaround. +config ARM_ERRATA_430973 + bool "ARM errata: Stale prediction on replaced interworking branch" + depends on CPU_V7 + help + This option enables the workaround for the 430973 Cortex-A8 + (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb + interworking branch is replaced with another code sequence at the + same virtual address, whether due to self-modifying code or virtual + to physical address re-mapping, Cortex-A8 does not recover from the + stale interworking branch prediction. This results in Cortex-A8 + executing the new code sequence in the incorrect ARM or Thumb state. + The workaround enables the BTB/BTAC operations by setting ACTLR.IBE + and also flushes the branch target cache at every context switch. + Note that setting specific bits in the ACTLR register may not be + available in non-secure mode. + endmenu source "arch/arm/common/Kconfig" -- cgit v1.2.3 From 855c551f5b8cc3815d58e1056c1f1e7c461e2d24 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Thu, 30 Apr 2009 17:06:15 +0100 Subject: [ARM] 5490/1: ARM errata: Processor deadlock when a false hazard is created This patch adds a workaround for the 458693 Cortex-A8 (r2p0) erratum. It sets the corresponding bits in the auxiliary control register so that the PLD instruction becomes a NOP. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/Kconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm/Kconfig') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 84e4816362b3..49f85664083d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -765,6 +765,19 @@ config ARM_ERRATA_430973 Note that setting specific bits in the ACTLR register may not be available in non-secure mode. +config ARM_ERRATA_458693 + bool "ARM errata: Processor deadlock when a false hazard is created" + depends on CPU_V7 + help + This option enables the workaround for the 458693 Cortex-A8 (r2p0) + erratum. For very specific sequences of memory operations, it is + possible for a hazard condition intended for a cache line to instead + be incorrectly associated with a different cache line. This false + hazard might then cause a processor deadlock. The workaround enables + the L1 caching of the NEON accesses and disables the PLD instruction + in the ACTLR register. Note that setting specific bits in the ACTLR + register may not be available in non-secure mode. + endmenu source "arch/arm/common/Kconfig" -- cgit v1.2.3 From 0516e4643cd22fc9f535aef02ad1de66c382c93b Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Thu, 30 Apr 2009 17:06:20 +0100 Subject: [ARM] 5489/1: ARM errata: Data written to the L2 cache can be overwritten with stale data This patch is a workaround for the 460075 Cortex-A8 (r2p0) erratum. It configures the L2 cache auxiliary control register so that the Write Allocate mode for the L2 cache is disabled. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/Kconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/Kconfig') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 49f85664083d..9faccc411c2a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -778,6 +778,18 @@ config ARM_ERRATA_458693 in the ACTLR register. Note that setting specific bits in the ACTLR register may not be available in non-secure mode. +config ARM_ERRATA_460075 + bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" + depends on CPU_V7 + help + This option enables the workaround for the 460075 Cortex-A8 (r2p0) + erratum. Any asynchronous access to the L2 cache may encounter a + situation in which recent store transactions to the L2 cache are lost + and overwritten with stale memory contents from external memory. The + workaround disables the write-allocate mode for the L2 cache via the + ACTLR register. Note that setting specific bits in the ACTLR register + may not be available in non-secure mode. + endmenu source "arch/arm/common/Kconfig" -- cgit v1.2.3 From 9abf137c6dbf6eabb3add98fcd8352c3dd520568 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 16 Apr 2009 14:12:54 +0200 Subject: ARM: ARCH_MXC should select HAVE_CLK All i.MX platforms support calls and should select HAVE_CLK. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Sascha Hauer --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/Kconfig') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9faccc411c2a..e60ec54df334 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -454,6 +454,7 @@ config ARCH_MXC select ARCH_MTD_XIP select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB + select HAVE_CLK help Support for Freescale MXC/iMX-based family of processors -- cgit v1.2.3