From 07862c1cd6675cde2dd4bd64e64d704ea2185b79 Mon Sep 17 00:00:00 2001 From: Jonas Jensen Date: Wed, 17 Jul 2013 10:04:57 +0200 Subject: ARM: clocksource: Add support for MOXA ART SoCs This patch adds an clocksource driver for the main timer(s) found on MOXA ART SoCs. The MOXA ART SoC provides three separate timers with individual count/load/match registers, two are used here: TIMER1: clockevents, used to support oneshot and periodic events TIMER2: set up as a free running counter, used as clocksource Timers are preconfigured by bootloader to count down and interrupt on match or zero. Count increments every APB clock cycle and is automatically reloaded when it reaches zero. Signed-off-by: Jonas Jensen Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/timer/moxa,moxart-timer.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt new file mode 100644 index 000000000000..77c4cfa198ee --- /dev/null +++ b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt @@ -0,0 +1,17 @@ +MOXA ART timer + +Required properties: + +- compatible : Should be "moxa,moxart-timer" +- reg : Should contain registers location and length +- interrupts : Should contain the timer interrupt number +- clocks : Should contain phandle for APB clock "clkapb" + +Example: + + timer: timer@98400000 { + compatible = "moxa,moxart-timer"; + reg = <0x98400000 0x42>; + interrupts = <19 1>; + clocks = <&clkapb>; + }; -- cgit v1.2.3 From b662a8662436cd4815e1738d5f491a12dc289177 Mon Sep 17 00:00:00 2001 From: Jonas Jensen Date: Fri, 19 Jul 2013 13:12:59 +0200 Subject: ARM: clocksource: moxart: documentation: Fix device tree bindings document Fix device tree bindings document with the correct clock name. Signed-off-by: Jonas Jensen Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt index 77c4cfa198ee..ad0bf7f1a7e7 100644 --- a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt +++ b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt @@ -5,7 +5,7 @@ Required properties: - compatible : Should be "moxa,moxart-timer" - reg : Should contain registers location and length - interrupts : Should contain the timer interrupt number -- clocks : Should contain phandle for APB clock "clkapb" +- clocks : Should contain phandle for the MOXA ART core clock "coreclk" Example: @@ -13,5 +13,5 @@ Example: compatible = "moxa,moxart-timer"; reg = <0x98400000 0x42>; interrupts = <19 1>; - clocks = <&clkapb>; + clocks = <&coreclk>; }; -- cgit v1.2.3 From 766acb88a773dcbc98f2ae8d7ef8c147e2dccd99 Mon Sep 17 00:00:00 2001 From: Jonas Jensen Date: Fri, 26 Jul 2013 16:17:15 +0200 Subject: ARM: clocksource: moxart: documentation: Update device tree bindings document 1. describe compatible variable "Must be" instead of "Should be". 2. change description so it's from the point of view of the device Signed-off-by: Jonas Jensen Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt index ad0bf7f1a7e7..da2d510cae47 100644 --- a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt +++ b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt @@ -2,10 +2,10 @@ MOXA ART timer Required properties: -- compatible : Should be "moxa,moxart-timer" +- compatible : Must be "moxa,moxart-timer" - reg : Should contain registers location and length - interrupts : Should contain the timer interrupt number -- clocks : Should contain phandle for the MOXA ART core clock "coreclk" +- clocks : Should contain phandle for the clock that drives the counter Example: -- cgit v1.2.3 From d53ef114cf40a043e3cc3fa70dbcdfb268a7e4dc Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 18 Jul 2013 16:59:29 -0700 Subject: Documentation: Add memory mapped ARM architected timer binding Add a binding for the arm architected timer hardware's memory mapped interface. The mmio timer hardware is made up of one base frame and a collection of up to 8 timer frames, where each of the 8 timer frames can have either one or two views. A frame typically maps to a privilege level (user/kernel, hypervisor, secure). The first view has full access to the registers within a frame, while the second view can be restricted to particular registers within a frame. Each frame must support a physical timer. It's optional for a frame to support a virtual timer. Cc: devicetree-discuss@lists.ozlabs.org Cc: Marc Zyngier Cc: Mark Rutland Cc: Rob Herring Signed-off-by: Stephen Boyd Signed-off-by: Daniel Lezcano Acked-by: Mark Rutland --- .../devicetree/bindings/arm/arch_timer.txt | 59 ++++++++++++++++++++-- 1 file changed, 56 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt index 20746e5abe6f..06fc7602593a 100644 --- a/Documentation/devicetree/bindings/arm/arch_timer.txt +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt @@ -1,10 +1,14 @@ * ARM architected timer -ARM cores may have a per-core architected timer, which provides per-cpu timers. +ARM cores may have a per-core architected timer, which provides per-cpu timers, +or a memory mapped architected timer, which provides up to 8 frames with a +physical and optional virtual timer per frame. -The timer is attached to a GIC to deliver its per-processor interrupts. +The per-core architected timer is attached to a GIC to deliver its +per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC +to deliver its interrupts via SPIs. -** Timer node properties: +** CP15 Timer node properties: - compatible : Should at least contain one of "arm,armv7-timer" @@ -26,3 +30,52 @@ Example: <1 10 0xf08>; clock-frequency = <100000000>; }; + +** Memory mapped timer node properties: + +- compatible : Should at least contain "arm,armv7-timer-mem". + +- clock-frequency : The frequency of the main counter, in Hz. Optional. + +- reg : The control frame base address. + +Note that #address-cells, #size-cells, and ranges shall be present to ensure +the CPU can address a frame's registers. + +A timer node has up to 8 frame sub-nodes, each with the following properties: + +- frame-number: 0 to 7. + +- interrupts : Interrupt list for physical and virtual timers in that order. + The virtual timer interrupt is optional. + +- reg : The first and second view base addresses in that order. The second view + base address is optional. + +- status : "disabled" indicates the frame is not available for use. Optional. + +Example: + + timer@f0000000 { + compatible = "arm,armv7-timer-mem"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xf0000000 0x1000>; + clock-frequency = <50000000>; + + frame@f0001000 { + frame-number = <0> + interrupts = <0 13 0x8>, + <0 14 0x8>; + reg = <0xf0001000 0x1000>, + <0xf0002000 0x1000>; + }; + + frame@f0003000 { + frame-number = <1> + interrupts = <0 15 0x8>; + reg = <0xf0003000 0x1000>; + status = "disabled"; + }; + }; -- cgit v1.2.3