From 57e7b08263d046ce0bbdf36adb20a268a80bf60a Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 3 Dec 2015 16:20:10 +0800 Subject: irqchip/sunxi-nmi: Rename binding doc filename to allwinner,sunxi-nmi.txt The NMI controller is found in all Allwinner multi-core SoCs. It is not limited to sun[67]i, nor is it always found in the "system controller" block. On sun[68]i, it is in the RTC block, while on sun9i, it is in the PRCM block. Drop these 2 specific bits from the binding doc filename. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Reviewed-by: Hans de Goede Link: https://lkml.kernel.org/r/1449130813-22400-2-git-send-email-wens@csie.org Signed-off-by: Jason Cooper --- .../allwinner,sun67i-sc-nmi.txt | 27 ---------------------- .../interrupt-controller/allwinner,sunxi-nmi.txt | 27 ++++++++++++++++++++++ 2 files changed, 27 insertions(+), 27 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt deleted file mode 100644 index d1c5cdabc3e0..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt +++ /dev/null @@ -1,27 +0,0 @@ -Allwinner Sunxi NMI Controller -============================== - -Required properties: - -- compatible : should be "allwinner,sun7i-a20-sc-nmi" or - "allwinner,sun6i-a31-sc-nmi" -- reg : Specifies base physical address and size of the registers. -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 2. The first cell is the IRQ number, the - second cell the trigger type as defined in interrupt.txt in this directory. -- interrupt-parent: Specifies the parent interrupt controller. -- interrupts: Specifies the interrupt line (NMI) which is handled by - the interrupt controller in the parent controller's notation. This value - shall be the NMI. - -Example: - -sc-nmi-intc@01c00030 { - compatible = "allwinner,sun7i-a20-sc-nmi"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x01c00030 0x0c>; - interrupt-parent = <&gic>; - interrupts = <0 0 4>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt new file mode 100644 index 000000000000..d1c5cdabc3e0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt @@ -0,0 +1,27 @@ +Allwinner Sunxi NMI Controller +============================== + +Required properties: + +- compatible : should be "allwinner,sun7i-a20-sc-nmi" or + "allwinner,sun6i-a31-sc-nmi" +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 2. The first cell is the IRQ number, the + second cell the trigger type as defined in interrupt.txt in this directory. +- interrupt-parent: Specifies the parent interrupt controller. +- interrupts: Specifies the interrupt line (NMI) which is handled by + the interrupt controller in the parent controller's notation. This value + shall be the NMI. + +Example: + +sc-nmi-intc@01c00030 { + compatible = "allwinner,sun7i-a20-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c00030 0x0c>; + interrupt-parent = <&gic>; + interrupts = <0 0 4>; +}; -- cgit v1.2.3 From cc66ef3c3923f8d2287c11e0a76ee2b68dc3e64a Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 3 Dec 2015 16:20:11 +0800 Subject: irqchip/sunxi-nmi: Add sun9i-a80 variant to binding doc sun9i A80 introduces a new variant of the NMI controller. The registers are reordered, but the functionality remains the same. Add a new compatible string for it. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Reviewed-by: Hans de Goede Link: https://lkml.kernel.org/r/1449130813-22400-3-git-send-email-wens@csie.org Signed-off-by: Jason Cooper --- .../devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt index d1c5cdabc3e0..81cd3692405e 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt @@ -4,7 +4,7 @@ Allwinner Sunxi NMI Controller Required properties: - compatible : should be "allwinner,sun7i-a20-sc-nmi" or - "allwinner,sun6i-a31-sc-nmi" + "allwinner,sun6i-a31-sc-nmi" or "allwinner,sun9i-a80-nmi" - reg : Specifies base physical address and size of the registers. - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Specifies the number of cells needed to encode an -- cgit v1.2.3 From 126aebd0557815f0d982c81a3ed9cd251f443de6 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 24 Oct 2015 00:15:51 +0200 Subject: irqchip/gic: Fix ARM11MPCore GIC bindings The GIC bindings for the ARM11MPCore need to differentiate between the GIC on the Test Chip and the one on the evaluation baseboard. Split the binding in two and define new compatible-strings. Cc: Thomas Gleixner Cc: Jason Cooper Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij Signed-off-by: Marc Zyngier --- Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt index cc56021eb60b..5a1cb4bc3dfe 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt @@ -18,6 +18,7 @@ Main node required properties: "arm,cortex-a9-gic" "arm,gic-400" "arm,pl390" + "arm,tc11mp-gic" "brcm,brahma-b15-gic" "qcom,msm-8660-qgic" "qcom,msm-qgic2" -- cgit v1.2.3 From 752b1b94e6c56af3621a4cad20bdc3032ae60950 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 17 Dec 2015 19:56:34 +0800 Subject: dt-bindings: Documents the mbigen bindings Add the mbigen msi interrupt controller bindings document. This patch based on Mark Rutland's patch https://lkml.org/lkml/2015/7/23/558 Signed-off-by: Ma Jun Acked-by: Mark Rutland Signed-off-by: Marc Zyngier --- .../interrupt-controller/hisilicon,mbigen-v2.txt | 74 ++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt new file mode 100644 index 000000000000..720f7c92e9a1 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt @@ -0,0 +1,74 @@ +Hisilicon mbigen device tree bindings. +======================================= + +Mbigen means: message based interrupt generator. + +MBI is kind of msi interrupt only used on Non-PCI devices. + +To reduce the wired interrupt number connected to GIC, +Hisilicon designed mbigen to collect and generate interrupt. + + +Non-pci devices can connect to mbigen and generate the +interrupt by writing ITS register. + +The mbigen chip and devices connect to mbigen have the following properties: + +Mbigen main node required properties: +------------------------------------------- +- compatible: Should be "hisilicon,mbigen-v2" + +- reg: Specifies the base physical address and size of the Mbigen + registers. + +- interrupt controller: Identifies the node as an interrupt controller + +- msi-parent: Specifies the MSI controller this mbigen use. + For more detail information,please refer to the generic msi-parent binding in + Documentation/devicetree/bindings/interrupt-controller/msi.txt. + +- num-pins: the total number of pins implemented in this Mbigen + instance. + +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value must be 2. + + The 1st cell is hardware pin number of the interrupt.This number is local to + each mbigen chip and in the range from 0 to the maximum interrupts number + of the mbigen. + + The 2nd cell is the interrupt trigger type. + The value of this cell should be: + 1: rising edge triggered + or + 4: high level triggered + +Examples: + + mbigen_device_gmac:intc { + compatible = "hisilicon,mbigen-v2"; + reg = <0x0 0xc0080000 0x0 0x10000>; + interrupt-controller; + msi-parent = <&its_dsa 0x40b1c>; + num-pins = <9>; + #interrupt-cells = <2>; + }; + +Devices connect to mbigen required properties: +---------------------------------------------------- +-interrupt-parent: Specifies the mbigen device node which device connected. + +-interrupts:Specifies the interrupt source. + For the specific information of each cell in this property,please refer to + the "interrupt-cells" description mentioned above. + +Examples: + gmac0: ethernet@c2080000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0xc2080000 0 0x20000>, + <0 0xc0000000 0 0x1000>; + interrupt-parent = <&mbigen_device_gmac>; + interrupts = <656 1>, + <657 1>; + }; -- cgit v1.2.3 From 0f6d785c847eeff55ae19546f5885156394be569 Mon Sep 17 00:00:00 2001 From: Damien Riegel Date: Mon, 21 Dec 2015 15:11:22 -0500 Subject: irqchip/ts4800: Add documentation for TS-4800 interrupt controller This is an interrupt-controller implemented in an FPGA, to multiplex interrupts generated from other IPs. The FPGA usually uses a GPIO as a parent interrupt controller to notify that one of the multiplexed interrupts has triggered. Signed-off-by: Damien Riegel Acked-by: Rob Herring Cc: Jason Cooper Cc: Marc Zyngier Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: kernel@savoirfairelinux.com Link: http://lkml.kernel.org/r/1450728683-31416-1-git-send-email-damien.riegel@savoirfairelinux.com Signed-off-by: Thomas Gleixner --- .../bindings/interrupt-controller/technologic,ts4800.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800.txt b/Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800.txt new file mode 100644 index 000000000000..7f15f1b0325b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800.txt @@ -0,0 +1,16 @@ +TS-4800 FPGA interrupt controller + +TS-4800 FPGA has an internal interrupt controller. When one of the +interrupts is triggered, the SoC is notified, usually using a GPIO as +parent interrupt source. + +Required properties: +- compatible: should be "technologic,ts4800-irqc" +- interrupt-controller: identifies the node as an interrupt controller +- reg: physical base address of the controller and length of memory mapped + region +- #interrupt-cells: specifies the number of cells needed to encode an interrupt + source, should be 1. +- interrupt-parent: phandle to the parent interrupt controller this one is + cascaded from +- interrupts: specifies the interrupt line in the interrupt-parent controller -- cgit v1.2.3