From 876611c493b10cbb59e0e2143d3e744d0442de63 Mon Sep 17 00:00:00 2001 From: Xu Yilun Date: Tue, 15 Sep 2020 11:44:21 +0800 Subject: mfd: intel-m10-bmc: Add Intel MAX 10 BMC chip support for Intel FPGA PAC This patch implements the basic functions of the BMC chip for some Intel FPGA PCIe Acceleration Cards (PAC). The BMC is implemented using the Intel MAX 10 CPLD. This BMC chip is connected to the FPGA by a SPI bus. To provide direct register access from the FPGA, the "SPI slave to Avalon Master Bridge" (spi-avmm) IP is integrated in the chip. It converts encoded streams of bytes from the host to the internal register read/write on the Avalon bus. So This driver uses the regmap-spi-avmm for register accessing. Signed-off-by: Xu Yilun Signed-off-by: Wu Hao Signed-off-by: Matthew Gerlach Signed-off-by: Russ Weight Reviewed-by: Tom Rix Signed-off-by: Lee Jones --- Documentation/ABI/testing/sysfs-driver-intel-m10-bmc | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-m10-bmc (limited to 'Documentation/ABI/testing') diff --git a/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc b/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc new file mode 100644 index 000000000000..979a2d62513f --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc @@ -0,0 +1,15 @@ +What: /sys/bus/spi/devices/.../bmc_version +Date: June 2020 +KernelVersion: 5.10 +Contact: Xu Yilun +Description: Read only. Returns the hardware build version of Intel + MAX10 BMC chip. + Format: "0x%x". + +What: /sys/bus/spi/devices/.../bmcfw_version +Date: June 2020 +KernelVersion: 5.10 +Contact: Xu Yilun +Description: Read only. Returns the firmware version of Intel MAX10 + BMC chip. + Format: "0x%x". -- cgit v1.2.3