From 960b2dee908b0fc51cf670841de13b40b44aaaae Mon Sep 17 00:00:00 2001 From: Helen Koike Date: Fri, 3 Apr 2020 18:15:34 +0200 Subject: media: dt-bindings: phy: phy-rockchip-dphy-rx0: move rockchip dphy rx0 bindings out of staging Move phy-rockchip-dphy-rx0 bindings to Documentation/devicetree/bindings/phy Verified with: make ARCH=arm64 dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml Signed-off-by: Helen Koike Acked-by: Rob Herring Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- .../bindings/phy/rockchip-mipi-dphy-rx0.yaml | 73 ++++++++++++++++++++++ .../bindings/phy/rockchip-mipi-dphy-rx0.yaml | 73 ---------------------- 2 files changed, 73 insertions(+), 73 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml delete mode 100644 drivers/staging/media/phy-rockchip-dphy-rx0/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml diff --git a/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml b/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml new file mode 100644 index 000000000000..7d888d358823 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings + +maintainers: + - Helen Koike + - Ezequiel Garcia + +description: | + The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to + the ISP1 (Image Signal Processing unit v1.0) for CSI cameras. + +properties: + compatible: + const: rockchip,rk3399-mipi-dphy-rx0 + + clocks: + items: + - description: MIPI D-PHY ref clock + - description: MIPI D-PHY RX0 cfg clock + - description: Video in/out general register file clock + + clock-names: + items: + - const: dphy-ref + - const: dphy-cfg + - const: grf + + '#phy-cells': + const: 0 + + power-domains: + description: Video in/out power domain. + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - '#phy-cells' + - power-domains + +additionalProperties: false + +examples: + - | + + /* + * MIPI D-PHY RX0 use registers in "general register files", it + * should be a child of the GRF. + * + * grf: syscon@ff770000 { + * compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; + * ... + * }; + */ + + #include + #include + + mipi_dphy_rx0: mipi-dphy-rx0 { + compatible = "rockchip,rk3399-mipi-dphy-rx0"; + clocks = <&cru SCLK_MIPIDPHY_REF>, + <&cru SCLK_DPHY_RX0_CFG>, + <&cru PCLK_VIO_GRF>; + clock-names = "dphy-ref", "dphy-cfg", "grf"; + power-domains = <&power RK3399_PD_VIO>; + #phy-cells = <0>; + }; diff --git a/drivers/staging/media/phy-rockchip-dphy-rx0/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml b/drivers/staging/media/phy-rockchip-dphy-rx0/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml deleted file mode 100644 index 7d888d358823..000000000000 --- a/drivers/staging/media/phy-rockchip-dphy-rx0/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml +++ /dev/null @@ -1,73 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0+ OR MIT) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings - -maintainers: - - Helen Koike - - Ezequiel Garcia - -description: | - The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to - the ISP1 (Image Signal Processing unit v1.0) for CSI cameras. - -properties: - compatible: - const: rockchip,rk3399-mipi-dphy-rx0 - - clocks: - items: - - description: MIPI D-PHY ref clock - - description: MIPI D-PHY RX0 cfg clock - - description: Video in/out general register file clock - - clock-names: - items: - - const: dphy-ref - - const: dphy-cfg - - const: grf - - '#phy-cells': - const: 0 - - power-domains: - description: Video in/out power domain. - maxItems: 1 - -required: - - compatible - - clocks - - clock-names - - '#phy-cells' - - power-domains - -additionalProperties: false - -examples: - - | - - /* - * MIPI D-PHY RX0 use registers in "general register files", it - * should be a child of the GRF. - * - * grf: syscon@ff770000 { - * compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; - * ... - * }; - */ - - #include - #include - - mipi_dphy_rx0: mipi-dphy-rx0 { - compatible = "rockchip,rk3399-mipi-dphy-rx0"; - clocks = <&cru SCLK_MIPIDPHY_REF>, - <&cru SCLK_DPHY_RX0_CFG>, - <&cru PCLK_VIO_GRF>; - clock-names = "dphy-ref", "dphy-cfg", "grf"; - power-domains = <&power RK3399_PD_VIO>; - #phy-cells = <0>; - }; -- cgit v1.2.3