From fff987e7328951f7d6fb2d0545de8635ceafa89f Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sun, 24 May 2020 18:06:35 +0200 Subject: ARM: dts: rockchip: rename label and nodename pinctrl subnodes that end with gpio A test with the command below gives for example this error: arch/arm/boot/dts/rk3288-tinker.dt.yaml: tsadc: otp-gpio: {'phandle': [[54]], 'rockchip,pins': [[0, 10, 0, 118]]} is not of type 'array' 'gpio' is a sort of reserved nodename and should not be used for pinctrl in combination with 'rockchip,pins', so change nodes that end with 'gpio' to end with 'pin' or 'pins'. make ARCH=arm dtbs_check DT_SCHEMA_FILES=~/.local/lib/python3.5/site-packages/ dtschema/schemas/gpio/gpio.yaml Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20200524160636.16547-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 6 +++--- arch/arm/boot/dts/rk3288-veyron-jaq.dts | 2 +- arch/arm/boot/dts/rk3288-veyron-jerry.dts | 2 +- arch/arm/boot/dts/rk3288-veyron-mighty.dts | 6 +++--- arch/arm/boot/dts/rk3288-veyron-minnie.dts | 2 +- arch/arm/boot/dts/rk3288-veyron-pinky.dts | 6 +++--- arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi | 2 +- arch/arm/boot/dts/rk3288-veyron-speedy.dts | 2 +- arch/arm/boot/dts/rk3288.dtsi | 6 +++--- arch/arm/boot/dts/rv1108.dtsi | 12 ++++++------ 10 files changed, 23 insertions(+), 23 deletions(-) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index b0fd92befdeb..3236abb0aba9 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -520,9 +520,9 @@ resets = <&cru SRST_TSADC>; reset-names = "tsadc-apb"; pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; + pinctrl-0 = <&otp_pin>; pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; + pinctrl-2 = <&otp_pin>; #thermal-sensor-cells = <0>; rockchip,hw-tshut-temp = <95000>; status = "disabled"; @@ -1111,7 +1111,7 @@ }; tsadc { - otp_gpio: otp-gpio { + otp_pin: otp-pin { rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts index 171ba6185b6d..8efba9deae3c 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts @@ -47,7 +47,7 @@ &sdmmc { disable-wp; pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin &sdmmc_bus4>; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts index 66f00d28801a..2c916c50dda5 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts @@ -192,7 +192,7 @@ &sdmmc { disable-wp; pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin &sdmmc_bus4>; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-mighty.dts b/arch/arm/boot/dts/rk3288-veyron-mighty.dts index 27fbc07476d2..fa695a88f236 100644 --- a/arch/arm/boot/dts/rk3288-veyron-mighty.dts +++ b/arch/arm/boot/dts/rk3288-veyron-mighty.dts @@ -18,8 +18,8 @@ }; &sdmmc { - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_wp_gpio &sdmmc_bus4>; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin + &sdmmc_wp_pin &sdmmc_bus4>; wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>; /delete-property/ disable-wp; @@ -27,7 +27,7 @@ &pinctrl { sdmmc { - sdmmc_wp_gpio: sdmmc-wp-gpio { + sdmmc_wp_pin: sdmmc-wp-pin { rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts index 383fad1a88a1..f8b69e0a16a0 100644 --- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts @@ -114,7 +114,7 @@ &sdmmc { disable-wp; pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin &sdmmc_bus4>; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts index 71e6629cc208..4e9fdb0f722d 100644 --- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts +++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts @@ -105,7 +105,7 @@ }; sdmmc { - sdmmc_wp_gpio: sdmmc-wp-gpio { + sdmmc_wp_pin: sdmmc-wp-pin { rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; }; }; @@ -126,8 +126,8 @@ &sdmmc { pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_wp_gpio &sdmmc_bus4>; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin + &sdmmc_wp_pin &sdmmc_bus4>; wp-gpios = <&gpio7 RK_PB2 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi index fe950f9863e8..27fb06ce907e 100644 --- a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi @@ -41,7 +41,7 @@ }; /* This is where we actually hook up CD */ - sdmmc_cd_gpio: sdmmc-cd-gpio { + sdmmc_cd_pin: sdmmc-cd-pin { rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts index e354c61a45e7..4a3ea934d03e 100644 --- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts +++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts @@ -54,7 +54,7 @@ &sdmmc { disable-wp; pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin &sdmmc_bus4>; }; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 2e1edd85f04a..84d59469035e 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -574,9 +574,9 @@ resets = <&cru SRST_TSADC>; reset-names = "tsadc-apb"; pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; + pinctrl-0 = <&otp_pin>; pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; + pinctrl-2 = <&otp_pin>; #thermal-sensor-cells = <1>; rockchip,grf = <&grf>; rockchip,hw-tshut-temp = <95000>; @@ -1929,7 +1929,7 @@ }; tsadc { - otp_gpio: otp-gpio { + otp_pin: otp-pin { rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; }; diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index f9cfe2c80791..a5d130bd0547 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -351,9 +351,9 @@ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; clock-names = "tsadc", "apb_pclk"; pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; + pinctrl-0 = <&otp_pin>; pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; + pinctrl-2 = <&otp_pin>; resets = <&cru SRST_TSADC>; reset-names = "tsadc-apb"; rockchip,hw-tshut-temp = <120000>; @@ -728,7 +728,7 @@ <0 RK_PC6 3 &pcfg_pull_none>; }; - i2c2m1_gpio: i2c2m1-gpio { + i2c2m1_pins: i2c2m1-pins { rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; }; @@ -740,7 +740,7 @@ <1 RK_PD4 2 &pcfg_pull_none>; }; - i2c2m05v_gpio: i2c2m05v-gpio { + i2c2m05v_pins: i2c2m05v-pins { rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; }; @@ -867,7 +867,7 @@ rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; }; - otp_gpio: otp-gpio { + otp_pin: otp-pin { rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -886,7 +886,7 @@ rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; }; - uart0_rts_gpio: uart0-rts-gpio { + uart0_rts_pin: uart0-rts-pin { rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; -- cgit v1.2.3 From 6c2b99a2e7a073575b4ee91abf7d16470991c1f4 Mon Sep 17 00:00:00 2001 From: Abhishek Pandit-Subedi Date: Fri, 12 Jun 2020 13:02:48 -0700 Subject: ARM: dts: rockchip: Add marvell BT irq config Veyron Jaq and Mighty both use the Marvel 8897 WiFi+BT chip. Add wakeup and pinctrl block to devicetree so the btmrvl driver can correctly configure the wakeup interrupt. Signed-off-by: Abhishek Pandit-Subedi Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20200612130219.v2.1.I66864be898aa835ccb66b6cd5220d0b082338a81@changeid Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron-jaq.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts index 8efba9deae3c..af77ab20586d 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts @@ -44,6 +44,21 @@ }; }; +&sdio0 { + #address-cells = <1>; + #size-cells = <0>; + + btmrvl: btmrvl@2 { + compatible = "marvell,sd8897-bt"; + reg = <2>; + interrupt-parent = <&gpio4>; + interrupts = ; + marvell,wakeup-pin = /bits/ 16 <13>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l>; + }; +}; + &sdmmc { disable-wp; pinctrl-names = "default"; -- cgit v1.2.3 From fb082df317823463eaf09ac88de19fb3319e4f58 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Mon, 29 Jun 2020 22:10:57 +0800 Subject: ARM: dts: rockchip: Add 'arm,pl330-periph-burst' for dmac This patch Add the quirk to specify to use burst transfer for better compatible and higher performance. Signed-off-by: Sugar Zhang Link: https://lore.kernel.org/r/1593439866-68459-1-git-send-email-sugar.zhang@rock-chips.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036.dtsi | 1 + arch/arm/boot/dts/rk322x.dtsi | 1 + arch/arm/boot/dts/rk3288.dtsi | 3 +++ arch/arm/boot/dts/rk3xxx.dtsi | 3 +++ arch/arm/boot/dts/rv1108.dtsi | 1 + 5 files changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index d9a0c9a29b68..093567022386 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -67,6 +67,7 @@ ; #dma-cells = <1>; arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; clocks = <&cru ACLK_DMAC2>; clock-names = "apb_pclk"; }; diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 3236abb0aba9..48e6e8d44a1a 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -107,6 +107,7 @@ interrupts = , ; #dma-cells = <1>; + arm,pl330-periph-burst; clocks = <&cru ACLK_DMAC>; clock-names = "apb_pclk"; }; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 84d59469035e..9fa11b9f4522 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -167,6 +167,7 @@ ; #dma-cells = <1>; arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; clocks = <&cru ACLK_DMAC2>; clock-names = "apb_pclk"; }; @@ -178,6 +179,7 @@ ; #dma-cells = <1>; arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; clocks = <&cru ACLK_DMAC1>; clock-names = "apb_pclk"; status = "disabled"; @@ -190,6 +192,7 @@ ; #dma-cells = <1>; arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; clocks = <&cru ACLK_DMAC1>; clock-names = "apb_pclk"; }; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index d929b60517ab..859a7477909f 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -45,6 +45,7 @@ ; #dma-cells = <1>; arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; clocks = <&cru ACLK_DMA1>; clock-names = "apb_pclk"; }; @@ -56,6 +57,7 @@ ; #dma-cells = <1>; arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; clocks = <&cru ACLK_DMA1>; clock-names = "apb_pclk"; status = "disabled"; @@ -68,6 +70,7 @@ ; #dma-cells = <1>; arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; clocks = <&cru ACLK_DMA2>; clock-names = "apb_pclk"; }; diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index a5d130bd0547..a1a08cb9364e 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -97,6 +97,7 @@ interrupts = ; #dma-cells = <1>; arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; clocks = <&cru ACLK_DMAC>; clock-names = "apb_pclk"; }; -- cgit v1.2.3 From c2f343510d99ab53b46bdfeb184cb48f622e6943 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 15 Jul 2020 14:04:12 +0530 Subject: ARM: dts: rockchip: dalang-carrier: Move i2c nodes into SOM I2C nodes and associated slave devices defined in Carrier board are specific to rk3399pro vmrac SOM. So, move them into SOM dtsi. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20200715083418.112003-2-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip-radxa-dalang-carrier.dtsi | 32 ---------------------- .../boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 29 ++++++++++++++++++++ 2 files changed, 29 insertions(+), 32 deletions(-) diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi index df3712aedf8a..176b53b8e41a 100644 --- a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi +++ b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi @@ -17,29 +17,6 @@ status = "okay"; }; -&i2c1 { - status = "okay"; - i2c-scl-rising-time-ns = <140>; - i2c-scl-falling-time-ns = <30>; -}; - -&i2c2 { - status = "okay"; - clock-frequency = <400000>; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio4>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - }; -}; - &pwm0 { status = "okay"; }; @@ -70,12 +47,3 @@ &uart2 { status = "okay"; }; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = - <4 RK_PD6 0 &pcfg_pull_up>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi index 0a516334f15f..e11538171e67 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi @@ -297,6 +297,29 @@ }; }; +&i2c1 { + i2c-scl-falling-time-ns = <30>; + i2c-scl-rising-time-ns = <140>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio4>; + interrupts = ; + }; +}; + &io_domains { status = "okay"; bt656-supply = <&vcca_1v8>; @@ -324,6 +347,12 @@ }; &pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <4 RK_PD6 0 &pcfg_pull_up>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = -- cgit v1.2.3 From 3047b384a74090f09b994298eb5c40986275233a Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 15 Jul 2020 14:04:13 +0530 Subject: arm64: dts: rk3399pro: vmarc-som: Fix sorting nodes, properties Fix node, properties sorting on RockPI N10 board dts(i) files. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20200715083418.112003-3-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399pro-rock-pi-n10.dts | 2 +- .../boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 35 +++++++++++----------- 2 files changed, 18 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts b/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts index a1783e7f769a..539f4005386d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts @@ -8,8 +8,8 @@ /dts-v1/; #include "rk3399.dtsi" #include "rk3399-opp.dtsi" -#include "rk3399pro-vmarc-som.dtsi" #include +#include "rk3399pro-vmarc-som.dtsi" / { model = "Radxa ROCK Pi N10"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi index e11538171e67..121a430d6a70 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi @@ -76,8 +76,8 @@ &i2c0 { clock-frequency = <400000>; - i2c-scl-rising-time-ns = <180>; i2c-scl-falling-time-ns = <30>; + i2c-scl-rising-time-ns = <180>; status = "okay"; rk809: pmic@20 { @@ -323,8 +323,22 @@ &io_domains { status = "okay"; bt656-supply = <&vcca_1v8>; - sdmmc-supply = <&vccio_sd>; gpio1830-supply = <&vccio_3v0>; + sdmmc-supply = <&vccio_sd>; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <4 RK_PD6 0 &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC2 0 &pcfg_pull_up>; + }; + }; }; &pmu_io_domains { @@ -341,22 +355,7 @@ }; &tsadc { - status = "okay"; rockchip,hw-tshut-mode = <1>; rockchip,hw-tshut-polarity = <1>; -}; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <4 RK_PD6 0 &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = - <1 RK_PC2 0 &pcfg_pull_up>; - }; - }; + status = "okay"; }; -- cgit v1.2.3 From 4a3ca113c0f3a2ce33e51fc6a48a121b2d707d4f Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 15 Jul 2020 14:04:14 +0530 Subject: arm64: dts: rk3399pro: vmarc-som: Move supply regulators into Carrier Supply regulators are common across different variants of vmarc SOM's since the Type C power controller IC is part of the carrier board. So, move the supply regulators into carrier board dtsi. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20200715083418.112003-4-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi | 19 +++++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 19 ------------------- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi index 176b53b8e41a..00b200a62263 100644 --- a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi +++ b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi @@ -11,6 +11,25 @@ chosen { stdout-path = "serial2:1500000n8"; }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; }; &gmac { diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi index 121a430d6a70..d8fa8127d9dc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi @@ -18,25 +18,6 @@ clock-output-names = "clkin_gmac"; #clock-cells = <0>; }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; }; &cpu_l0 { -- cgit v1.2.3 From a66bd94d0eac017e4846658750acaca2937555bb Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 15 Jul 2020 14:04:15 +0530 Subject: arm64: dts: rk3399pro: vmarc-som: Move common properties into Carrier Some of gmac, sdmmc node properties are common across rk3288 and rk3399pro SOM's so move them into Carrier dtsi. Chosen node is specific to rk3399pro configure SBC, so move it into RockPI N10 dts. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20200715083418.112003-5-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- .../arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi | 18 ++++++++++++++---- .../boot/dts/rockchip/rk3399pro-rock-pi-n10.dts | 4 ++++ .../boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 21 +++++---------------- 3 files changed, 23 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi index 00b200a62263..450e5bb5af0b 100644 --- a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi +++ b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi @@ -8,8 +8,11 @@ #include / { - chosen { - stdout-path = "serial2:1500000n8"; + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; }; vcc12v_dcin: vcc12v-dcin-regulator { @@ -33,6 +36,15 @@ }; &gmac { + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; status = "okay"; }; @@ -48,10 +60,8 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; disable-wp; vqmmc-supply = <&vccio_sd>; - max-frequency = <150000000>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts b/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts index 539f4005386d..369de5dc0ebd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts @@ -15,4 +15,8 @@ model = "Radxa ROCK Pi N10"; compatible = "radxa,rockpi-n10", "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi index d8fa8127d9dc..37ed95d5f7e9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi @@ -11,13 +11,6 @@ / { compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro"; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; }; &cpu_l0 { @@ -42,17 +35,8 @@ &gmac { assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; }; &i2c0 { @@ -335,6 +319,11 @@ status = "okay"; }; +&sdmmc { + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + max-frequency = <150000000>; +}; + &tsadc { rockchip,hw-tshut-mode = <1>; rockchip,hw-tshut-polarity = <1>; -- cgit v1.2.3 From 09ee4794270f0010c6397163f033f883f5bff1aa Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 15 Jul 2020 14:04:16 +0530 Subject: dt-bindings: arm: rockchip: Add Rock Pi N8 binding Rock Pi N8 is a Rockchip RK3288 based SBC, which has - VMARC RK3288 SOM (as per SMARC standard) from Vamrs. - Compatible carrier board from Radxa. VMARC RK3288 SOM need to mount on top of dalang carrier board for making Rock PI N8 SBC. Add dt-bindings for it. Signed-off-by: Jagan Teki Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20200715083418.112003-6-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index d4a4045092df..db2e35796795 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -435,6 +435,12 @@ properties: - const: radxa,rockpi4 - const: rockchip,rk3399 + - description: Radxa ROCK Pi N8 + items: + - const: radxa,rockpi-n8 + - const: vamrs,rk3288-vmarc-som + - const: rockchip,rk3288 + - description: Radxa ROCK Pi N10 items: - const: radxa,rockpi-n10 -- cgit v1.2.3 From b8c564d4fa76b1314a10585eea8e97b8c621a77a Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 15 Jul 2020 14:04:17 +0530 Subject: ARM: dts: rockchip: Add VMARC RK3288 SOM initial support VMARC RK3288 SOM is a standard SMARC SOM design with Rockchip RK3288 SoC, which is designed by Vamrs. Specification: - Rockchip RK3288 - PMIC: RK808 - eMMC: 16GB/32GB/64GB - SD slot - 2xUSB-2.0, 1xUSB3.0 - USB-C for power supply - Ethernet - HDMI, MIPI-DSI/CSI, eDP Add initial support for VMARC RK3288 SOM, this would use with associated carrier board. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20200715083418.112003-7-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-vmarc-som.dtsi | 270 ++++++++++++++++++++++++++++++++ 1 file changed, 270 insertions(+) create mode 100644 arch/arm/boot/dts/rk3288-vmarc-som.dtsi diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi new file mode 100644 index 000000000000..cd61b6230f0d --- /dev/null +++ b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Vamrs Limited + * Copyright (c) 2019 Amarula Solutions(India) + */ + +#include +#include + +/ { + compatible = "vamrs,rk3288-vmarc-som", "rockchip,rk3288"; + + vccio_flash: vccio-flash-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_flash"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vccio_flash>; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + phy-supply = <&vcc_io>; + snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &global_pwroff>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_io>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc_io>; + vddio-supply = <&vcc_io>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1400000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-ramp-delay = <6000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_tp: LDO_REG1 { + regulator-name = "vcc_tp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_codec: LDO_REG2 { + regulator-name = "vcca_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_wl: LDO_REG4 { + regulator-name = "vcc_wl"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-name = "vdd10_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_18: LDO_REG7 { + regulator-name = "vcc_18"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_lcd: LDO_REG8 { + regulator-name = "vcc18_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_sd: SWITCH_REG1 { + regulator-name = "vcc_sd"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_lcd: SWITCH_REG2 { + regulator-name = "vcc_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&io_domains { + bb-supply = <&vcc_io>; + flash0-supply = <&vccio_flash>; + gpio1830-supply = <&vcc_18>; + gpio30-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + status = "okay"; +}; + +&pinctrl { + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + drive-strength = <8>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; + }; + }; +}; -- cgit v1.2.3 From afd9eb88041409e0f311730f23e8fe6921e74cb8 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 15 Jul 2020 14:04:18 +0530 Subject: ARM: dts: rockchip: Add Radxa Rock Pi N8 initial support Rock Pi N8 is a Rockchip RK3288 based SBC, which has - VMARC RK3288 SOM (as per SMARC standard) from Vamrs. - Compatible carrier board from Radxa. VAMRC RK3288 SOM need to mount on top of radxa dalang carrier board for making Rock Pi N8 SBC. So, add initial support for Rock Pi N8 by including rk3288, rk3288 vamrc-som and raxda dalang carrier board dtsi files. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20200715083418.112003-8-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rk3288-rock-pi-n8.dts | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 arch/arm/boot/dts/rk3288-rock-pi-n8.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e6a1cac0bfc7..318664fea748 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -974,6 +974,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-popmetal.dtb \ rk3288-r89.dtb \ rk3288-rock2-square.dtb \ + rk3288-rock-pi-n8.dtb \ rk3288-tinker.dtb \ rk3288-tinker-s.dtb \ rk3288-veyron-brain.dtb \ diff --git a/arch/arm/boot/dts/rk3288-rock-pi-n8.dts b/arch/arm/boot/dts/rk3288-rock-pi-n8.dts new file mode 100644 index 000000000000..b19593021713 --- /dev/null +++ b/arch/arm/boot/dts/rk3288-rock-pi-n8.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Vamrs Limited + * Copyright (c) 2019 Amarula Solutions(India) + */ + +/dts-v1/; +#include "rk3288.dtsi" +#include +#include "rk3288-vmarc-som.dtsi" + +/ { + model = "Radxa ROCK Pi N8"; + compatible = "radxa,rockpi-n8", "vamrs,rk3288-vmarc-som", + "rockchip,rk3288"; +}; -- cgit v1.2.3 From 719646b76a41b8a482f8701825b635e9710ab329 Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Tue, 7 Jul 2020 12:12:14 +0200 Subject: ARM: dts: rockchip: Fix VBUS on rk3288-vyasa Connect the voltage regulator of vbus to the otg connector. Depending on the current mode this is enabled (in "host" mode") or disabled (in "peripheral" mode). The regulator must be updated if the controller is configured in "otg" mode and the status changes between "host" and "peripheral". Signed-off-by: Michael Trimarchi Link: https://lore.kernel.org/r/20200707101214.2301768-1-michael@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-vyasa.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts index 385dd59393e1..1a20854a1317 100644 --- a/arch/arm/boot/dts/rk3288-vyasa.dts +++ b/arch/arm/boot/dts/rk3288-vyasa.dts @@ -99,8 +99,6 @@ pinctrl-0 = <&otg_vbus_drv>; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; vin-supply = <&vsus_5v>; }; @@ -416,6 +414,7 @@ }; &usb_otg { + vbus-supply = <&vusb1_5v>; status = "okay"; }; -- cgit v1.2.3 From 82540defdd9cfc491f564ffb8d01911966636bc7 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 20 Jul 2020 16:28:46 +0530 Subject: ARM: dts: rockchip: Add usb host0 ohci node for rk3288 rk3288 and rk3288w have a usb host0 ohci controller. Although rk3288 ohci doesn't actually work on hardware, but rk3288w ohci can work well. So add usb host0 ohci node in rk3288 dtsi and boards can then enable it if supported. Signed-off-by: Jagan Teki Cc: William Wu Link: https://lore.kernel.org/r/20200720105846.367776-1-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 9fa11b9f4522..68d5a58cfe88 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -616,7 +616,16 @@ status = "disabled"; }; - /* NOTE: ohci@ff520000 doesn't actually work on hardware */ + /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */ + usb_host0_ohci: usb@ff520000 { + compatible = "generic-ohci"; + reg = <0x0 0xff520000 0x0 0x100>; + interrupts = ; + clocks = <&cru HCLK_USBHOST0>; + phys = <&usbphy1>; + phy-names = "usb"; + status = "disabled"; + }; usb_host1: usb@ff540000 { compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", -- cgit v1.2.3 From 417b188a985d3557b0ecb5623b27bd9843f03aec Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 20 Jul 2020 16:32:28 +0530 Subject: ARM: dts: rockchip: Add USB for RockPI N8/N10 Radxa dalang carrier board has 2x USB 2.0 and 1x USB 3.0 ports. This patch adds support to enable all these USB ports for N10 and N8 combinations SBCs. Note that the USB 3.0 port on RockPI N8 combination works as USB 2.0 OTG since it is driven from RK3288. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20200720110230.367985-1-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-vmarc-som.dtsi | 42 ++++++++++++ .../boot/dts/rockchip-radxa-dalang-carrier.dtsi | 18 +++++ .../boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 78 ++++++++++++++++++++++ 3 files changed, 138 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi index cd61b6230f0d..78164d117248 100644 --- a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi +++ b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi @@ -267,4 +267,46 @@ rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; }; }; + + vbus_host { + usb1_en_oc: usb1-en-oc { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + vbus_typec { + usb0_en_oc: usb0-en-oc { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&vbus_host { + enable-active-high; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; /* USB1_EN_OC# */ +}; + +&vbus_typec { + enable-active-high; + gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; /* USB0_EN_OC# */ }; diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi index 450e5bb5af0b..d2b6ead148a2 100644 --- a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi +++ b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi @@ -33,6 +33,24 @@ regulator-max-microvolt = <5000000>; vin-supply = <&vcc12v_dcin>; }; + + vbus_host: vbus-host { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_en_oc>; + regulator-name = "vbus_host"; /* HOST-5V */ + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vbus_typec: vbus-typec { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_en_oc>; + regulator-name = "vbus_typec"; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; }; &gmac { diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi index 37ed95d5f7e9..111d6cf9a4e6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi @@ -304,6 +304,18 @@ rockchip,pins = <1 RK_PC2 0 &pcfg_pull_up>; }; }; + + vbus_host { + usb1_en_oc: usb1-en-oc { + rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + vbus_typec { + usb0_en_oc: usb0-en-oc { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; }; &pmu_io_domains { @@ -324,8 +336,74 @@ max-frequency = <150000000>; }; +&tcphy0 { + status = "okay"; +}; + &tsadc { rockchip,hw-tshut-mode = <1>; rockchip,hw-tshut-polarity = <1>; status = "okay"; }; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + phy-supply = <&vbus_typec>; + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vbus_host>; + status = "okay"; + }; +}; + + +&u2phy1 { + status = "okay"; + + u2phy1_host: host-port { + phy-supply = <&vbus_host>; + status = "okay"; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; +}; + +&vbus_host { + enable-active-high; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; /* USB1_EN_OC# */ + pinctrl-names = "default"; + pinctrl-0 = <&usb1_en_oc>; +}; + +&vbus_typec { + enable-active-high; + gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; /* USB0_EN_OC# */ + pinctrl-names = "default"; + pinctrl-0 = <&usb0_en_oc>; +}; -- cgit v1.2.3 From d0cb2f30e7c033f0a8bbe98ec73dbc1db4788942 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 20 Jul 2020 16:32:29 +0530 Subject: ARM: dts: rockchip: Add HDMI out for RockPI N8/N10 This patch adds support to enable HDMI out for N10 and N8 combinations SBCs. Signed-off-by: Jagan Teki Signed-off-by: Suniel Mahesh Link: https://lore.kernel.org/r/20200720110230.367985-2-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-vmarc-som.dtsi | 10 ++++++++++ arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi | 20 ++++++++++++++++++++ .../arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 12 ++++++++++++ 3 files changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi index 78164d117248..4a373f5aa600 100644 --- a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi +++ b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi @@ -38,6 +38,12 @@ snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; }; +&hdmi { + ddc-i2c-bus = <&i2c5>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec_c0>; +}; + &i2c0 { clock-frequency = <400000>; status = "okay"; @@ -225,6 +231,10 @@ }; }; +&i2c5 { + status = "okay"; +}; + &io_domains { bb-supply = <&vcc_io>; flash0-supply = <&vccio_flash>; diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi index d2b6ead148a2..26b53eac4706 100644 --- a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi +++ b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi @@ -66,6 +66,10 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + &pwm0 { status = "okay"; }; @@ -94,3 +98,19 @@ &uart2 { status = "okay"; }; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi index 111d6cf9a4e6..ebccc4a153a2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi @@ -39,6 +39,12 @@ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; }; +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; +}; + &i2c0 { clock-frequency = <400000>; i2c-scl-falling-time-ns = <30>; @@ -285,6 +291,12 @@ }; }; +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + &io_domains { status = "okay"; bt656-supply = <&vcca_1v8>; -- cgit v1.2.3 From 93ca8ac2e8fcea6feb02a40edd2334144b62fc6e Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 20 Jul 2020 16:32:30 +0530 Subject: arm64: dts: rockchip: Add PCIe for RockPI N10 This patch adds support to enable PCIe for RockPI N10. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20200720110230.367985-3-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 40 ++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi index ebccc4a153a2..5d087be04af8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi @@ -11,6 +11,18 @@ / { compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro"; + + vcc3v3_pcie: vcc-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwr>; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; }; &cpu_l0 { @@ -142,7 +154,8 @@ regulator-min-microvolt = <900000>; regulator-max-microvolt = <900000>; regulator-state-mem { - regulator-off-in-suspend; + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; }; }; @@ -177,7 +190,8 @@ regulator-min-microvolt = <1850000>; regulator-max-microvolt = <1850000>; regulator-state-mem { - regulator-off-in-suspend; + regulator-on-in-suspend; + regulator-suspend-microvolt = <1850000>; }; }; @@ -304,6 +318,22 @@ sdmmc-supply = <&vccio_sd>; }; +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + max-link-speed = <2>; + num-lanes = <4>; + pinctrl-0 = <&pcie_clkreqnb_cpm>; + pinctrl-names = "default"; + vpcie0v9-supply = <&vcca_0v9>; /* VCC_0V9_S0 */ + vpcie1v8-supply = <&vcca_1v8>; /* VCC_1V8_S0 */ + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { @@ -311,6 +341,12 @@ }; }; + pcie { + pcie_pwr: pcie-pwr { + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <1 RK_PC2 0 &pcfg_pull_up>; -- cgit v1.2.3