From 090f4b6ad38eec0c24dcdc9d01cc22077c3b9d22 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 14 Aug 2013 18:53:56 -0400 Subject: drm/radeon: enable mgcg on SI Now that the CP is no longer reset and cg is properly disabled in when appropriate in the dpm code we can now enable mgcg (medium grained clockgating). Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_asic.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 52fe0d4eeaa0..3bd96cdb7601 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -2338,7 +2338,7 @@ int radeon_asic_init(struct radeon_device *rdev) switch (rdev->family) { case CHIP_TAHITI: rdev->cg_flags = - /*RADEON_CG_SUPPORT_GFX_MGCG |*/ + RADEON_CG_SUPPORT_GFX_MGCG | RADEON_CG_SUPPORT_GFX_MGLS | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ RADEON_CG_SUPPORT_GFX_CGLS | @@ -2355,7 +2355,7 @@ int radeon_asic_init(struct radeon_device *rdev) break; case CHIP_PITCAIRN: rdev->cg_flags = - /*RADEON_CG_SUPPORT_GFX_MGCG |*/ + RADEON_CG_SUPPORT_GFX_MGCG | RADEON_CG_SUPPORT_GFX_MGLS | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ RADEON_CG_SUPPORT_GFX_CGLS | @@ -2374,7 +2374,7 @@ int radeon_asic_init(struct radeon_device *rdev) break; case CHIP_VERDE: rdev->cg_flags = - /*RADEON_CG_SUPPORT_GFX_MGCG |*/ + RADEON_CG_SUPPORT_GFX_MGCG | RADEON_CG_SUPPORT_GFX_MGLS | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ RADEON_CG_SUPPORT_GFX_CGLS | @@ -2395,7 +2395,7 @@ int radeon_asic_init(struct radeon_device *rdev) break; case CHIP_OLAND: rdev->cg_flags = - /*RADEON_CG_SUPPORT_GFX_MGCG |*/ + RADEON_CG_SUPPORT_GFX_MGCG | RADEON_CG_SUPPORT_GFX_MGLS | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ RADEON_CG_SUPPORT_GFX_CGLS | @@ -2413,7 +2413,7 @@ int radeon_asic_init(struct radeon_device *rdev) break; case CHIP_HAINAN: rdev->cg_flags = - /*RADEON_CG_SUPPORT_GFX_MGCG |*/ + RADEON_CG_SUPPORT_GFX_MGCG | RADEON_CG_SUPPORT_GFX_MGLS | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ RADEON_CG_SUPPORT_GFX_CGLS | -- cgit v1.2.3