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Generate a stop condition after each message marked with I2C_M_STOP.
[JD: Add I2C_FUNC_PROTOCOL_MANGLING.]
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
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Adapter drivers might support only a subset of the SMBus operations
natively. Those drivers currently have to manually emulate unsupported
operations using I2C.
Make the i2c_smbus_xfer() function fall back to
i2c_smbus_xfer_emulated() when the adapter's .smbus_xfer() operation
returns -EOPNOTSUPP, like it already does when the .smbus_xfer()
operation isn't available at all.
[JD: Minor optimization.]
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
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SCCB is a serial communication bus developed by Omnivision. Its 2-wire
mode is very similar to SMBus byte data transactions, but requires the
controller to ignore the ACK bit and to insert a stop condition after
each message.
Add a device SCCB flag and a message stop flag to be passed to
controller drivers.
[JD: Kill rogue definition in go7007 driver.]
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
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Robofuzz OSIF is a generic USB/iIC interface that embeds an ATMega8A
AVR-RISC microcontroler.
The device is based upon Till Harbaum's i2c-tiny-usb and although it
enhances the original design with further functionnalities it still
maintain compatibility with it with respect to the USB/I2C interface.
Signed-off-by: Emmanuel Deloget <logout@free.fr>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
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Byte-by-byte transactions are used primarily for accessing I2C devices
with an SMBus controller. For these transactions, for each byte that is
read or written, the SMBus controller generates a BYTE_DONE IRQ. The isr
reads/writes the next byte, and clears the IRQ flag to start the next byte.
On the penultimate IRQ, the isr also sets the LAST_BYTE flag.
There is no locking around the cmd/len/count/data variables, since the
I2C adapter lock ensures there is never multiple simultaneous transactions
for the same device, and the driver thread never accesses these variables
while interrupts might be occurring.
The end result is faster I2C block read and write transactions.
Note: This patch has only been tested and verified by doing I2C read and
write block transfers on Cougar Point 6 Series PCH, as well as I2C read
block transfers on ICH5.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
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Enable interrupts on more devices. ICH5, ICH7(-M) and ICH10 have been
tested to work OK. ICH8 and ICH9 are expected to work just fine as
they are very close to ICH7 and ICH10.
Ultimately we want to enable this feature on at least every device
since the ICH5, but for now we limit the exposure. We'll enable it for
other devices if we don't get negative feedback.
As a bonus, let the user know when interrupts are used.
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Cc: Daniel Kurtz <djkurtz@chromium.org>
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Add a new 'feature' to i2c-i801 to enable using PCI interrupts.
When the feature is enabled, then an isr is installed for the device's
PCI IRQ.
An I2C/SMBus transaction is always terminated by one of the following
interrupt sources: FAILED, BUS_ERR, DEV_ERR, or on success: INTR.
When the isr fires for one of these cases, it sets the ->status variable
and wakes up the waitq. The waitq then saves off the status code, and
clears ->status (in preparation for some future transaction).
The SMBus controller generates an INTR irq at the end of each
transaction where INTREN was set in the HST_CNT register.
No locking is needed around accesses to priv->status since all writes to
it are serialized: it is only ever set once in the isr at the end of a
transaction, and cleared while no interrupts can occur. In addition, the
I2C adapter lock guarantees that entire I2C transactions for a single
adapter are always serialized.
For this patch, the INTREN bit is set only for SMBus block, byte and word
transactions, but not for I2C reads or writes. The use of the DS
(BYTE_DONE) interrupt with byte-by-byte I2C transactions is implemented in
a subsequent patch.
The interrupt feature has only been enabled for COUGARPOINT hardware.
In addition, it is disabled if SMBus is using the SMI# interrupt.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
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(Based on earlier work by Daniel Kurtz.)
Come up with a consistent, driver-wide strategy for event polling. For
intermediate steps of byte-by-byte block transactions, check for
BYTE_DONE or any error flag being set. At the end of every transaction
(regardless of PEC being used), check for both BUSY being cleared and
INTR or any error flag being set. This ensures proper action for all
transaction types.
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Cc: Daniel Kurtz <djkurtz@chromium.org>
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Later patches enable interrupts. This preliminary patch removes the older
unsupported ENABLE_INT9 flag.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
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Rename the SMBHSTCNT register bit access constants to match the style of
other register bits.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
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If an error is detected in the polling loop, abort the transaction and
return an error code.
* DEV_ERR is set if the device does not respond with an acknowledge, and
the SMBus controller times out (minimum 25ms).
* BUS_ERR is set if a bus arbitration collision is detected. In other
words, when the SMBus controller tries to generate a START condition, but
detects that the SMBDATA is being held low, usually by another SMBus/I2C
master.
* FAILED is only set if a transaction is stopped by software (using
the SMBHSTCNT KILL bit).
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
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Writing back the whole status register could clear unwanted bits.
In particular, it could clear the "INUSE_STS" bit, which is a
'hardware semaphore', that might be useful to use some day.
To prepare for this, let's ban writing back the whole status to register
HST_STS, of which this is the only instance.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
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As a slight optimization, pull some logic out of the polling loop during
byte-by-byte transactions by just setting the I801_LAST_BYTE bit, as
defined in the i801 (PCH) datasheet, when reading the last byte of a
byte-by-byte I2C_SMBUS_READ.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
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Using module_i2c_driver() makes the code smaller and cleaner.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
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Some AMD chipsets, such as the SP5100, have an auxiliary SMBus
controller with a second set of registers. This patch adds
support for this auxiliary controller.
Tested on ASUS KCMA-D8 motherboard.
Signed-off-by: Andrew Armenia <andrew@asquaredlabs.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
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Some chipsets have multiple sets of SMBus registers each controlling a
separate SMBus. Supporting these chipsets properly will require registering
multiple I2C adapters for one piix4.
The code to initialize and register the i2c_adapter structure has been
separated from piix4_probe and allows registration of a piix4 adapter
given its base address. Note that the i2c_adapter and i2c_piix4_adapdata
structures are now dynamically allocated.
Signed-off-by: Andrew Armenia <andrew@asquaredlabs.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
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Some chipsets have multiple sets of piix4-compatible SMBus registers.
Eliminating the global variable will allow these chipsets to be fully
supported.
Return value from piix4_setup and piix4_sb800_setup now returns the smba
value detected. This is stored in a struct i2c_piix4_adapdata. Thus
the global variable is eliminated.
Signed-off-by: Andrew Armenia <andrew@asquaredlabs.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
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Convert the drivers in drivers/i2c/busses/* to usemodule_pci_driver()
macro which makes the code smaller and a bit simpler.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Cc: Rudolf Marek <r.marek@assembler.cz>
Cc: Olof Johansson <olof@lixom.net>
Cc: "Mark M. Hoffman" <mhoffman@lightlink.com>
Cc: Tomoya MORINAGA <tomoya.rohm@gmail.com>
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My old e-mail address won't be valid for much longer. Time to update it.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
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Conflicts:
drivers/hid/Kconfig
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'suspend-fixes' and 'upstream' into for-linus
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Correct spelling typo in drivers/pci/hotplug.
Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
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Correct spelling typo in debug messages and comments
in drivers/iommu.
Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
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Correct spelling typo in debug messages and comments
within drivers/video.
Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
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Pull arch/tile updates from Chris Metcalf:
"These changes provide support for PCIe root complex and USB host mode
for tilegx's on-chip I/Os.
In addition, this pull provides the required underpinning for the
on-chip networking support that was pulled into 3.5. The changes have
all been through LKML (with several rounds for PCIe RC) and on
linux-next."
* git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile:
tile: updates to pci root complex from community feedback
bounce: allow use of bounce pool via config option
usb: add host support for the tilegx architecture
arch/tile: provide kernel support for the tilegx USB shim
tile pci: enable IOMMU to support DMA for legacy devices
arch/tile: enable ZONE_DMA for tilegx
tilegx pci: support I/O to arbitrarily-cached pages
tile: remove unused header
arch/tile: tilegx PCI root complex support
arch/tile: provide kernel support for the tilegx TRIO shim
arch/tile: break out the "csum a long" function to <asm/checksum.h>
arch/tile: provide kernel support for the tilegx mPIPE shim
arch/tile: common DMA code for the GXIO IORPC subsystem
arch/tile: support MMIO-based readb/writeb etc.
arch/tile: introduce GXIO IORPC framework for tilegx
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Pull SuperH updates from Paul Mundt:
- Migration off of old-style dynamic IRQ API.
- irqdomain and generic irq chip propagation.
- div4/6 clock consolidation, another step towards co-existing with the
common struct clk infrastructure.
- Extensive PFC rework
- Decoupling GPIO from pin state.
- Initial pinctrl support to facilitate incremental migration off of
legacy pinmux.
- gpiolib support made optional, and made pinctrl-backed.
* tag 'sh-for-linus' of git://github.com/pmundt/linux-sh: (38 commits)
sh: pfc: pin config get/set support.
sh: pfc: Prefer DRV_NAME over KBUILD_MODNAME.
sh: pfc: pinctrl legacy group support.
sh: pfc: Ignore pinmux GPIOs with invalid enum IDs.
sh: pfc: Export pinctrl binding init symbol.
sh: pfc: Error out on pinctrl init resolution failure.
sh: pfc: Make pr_fmt consistent across pfc drivers.
sh: pfc: pinctrl legacy function support.
sh: pfc: Rudimentary pinctrl-backed GPIO support.
sh: pfc: Dumb GPIO stringification.
sh: pfc: Shuffle PFC support core.
sh: pfc: Verify pin type encoding size at build time.
sh: pfc: Kill off unused pinmux bias flags.
sh: pfc: Make gpio chip support optional where possible.
sh: pfc: Split out gpio chip support.
sh64: Fix up section mismatch warnings.
sh64: Attempt to make reserved insn trap handler resemble C.
sh: Consolidate die definitions for trap handlers.
sh64: Kill off old exception debugging helpers.
sh64: Use generic unaligned access control/counters.
...
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git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
Pull powerpc updates from Benjamin Herrenschmidt:
"Notable highlights:
- iommu improvements from Anton removing the per-iommu global lock in
favor of dividing the DMA space into pools, each with its own lock,
and hashed on the CPU number. Along with making the locking more
fine grained, this gives significant improvements in multiqueue
networking scalability.
- Still from Anton, we know provide a vdso based variant of getcpu
which makes sched_getcpu with the appropriate glibc patch something
like 18 times faster.
- More anton goodness (he's been busy !) in other areas such as a
faster __clear_user and copy_page on P7, various perf fixes to
improve sampling quality, etc...
- One more step toward removing legacy i2c interfaces by using new
device-tree based probing of platform devices for the AOA audio
drivers
- A nice series of patches from Michael Neuling that helps avoiding
confusion between register numbers and litterals in assembly code,
trying to enforce the use of "%rN" register names in gas rather
than plain numbers.
- A pile of FSL updates
- The usual bunch of small fixes, cleanups etc...
You may spot a change to drivers/char/mem. The patch got no comment
or ack from outside, it's a trivial patch to allow the architecture to
skip creating /dev/port, which we use to disable it on ppc64 that
don't have a legacy brige. On those, IO ports 0...64K are not mapped
in kernel space at all, so accesses to /dev/port cause oopses (and
yes, distros -still- ship userspace that bangs hard coded ports such
as kbdrate)."
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (106 commits)
powerpc/mpic: Create a revmap with enough entries for IPIs and timers
Remove stale .rej file
powerpc/iommu: Fix iommu pool initialization
powerpc/eeh: Check handle_eeh_events() return value
powerpc/85xx: Add phy nodes in SGMII mode for MPC8536/44/72DS & P2020DS
powerpc/e500: add paravirt QEMU platform
powerpc/mpc85xx_ds: convert to unified PCI init
powerpc/fsl-pci: get PCI init out of board files
powerpc/85xx: Update corenet64_smp_defconfig
powerpc/85xx: Update corenet32_smp_defconfig
powerpc/85xx: Rename P1021RDB-PC device trees to be consistent
powerpc/watchdog: move booke watchdog param related code to setup-common.c
sound/aoa: Adapt to new i2c probing scheme
i2c/powermac: Improve detection of devices from device-tree
powerpc: Disable /dev/port interface on systems without an ISA bridge
of: Improve prom_update_property() function
powerpc: Add "memory" attribute for mfmsr()
powerpc/ftrace: Fix assembly trampoline register usage
powerpc/hw_breakpoints: Fix incorrect pointer access
powerpc: Put the gpr save/restore functions in their own section
...
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git://git.kernel.org/pub/scm/linux/kernel/git/jmorris/linux-security
Pull security subsystem updates from James Morris:
"Nothing groundbreaking for this kernel, just cleanups and fixes, and a
couple of Smack enhancements."
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris/linux-security: (21 commits)
Smack: Maintainer Record
Smack: don't show empty rules when /smack/load or /smack/load2 is read
Smack: user access check bounds
Smack: onlycap limits on CAP_MAC_ADMIN
Smack: fix smack_new_inode bogosities
ima: audit is compiled only when enabled
ima: ima_initialized is set only if successful
ima: add policy for pseudo fs
ima: remove unused cleanup functions
ima: free securityfs violations file
ima: use full pathnames in measurement list
security: Fix nommu build.
samples: seccomp: add .gitignore for untracked executables
tpm: check the chip reference before using it
TPM: fix memleak when register hardware fails
TPM: chip disabled state erronously being reported as error
MAINTAINERS: TPM maintainers' contacts update
Merge branches 'next-queue' and 'next' into next
Remove unused code from MPI library
Revert "crypto: GnuPG based MPI lib - additional sources (part 4)"
...
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This reverts commit 036dafa28da1e2565a8529de2ae663c37b7a0060.
First it appears in bisection, then reverting it solves the usual
netdev watchdog problem for different people. I don't have a proper
fix yet so get rid of it.
Bisected-and-reported-by: Alex Villacís Lasso <a_villacis@palosanto.com>
Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
Cc: Josh Boyer <jwboyer@redhat.com>
Cc: Hayes Wang <hayeswang@realtek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Pull arm-soc clk changes from Arnd Bergmann:
"Clock support is moving to the clk subsystem. These tegra, omap and
imx changes are for code that is still platform specific and not (yet)
part of that subsystem."
Fix up conflicts in arch/arm/mach-{imx/clk-imx51-imx53.c,omap2/Makefile}
* tag 'clk' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (23 commits)
ARM: imx: clk-imx31: Fix clock id for rnga driver
ARM: imx: add missing item to the list of clock event modes
ARM: i.MX5x CSPI: Fixed clock name for CSPI
ARM: i.MX5x clocks: Fix GPT clocks
ARM: i.MX5x clocks: Fix parent for PWM clocks
ARM: i.MX5x clocks: Add EPIT support
ARM: mx27: Reenable silicon version print
ARM: clk-imx27: Fix rtc clock id
ARM: tegra: Provide clock for only one PWM controller
ARM: tegra: Fix PWM clock programming
ARM: OMAP3+: clock33xx: Add AM33XX clock tree data
ARM: OMAP3+: clock: Move common clksel_rate & clock data to common file
ARM: tegra: dma: rename driver name for clock to "tegra-apbdma"
ARM: tegra: Remove second instance of uart clk
crypto: add clk_prepare/clk_unprepare
ASoC: tegra: add clk_prepare/clk_unprepare
staging: nvec: add clk_prepare/clk_unprepare
spi/tegra: add clk_prepare/clk_unprepare
Input: tegra-kbc - add clk_prepare/clk_unprepare
USB: ehci-tegra: add clk_prepare/clk_unprepare
...
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Pull arm-soc power management changes from Arnd Bergmann:
"These are various power management related changes, mainly concerning
cpuidle on i.MX and OMAP, as well as a the move of the omap
smartreflex driver to live in the power subsystem."
Fix up conflicts in arch/arm/mach-{imx/mach-imx6q.c,omap2/prm2xxx_3xxx.h}
* tag 'pm' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (37 commits)
ARM: OMAP2+: PM: fix IRQ_NOAUTOEN removal by mis-merge
ARM: OMAP2+: do not allow SmartReflex to be built as a module
ARM: OMAP2: Use hwmod to initialize mmc for 2420
ARM: OMAP3: PM: cpuidle: optimize the clkdm idle latency in C1 state
ARM: OMAP3: PM: cpuidle: optimize the PER latency in C1 state
ARM: OMAP3: PM: cpuidle: default to C1 in next_valid_state
ARM: OMAP3: PM: cleanup cam_pwrdm leftovers
ARM: OMAP3: PM: call pre/post transition per powerdomain
ARM: OMAP2+: powerdomain: allow pre/post transtion to be per pwrdm
ARM: OMAP3: PM: Remove IO Daisychain control from cpuidle
ARM: OMAP3PLUS: hwmod: reconfigure IO Daisychain during hwmod mux
ARM: OMAP3+: PRM: Enable IO wake up
ARM: OMAP4: PRM: Add IO Daisychain support
ARM: OMAP3: PM: Move IO Daisychain function to omap3 prm file
ARM: OMAP3: PM: correct enable/disable of daisy io chain
ARM: OMAP2+: PRM: fix compile for OMAP4-only build
W1: OMAP HDQ1W: use runtime PM
ARM: OMAP2+: HDQ1W: use omap_device
W1: OMAP HDQ1W: use 32-bit register accesses
W1: OMAP HDQ1W: allow driver to be built on all OMAP2+
...
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Pull arm-soc pincontrol drivers update from Arnd Bergmann:
"We are converting platforms to use the pinctrl framework over time,
rather than using platform specific code for the same effect. This
adds the respective driver for the prima2 platform."
* tag 'pinctrl' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: prima2: enable gpiolib unconditionally
PINCTRL: SiRF: add GPIO and GPIO irq support in CSR SiRFprimaII
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Pull arm-soc sparse IRQ conversion from Arnd Bergmann:
"The I.MX platform is getting converted to use sparse IRQs. We are
doing this for all platforms over time, because this is one of the
requirements for building a multiplatform kernel, and generally a good
idea."
* tag 'irq' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: imx: select USE_OF
ARM: imx: Fix build error due to missing irqs.h include
ARM: imx: enable SPARSE_IRQ for imx platform
ARM: fiq: change FIQ_START to a variable
tty: serial: imx: remove the use of MXC_INTERNAL_IRQS
ARM: imx: remove unneeded mach/irq.h inclusion
i2c: imx: remove unneeded mach/irqs.h inclusion
ARM: imx: add a legacy irqdomain for mx31ads
ARM: imx: add a legacy irqdomain for 3ds_debugboard
ARM: imx: pass gpio than irq number into mxc_expio_init
ARM: imx: leave irq_base of wm8350_platform_data uninitialized
dma: ipu: remove the use of ipu_platform_data
ARM: imx: move irq_domain_add_legacy call into avic driver
ARM: imx: move irq_domain_add_legacy call into tzic driver
gpio/mxc: move irq_domain_add_legacy call into gpio driver
ARM: imx: eliminate macro IRQ_GPIOx()
ARM: imx: eliminate macro IOMUX_TO_IRQ()
ARM: imx: eliminate macro IMX_GPIO_TO_IRQ()
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Pull arm-soc board specific updates from Arnd Bergmann:
"These changes are all for individual board files. In the long run,
those files will largely go away, and the amount of changes appears to
be continuously decreasing, which is a good sign. This time around,
changes are focused on tegra, omap and samsung."
Fix conflicts in arch/arm/mach-{omap2/common-board-devices.c,tegra/Makefile.boot}
as per the 'for-linus' branch.
* tag 'boards' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (39 commits)
ARM: EXYNOS: Add leds status1 and status2 on Origen board
ARM: S3C64XX: Mark most Cragganmore initdata devinitdata
ARM: EXYNOS: Add missing .reserve field to SMDKC210
ARM: EXYNOS: Add DRM device to SMDK4X12 board
ARM: S3C64XX: Clean up after SPI driver platform data updates
ARM: SAMSUNG: no need to set the value for clk_xusbxti when it is 24Mhz
ARM: EXYNOS: Add framebuffer support for SMDK4X12
ARM: EXYNOS: Add HSOTG support to SMDK4X12
ARM: S5PV210: Add audio platform device in Goni board
ARM: S5PV210: Add audio platform device in Aquila board
ARM: EXYNOS: Add audio platform device in SMDKV310 board
ARM: S3C64XX: Don't specify an irq_base for WM1192-EV1 board
ARM: OMAP3: Fix omap3evm randconfig error introduced by VBUS support
ARM: OMAP: board-omap4panda: MUX configuration for sys_nirq2
ARM: OMAP: board-4430sdp: MUX configuration for sys_nirq2
ARM: OMAP3530evm: set pendown_state and debounce time for ads7846
ARM: omap3evm: enable VBUS switch for EHCI tranceiver
ARM: OMAP3EVM: Adding USB internal LDOs board file
ARM: OMAP3EVM: Add NAND flash definition
ARM: OMAP3: cm-t35: add tvp5150 decoder support
...
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Pull support for three new arm SoC types from Arnd Bergmann:
- The mvebu platform includes Marvell's Armada XP and Armada 370 chips,
made by the mvebu business unit inside of Marvell. Since the same
group also made the older but similar platforms we call "orion5x",
"kirkwood", "mv78xx0" and "dove", we plan to move all of them into
the mach-mvebu directory in the future.
- socfpga is Altera's platform based on Cortex-A9 cores and a lot of
FPGA space. This is similar to the Xilinx zynq platform we already
support. The code is particularly clean, which is helped by the fact
that the hardware doesn't do much besides the parts that are expected
to get added in the FPGA.
- The OMAP subarchitecture gains support for the latest generation, the
OMAP5 based on the new Cortex-A15 core. Support is rather
rudimentary for now, but will be extended in the future.
* tag 'newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (25 commits)
ARM: socfpga: initial support for Altera's SOCFPGA platform
arm: mvebu: generate DTBs for supported SoCs
ARM: mvebu: MPIC: read number of interrupts from control register
arm: mach-mvebu: add entry to MAINTAINERS
arm: mach-mvebu: add compilation/configuration change
arm: mach-mvebu: add defconfig
arm: mach-mvebu: add documentation for new device tree bindings
arm: mach-mvebu: add support for Armada 370 and Armada XP with DT
arm: mach-mvebu: add source files
arm: mach-mvebu: add header
clocksource: time-armada-370-xp: Marvell Armada 370/XP SoC timer driver
ARM: Kconfig update to support additional GPIOs in OMAP5
ARM: OMAP5: Add the build support
arm/dts: OMAP5: Add omap5 dts files
ARM: OMAP5: board-generic: Add device tree support
ARM: omap2+: board-generic: clean up the irq data from board file
ARM: OMAP5: Add SMP support
ARM: OMAP5: Add the WakeupGen IP updates
ARM: OMAP5: l3: Add l3 error handler support for omap5
ARM: OMAP5: gpmc: Update gpmc_init()
...
Conflicts:
Documentation/devicetree/bindings/arm/omap/omap.txt
arch/arm/mach-omap2/Makefile
drivers/clocksource/Kconfig
drivers/clocksource/Makefile
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Pull arm-soc timer updates from Arnd Bergmann:
"This contains two branches dealing with timers, one for the picoxcell
platform that is now using DT with the platform-independent
dw_apb_timer driver. The other change is for the omap-specific
dmtimer driver."
* tag 'timer' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
clocksource: dw_apb_timer: Add common DTS glue for dw_apb_timer
ARM: OMAP2+: Simplify dmtimer clock aliases
ARM: OMAP2+: Move dmtimer clock set function to dmtimer driver
ARM: OMAP1: Fix dmtimer support
ARM: OMAP: Add flag to indicate if a timer needs a manual reset
ARM: OMAP: Remove timer function pointer for context loss counter
ARM: OMAP: Remove loses_context variable from timer platform data
ARM: OMAP2+: Fix external clock support for dmtimers
ARM: OMAP2+: HWMOD: Correct timer device attributes
ARM: OMAP: Add DMTIMER capability variable to represent timer features
ARM: OMAP2+: Add dmtimer platform function to reserve systimers
ARM: OMAP2+: Remove unused max number of timers definition
ARM: OMAP: Remove unnecessary clk structure
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Pull arm-soc spi updates from Arnd Bergmann:
"These changes conceptually belong into the spi tree, but we decided to
put them into arm-soc to better deal with interdependencies with other
platform specific patches that are already there."
* tag 'spi' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
spi/s3c64xx: Expand S3C64XX_SPI_{DE,}ACT macros at call sites
spi/s3c64xx: Convert to devm_request_and_ioremap()
spi/s3c64xx: Put the /CS GPIO into output mode
spi/s3c64xx: Fix handling of errors in gpio_request()
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Pull arm-soc device tree description updates from Arnd Bergmann:
"This branch contains two kinds of updates: Some platforms in the
process of getting converted to device tree based booting, and the
platform specific patches necessary for that are included here.
Other platforms are already converted, so we just need to update the
actual device tree source files and the binding documents to add
support for new board and new drivers.
In the future we will probably separate those into two branches, and
in the long run, the plan is to move the device tree source files out
of the kernel repository, but that has to wait until we have completed
a much larger portion of the binding documents."
Fix up trivial conflicts in arch/arm/mach-imx/clk-imx6q.c due to newly
added clkdev registers next to a few removed unnecessary ones.
* tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (119 commits)
ARM: LPC32xx: Add PWM to base dts file
ARM: EXYNOS: mark the DMA channel binding for SPI as preliminary
ARM: dts: Add nodes for spi controllers for SAMSUNG EXYNOS5 platforms
ARM: EXYNOS: Enable platform support for SPI controllers for EXYNOS5
ARM: EXYNOS: Add spi clock support for EXYNOS5
ARM: dts: Add nodes for spi controllers for SAMSUNG EXYNOS4 platforms
ARM: EXYNOS: Enable platform support for SPI controllers for EXYNOX4
ARM: EXYNOS: Fix the incorrect hierarchy of spi controller bus clock
ARM: ux500: Remove PMU platform registration when booting with DT
ARM: ux500: Remove temporary snowball_of_platform_devs enablement structure
ARM: ux500: Ensure vendor specific properties have the vendor's identifier
pinctrl: pinctrl-nomadik: Append sleepmode property with vendor specific prefixes
ARM: ux500: Move rtc-pl031 registration to Device Tree when enabled
ARM: ux500: Enable the AB8500 RTC for all DT:ed DB8500 based devices
ARM: ux500: Correctly reference IRQs supplied by the AB8500 from Device Tree
ARM: ux500: Apply ab8500-debug node do the db8500 DT structure
ARM: ux500: Add a ab8500-usb Device Tree node for db8500 based devices
ARM: ux500: Add db8500 Device Tree node for misc/ab8500-pwm
ARM: ux500: Add db8500 Device Tree node for ab8500-sysctrl
ARM: ux500: Enable LED heartbeat functionality on Snowbal via DT
...
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Pull samsung arm-soc dma changes from Arnd Bergmann:
"Some platforms are not yet converted to use the dmaengine framework,
including some of the samsung SoCs. In the meantime, we treat this as
platform code and merge the patches through the arm-soc tree."
* tag 'dma' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: SAMSUNG: Fix compiler warning in dma-ops.c file
ASoC: follow the updated samsung DMA common operations
spi/s3c64xx: Add the use of DMA config operation
ARM: SAMSUNG: Add config() function in DMA common operations
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Pull arm soc-specific updates from Arnd Bergmann:
"This is stuff that does not fit well into another category and in
particular is not related to a particular board. The largest part in
here is extending the am33xx support in the omap platform."
Fix up trivial conflicts in arch/arm/mach-{imx/mach-mx35_3ds.c, tegra/Makefile}
* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (74 commits)
ARM: LPC32xx: Add PWM support
ARM: LPC32xx: Add PWM clock
ARM: LPC32xx: Set system serial based on cpu unique id
ARM: vexpress: Config option for early printk console
ARM: vexpress: Add Device Tree for V2P-CA15_CA7 core tile
ARM: vexpress: Convert V2P-CA15 Device Tree to 64 bit addresses
ARM: vexpress: Add fixed regulator for SMSC
ARM: vexpress: Add missing SP804 interrupt in motherboard's DTS files
ARM: vexpress: Initial common clock support
ARM: SAMSUNG: Introduce Kconfig variable for Samsung custom clk API
ARM: EXYNOS: Add missing static storage class specifier in pmu.c file
ARM: EXYNOS: Make combiner_init function static
ARM: EXYNOS: Update HSOTG PHY clock setting for EXYNOS4X12
ARM: versatile: Make plat-versatile clock optional
ARM: vexpress: Check master site in daughterboard's sysctl operations
ARM: vexpress: remove automatic errata workaround selection
ARM: LPC32xx: Adjust to pl08x DMA interface changes
ARM: EXYNOS: Clear SYS_WDTRESET bit to use watchdog reset
ARM: imx: fix mx51 ehci setup errors
ARM: imx: make ehci power/oc polarities configurable
...
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Pull general arm-soc cleanups from Arnd Bergmann:
"These are all boring changes, moving stuff around or renaming things
mostly, and also getting rid of stuff that is duplicate or should not
be there to start with. Platform-wise this is all over the place,
mainly omap, samsung, at91, imx and tegra."
Resolve trivial conflict in arch/arm/mach-omap2/clockdomains3xxx_data.c
* tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (67 commits)
ARM: clps711x: Remove the setting of the time
ARM: clps711x: Removed superfluous transform virt_to_bus and related functions
ARM: clps711x/p720t: Replace __initcall by .init_early call
ARM: S3C24XX: Remove unused GPIO definitions for Openmoko GTA02 board
ARM: S3C24XX: Remove unused GPIO definitions for port J
ARM: S3C24XX: Remove unused GPA, GPE, GPH bank GPIO aliases
ARM: S3C24XX: Convert the touchscreen setup code to common GPIO API
ARM: S3C24XX: Convert the PM code to gpiolib API
ARM: S3C24XX: Convert QT2410 board file to the gpiolib API
ARM: S3C24XX: Convert SMDK board file to the gpiolib API
ARM: S3C24XX: Free the backlight gpio requested in Mini2440 board code
ARM: imx: remove unused pdata from device macros
ARM: imx: Kconfig: Remove IMX_HAVE_PLATFORM_IMX_SSI from MACH_MX25_3DS
ARM: at91: fix new build errors
ARM: at91: add AIC5 support
ARM: at91: remove mach/irqs.h
ARM: at91: sparse irq support
ARM: at91: at91 based machines specify their own irq handler at run time
ARM: at91: remove static irq priorities for sam9x5
ARM: at91: add of irq priorities support
...
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Pull UBI changes from Artem Bityutskiy:
"Change the default amount of eraseblocks which UBI reserves for bad
block handling from 1% to 2%, because 1% does not meet most modern
flash requirements. 1% was good enough in the past for old
high-quality SLCs, but nowadays 2% is much more appropriate.:
Other changes are clean-ups.
* tag 'upstream-3.6-rc1' of git://git.infradead.org/linux-ubi:
UBI: harmonize the update of ubi->beb_rsvd_pebs
UBI: trivial: fix comment of ubi_calculate_reserved function
UBI: fix spelling of detach in debug output
UBI: Change the default percentage of reserved PEB
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git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
Pull the big VFS changes from Al Viro:
"This one is *big* and changes quite a few things around VFS. What's in there:
- the first of two really major architecture changes - death to open
intents.
The former is finally there; it was very long in making, but with
Miklos getting through really hard and messy final push in
fs/namei.c, we finally have it. Unlike his variant, this one
doesn't introduce struct opendata; what we have instead is
->atomic_open() taking preallocated struct file * and passing
everything via its fields.
Instead of returning struct file *, it returns -E... on error, 0
on success and 1 in "deal with it yourself" case (e.g. symlink
found on server, etc.).
See comments before fs/namei.c:atomic_open(). That made a lot of
goodies finally possible and quite a few are in that pile:
->lookup(), ->d_revalidate() and ->create() do not get struct
nameidata * anymore; ->lookup() and ->d_revalidate() get lookup
flags instead, ->create() gets "do we want it exclusive" flag.
With the introduction of new helper (kern_path_locked()) we are rid
of all struct nameidata instances outside of fs/namei.c; it's still
visible in namei.h, but not for long. Come the next cycle,
declaration will move either to fs/internal.h or to fs/namei.c
itself. [me, miklos, hch]
- The second major change: behaviour of final fput(). Now we have
__fput() done without any locks held by caller *and* not from deep
in call stack.
That obviously lifts a lot of constraints on the locking in there.
Moreover, it's legal now to call fput() from atomic contexts (which
has immediately simplified life for aio.c). We also don't need
anti-recursion logics in __scm_destroy() anymore.
There is a price, though - the damn thing has become partially
asynchronous. For fput() from normal process we are guaranteed
that pending __fput() will be done before the caller returns to
userland, exits or gets stopped for ptrace.
For kernel threads and atomic contexts it's done via
schedule_work(), so theoretically we might need a way to make sure
it's finished; so far only one such place had been found, but there
might be more.
There's flush_delayed_fput() (do all pending __fput()) and there's
__fput_sync() (fput() analog doing __fput() immediately). I hope
we won't need them often; see warnings in fs/file_table.c for
details. [me, based on task_work series from Oleg merged last
cycle]
- sync series from Jan
- large part of "death to sync_supers()" work from Artem; the only
bits missing here are exofs and ext4 ones. As far as I understand,
those are going via the exofs and ext4 trees resp.; once they are
in, we can put ->write_super() to the rest, along with the thread
calling it.
- preparatory bits from unionmount series (from dhowells).
- assorted cleanups and fixes all over the place, as usual.
This is not the last pile for this cycle; there's at least jlayton's
ESTALE work and fsfreeze series (the latter - in dire need of fixes,
so I'm not sure it'll make the cut this cycle). I'll probably throw
symlink/hardlink restrictions stuff from Kees into the next pile, too.
Plus there's a lot of misc patches I hadn't thrown into that one -
it's large enough as it is..."
* 'for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs: (127 commits)
ext4: switch EXT4_IOC_RESIZE_FS to mnt_want_write_file()
btrfs: switch btrfs_ioctl_balance() to mnt_want_write_file()
switch dentry_open() to struct path, make it grab references itself
spufs: shift dget/mntget towards dentry_open()
zoran: don't bother with struct file * in zoran_map
ecryptfs: don't reinvent the wheels, please - use struct completion
don't expose I_NEW inodes via dentry->d_inode
tidy up namei.c a bit
unobfuscate follow_up() a bit
ext3: pass custom EOF to generic_file_llseek_size()
ext4: use core vfs llseek code for dir seeks
vfs: allow custom EOF in generic_file_llseek code
vfs: Avoid unnecessary WB_SYNC_NONE writeback during sys_sync and reorder sync passes
vfs: Remove unnecessary flushing of block devices
vfs: Make sys_sync writeout also block device inodes
vfs: Create function for iterating over block devices
vfs: Reorder operations during sys_sync
quota: Move quota syncing to ->sync_fs method
quota: Split dquot_quota_sync() to writeback and cache flushing part
vfs: Move noop_backing_dev_info check from sync into writeback
...
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This was formerly used to store the tclk value. This is now discovered
using the clk API, rather than pass it as platform data.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@googlemail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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We are currently using an inferior or equal operator for comparing
the transfer frequency with the clock frequency table. Because of
this, we always end up selecting 20Mhz as a frequency, due to the
inequality transfer hz <= 20 Mhz being always true. Fix this by
reversing the inequality, which is how the comparison should be done.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Convert orion_wdt driver to use watchdog framework API.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
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module_platform_driver() replaces module_init() and module_exit()
and makes the code simpler.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
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Some motherboards like the Advantech ARK3400 documentation
use a non-inverted GPIO pin. We fix this by assuming that
the BIOS will set the Polarity bit for the GPIO correctly
at startup and we keep the Bit-setting intact when we start
and stop the watchdog.
Reported-by: Jean-François Deverge <jf.deverge@gmail.com>
Signed-off-by: Dave Mueller <d.mueller@elsoft.ch>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
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intransition state.
OMAP watchdog driver is adapted to runtime PM like a general device
driver but it is not appropriate. It is causing couple of functional
issues.
1. On OMAP4 SYSCLK can't be gated, because of issue with WDTIMER2 module,
which constantly stays in "in transition" state. Value of register
CM_WKUP_WDTIMER2_CLKCTRL is always 0x00010000 in this case.
Issue occurs immediately after first idle, when hwmod framework tries
to disable WDTIMER2 functional clock - "wd_timer2_fck". After this
module falls to "in transition" state, and SYSCLK gating is blocked.
2. Due to runtime PM, watchdog timer may be completely disabled.
In current code base watchdog timer is not disabled only because of
issue 1. Otherwise state of WDTIMER2 module will be "Disabled", and there
will be no interrupts from omap_wdt. In other words watchdog will not
work at all.
Watchdong is a special IP and it should not be disabled otherwise
purpose of it itself is defeated. Watchdog functional clock should
never be disabled. This patch updates the runtime PM handling in
driver so that runtime PM is limited only during probe/shutdown
and suspend/resume.
The patch fixes issue 1 and 2
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
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ie6xx_wdt_probe() calls ie6xx_wdt_debugfs_exit() as part of
it's error cleanup path, and ie6xx_wdt_debugfs_exit() is
currently annotated __devexit.
Signed-off-by: Gerard Snitselaar <dev@snitselaar.org>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
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