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The SAI_IPG clocks are enabled by the same bits that control SAI_ROOT_CLK
clocks, so represent them as shared clocks.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Introduce imx_clk_gate2_shared2() which is similar to the existing
imx_clk_gate2_shared() and passes CLK_OPS_PARENT_ENABLE flag, which
is useful for i.MX7 shared clocks.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Add IMX7D_SDMA_CORE_CLK clock so that SDMA can be functional.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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* clk-meson-gxbb-ao:
clk: meson: Add GXBB AO Clock and Reset controller driver
dt-bindings: clock: reset: Add GXBB AO Clock and Reset Bindings
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Adds a Clock and Reset controller driver for the Always-On part
of the Amlogic Meson GXBB SoC.
It exports paired Clocks and Resets lines that will be used by
peripherals in the Always-On subsystem.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Add a Kconfig to define clock configuration for each SoC, and
modify the Makefile to build drivers that only selected in config.
Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Tested-by: John Crispin <blogic@openwrt.org>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Remove __init from functions that will be used by init functions
that support probe deferral.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.
Cc: Kelvin Cheung <keguang.zhang@gmail.com>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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The offset of Core Cluster clock control/status register
on cluster group V3 version is different from others, and
should be plus 0x70000.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: Scott Wood <oss@buserror.net>
Fixes: 9e19ca2f627e ("clk: qoriq: Add ls2080a support.")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Cc: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Merge r8a7796 watchdog clk support from Geert Uytterhoeven:
Add all clocks related to the Watchdog Timer (WDT) controller on the
Renesas R-Car M3-W (r8a7796) SoC.
* tag 'clk-renesas-for-v4.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a7796: Add watchdog module clock
clk: renesas: r8a7796: Add watchdog core clocks
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Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs. We also remove some __init
markings in header files as they're useless and we're in the
area.
Tested-by: Jisheng Zhang <jszhang@marvell.com>
Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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The field "owner" is set by the core.
Thus delete an unneeded initialisation.
Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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We've started getting out of order, fix it.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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* clk-qcom-9615:
dt-bindings: clock: Update bindings for MDM9615 GCC and LCC
clk: mdm9615: Add support for MDM9615 Clock Controllers
dt-bindings: Add MDM9615 DT bindings include files for GCC and LCC
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In order to support the Qualcomm MDM9615 SoC, add support for
the Global and LPASS Clock Controllers.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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* clk-meson-gxbb:
clk: gxbb: add MMC gate clocks, and expose for DT
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Add the SD/eMMC gate clocks and expose them for use by DT.
While at it, also explose FCLK_DIV2 since this is one of the input
clocks to the mux internal to each of the SD/eMMC blocks.
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Maxim Max77620 has one 32KHz clock output and the clock HW
IP used on this PMIC is same as what it is there in the MAX77686.
Add clock driver support for MAX77620 on the MAX77686 driver.
CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
CC: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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The clock IP used on the Maxim PMICs max77686 and max77802 are
same. The configuration of clock register is also same except
the number of clocks.
Part of common code utilisation, there is 3 files for these chips
clock driver, one for common and two files for driver registration.
Combine both drivers into single file and move common code into
same common file reduces the 2 files and make max77686 and max77802
clock driver in single fine. This driver does not depends on the
parent driver structure. The regmap handle is acquired through
regmap APIs for the register access.
This combination of driver helps on adding clock driver for different
Maxim PMICs which has similar clock IP like MAX77620 and MAX20024.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
CC: Javier Martinez Canillas <javier@dowhile0.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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This function is only called by builtin code, but we always
exported it and had marked it as __init before commit
e4eda8e0654c (clk: remove exported function from __init section,
2013-01-06) removed that marking. Given that it isn't used by
modules, lets unexport it and add back __init.
Cc: Denis Efremov <yefremov.denis@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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This function is marked __init, so it can't possibly need to be
exported to modules. Remove the marking.
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Before commit 0861e5b8cf80 (clk: Add clk_hw OF clk providers,
2016-02-05) __of_clk_get_from_provider() would return an error
pointer of the provider's choosing if there was a provider
registered and EPROBE_DEFER otherwise. After that commit, it
would return EPROBE_DEFER regardless of whether or not the
provider returned an error. This is odd and can lead to behavior
where clk consumers keep probe deferring when they should be
seeing some other error.
Let's restore the previous behavior where we only return
EPROBE_DEFER when there isn't a provider in our of_clk_providers
list. Otherwise, return the error from the last provider we find
that matches the node.
Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Fixes: 0861e5b8cf80 ("clk: Add clk_hw OF clk providers")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Use the builtin_platform_driver() macro to make the code simpler.
Signed-off-by: Wei Yongjun <weiyj.lk@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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These clocks are the ones which will be used as source for the
peripherals of the Armada 3700 SoC. On this SoC there is two blocks of
clocks: the North bridge one and the South bridge one.
Most of them are gatable. Most of the time their rate are their parent
rated divided by a ratio depending of two registers. Their parent can be
choose between the TBG clocks for most of them.
However, some of them can't choose their parent or directly depend of the
xtal clocks. Other ones do not use exactly the same pattern to find the
ratio between their parent rate and their rate.
For these reason each clock is a composite clock and the operations they
use are different depending of the clock.
According to the datasheet it would be possible to select the parent
clock and the ratio, however currently the driver does not support it.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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These clocks are children of the xtal clock and each one can be selected
as a source for the peripheral clocks.
According to the datasheet it should be possible to modify their rate,
but currently it is not supported.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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This clock is the parent of all the Armada 3700 clocks. It is a fixed
rate clock which depends on the gpio configuration read when resetting
the SoC.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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The driver is to provide the functional clock to OMAP4/5 McPDM. The clock
is named as pdmclk in the documentations so change the function names,
structure names and variables to align with this.
At the same time rename the driver from "twl6040-clk" to "twl6040-pdmclk".
This can be done w/o regression since the clock driver is not in use at
the moment, the MFD core driver is not even registering the device for it.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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In order ot be able to use the pdmclk clock via DT it need to be registered
as of_clk_provide.
Since the twl6040 clock driver does not have it's own DT node, use the
parent's node for registering.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Since the drover only supports prepare callbacks, the use of is_enabled is
not correct, it should be handling is_prepared.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Both SATA and second USB3.0 interface are supported in Armada-39x SoC
family. Add necessary clk description, so both xhci and sata drivers
can be correctly initialized.
The binding documentation has also been updated accordingly.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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This code is clear enough, but the intention will be even clearer
with this.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Adds support for fixed-rate clock providers which have not been
enabled via of_clk_init().
This is required by Device trees overlays that introduce clocks
providers.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
[sboyd@codeaurora.org: Make new private function static, don't
check clk for NULL when unregistering in driver remove]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Adds support for fixed-factor clock providers which have not been
enabled via of_clk_init().
This is required by Device trees overlays that introduce clocks
providers.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
[sboyd@codeaurora.org: Make new private function static, don't
check clk for NULL when unregistering in driver remove]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Some clock providers can be initialized via of_clk_init() and also via
platform device probe.
Avoid double initialization of them by setting the OF_POPULATED flag.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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This driver initializes a clock provider via sun8i_a23_apb0_setup
and then continues the initialization on sun8i_a23_apb0_clk_probe.
Use the new macro to notify the clk subsystem about this behaviour.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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This driver initializes a clock provider via sun4i_a10_mod0_setup
and then continues the initialization on sun4i_a10_mod0_clk_probe.
Use the new macro to notify the clk subsystem about this behaviour.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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This driver initializes a clock provider via lpc18xx_creg_clk_init
and then continues the initialization on lpc18xx_creg_clk_probe.
Use the new macro to notify the clk subsystem about this behaviour.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
[sboyd@codeaurora.org: s/npx/nxp/ in subject]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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This driver initializes a clock provider via of_artpec6_clkctrl_setup
and then continues the initialization on artpec6_clkctrl_probe.
Use the new macro to notify the clk subsystem about this behaviour.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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clk-divider uses clk_readl()/clk_writel() everywhere, except in
clk_divider_round_rate(), where plain readl() is used. Change this to
clk_readl(), as it makes a difference on powerpc.
Fixes: e6d5e7d90be92cee ("clk-divider: Fix READ_ONLY when divider > 1")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Booting the kernel on a imx7s-warp leads to several warnings like these:
[ 0.000000] ------------[ cut here ]------------
[ 0.000000] WARNING: CPU: 0 PID: 0 at kernel/locking/lockdep.c:3536 lock_release+0x2f8/0x330
[ 0.000000] releasing a pinned lock
[ 0.000000] ------------[ cut here ]------------
[ 0.000000] WARNING: CPU: 0 PID: 0 at kernel/locking/lockdep.c:2722 trace_hardirqs_on_caller+0x1ac/0x1f4
[ 0.000000] DEBUG_LOCKS_WARN_ON(unlikely(early_boot_irqs_disabled))
[ 0.000000] ---[ end trace cb88537fdc8fa201 ]---
[ 0.000000] bad: scheduling from the idle thread!
[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 4.7.0-rc7-next-20160715 #404
[ 0.000000] ------------[ cut here ]------------
[ 0.000000] WARNING: CPU: 0 PID: 0 at kernel/time/sched_clock.c:179 sched_clock_register+0x44/0x1f8
[ 0.000000] Modules linked in:
[ 0.000591] ------------[ cut here ]------------
[ 0.000610] WARNING: CPU: 0 PID: 0 at kernel/time/sched_clock.c:179 sched_clock_register+0x44/0x1f8
[ 0.002084] ------------[ cut here ]------------
[ 0.002104] WARNING: CPU: 0 PID: 0 at init/main.c:576 start_kernel+0x258/0x3b0
[ 0.002114] Interrupts were enabled early
This fix is along the same lines as 5e33ebff7edd ("clk: imx7d: do not
set parent of ethernet time/ref clocks") and the explanation from that
commit is:
"The reason for the warning is that setting the parent enables the ENET
PLL since we are using CLK_OPS_PARENT_ENABLE. Enabling the ENET PLL can
cause clk_pllv3_wait_lock to sleep. See also:
commit fc8726a2c021 ("clk: core: support clocks which requires parents
enable (part 2)")."
imx7s-warp does not even use the FEC interface, so we should not really
configure the parent of IMX7D_ENET_AXI_ROOT_SRC in the common MX7 clock
driver code.
The dts file should use the assigned-clocks/assigned-clock-parents method,
so simply remove the configuration of IMX7D_ENET_AXI_ROOT_SRC parent.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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It's always nice to see families reunited, and this is equally true when
talking about parent clocks and their children. However, if the orphan
clk had a positive prepare_count or enable_count, then we would not
migrate those counts up the parent chain correctly.
This has manifested with the recent critical clocks feature, which often
enables clocks very early, before their parents have been registered.
Fixed by replacing the call to clk_core_reparent with calls to
__clk_set_parent_{before,after}.
Cc: James Liao <jamesjj.liao@mediatek.com>
Cc: Erin Lo <erin.lo@mediatek.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
[sboyd@codeaurora.org: Recalc accuracies and rates too]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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According to the datasheet, SDn clocks are from the SDSRC clock. And
the SDSRC has a 1/2 divider. So, we should have ".sdsrc" as an internal
core clock. Otherwise, since the sdhi driver will calculate clock for
a sd card using the wrong parent clock rate, and then performance will
be not good.
Fixes: 90c073e53909da85 ("clk: shmobile: r8a7795: Add SD divider support")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: stable@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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The condition passed to read*_poll_timeout() is the break condition,
i.e. wait for this condition to happen and return success.
The original code assumed the opposite, resulting in a warning when
the PLL clock rate was changed but never lost it's lock as far as
the readout indicated. This was verified by checking the read out
register value.
Fixes: 1d80c14248d6 ("clk: sunxi-ng: Add common infrastructure")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Add the module clock for the Watchdog Timer (WDT) controller on the
Renesas R-Car M3-W (r8a7796) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add all core clocks related to the Watchdog Timer (WDT) controller on
the Renesas R-Car M3-W (r8a7796) SoC: OSC, Internal RCLK, and RCLK.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Pull more block fixes from Jens Axboe:
"As mentioned in the pull the other day, a few more fixes for this
round, all related to the bio op changes in this series.
Two fixes, and then a cleanup, renaming bio->bi_rw to bio->bi_opf. I
wanted to do that change right after or right before -rc1, so that
risk of conflict was reduced. I just rebased the series on top of
current master, and no new ->bi_rw usage has snuck in"
* 'for-linus' of git://git.kernel.dk/linux-block:
block: rename bio bi_rw to bi_opf
target: iblock_execute_sync_cache() should use bio_set_op_attrs()
mm: make __swap_writepage() use bio_set_op_attrs()
block/mm: make bdev_ops->rw_page() take a bool for read/write
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Pull drm zpos property support from Dave Airlie:
"This tree was waiting on some media stuff I hadn't had time to get a
stable branchpoint off, so I just waited until it was all in your tree
first.
It's been around a bit on the list and shouldn't affect anything
outside adding the generic API and moving some ARM drivers to using
it"
* tag 'drm-for-v4.8-zpos' of git://people.freedesktop.org/~airlied/linux:
drm: rcar: use generic code for managing zpos plane property
drm/exynos: use generic code for managing zpos plane property
drm: sti: use generic zpos for plane
drm: add generic zpos property
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Since commit 63a4cc24867d, bio->bi_rw contains flags in the lower
portion and the op code in the higher portions. This means that
old code that relies on manually setting bi_rw is most likely
going to be broken. Instead of letting that brokeness linger,
rename the member, to force old and out-of-tree code to break
at compile time instead of at runtime.
No intended functional changes in this commit.
Signed-off-by: Jens Axboe <axboe@fb.com>
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The original commit missed this function, it needs to mark it a
write flush.
Cc: Mike Christie <mchristi@redhat.com>
Fixes: e742fc32fcb4 ("target: use bio op accessors")
Signed-off-by: Jens Axboe <axboe@fb.com>
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