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2021-06-29Merge branches 'clk-legacy', 'clk-vc5', 'clk-allwinner', 'clk-nvidia' and ↵Stephen Boyd
'clk-imx' into clk-next * clk-legacy: clkdev: remove unused clkdev_alloc() interfaces clkdev: remove CONFIG_CLKDEV_LOOKUP m68k: coldfire: remove private clk_get/clk_put m68k: coldfire: use clkdev_lookup on most coldfire mips: ralink: convert to CONFIG_COMMON_CLK mips: ar7: convert to CONFIG_COMMON_CLK mips: ar7: convert to clkdev_lookup * clk-vc5: clk: vc5: fix output disabling when enabling a FOD * clk-allwinner: clk: sunxi-ng: v3s: fix incorrect postdivider on pll-audio * clk-nvidia: clk: tegra: clk-tegra124-dfll-fcpu: don't use devm functions for regulator clk: tegra: tegra124-emc: Fix clock imbalance in emc_set_timing() clk: tegra: Add stubs needed for compile-testing clk: tegra: Don't deassert reset on enabling clocks clk: tegra: Mark external clocks as not having reset control clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling clk: tegra: Don't allow zero clock rate for PLLs clk: tegra: Halve SCLK rate on Tegra20 clk: tegra: Ensure that PLLU configuration is applied properly clk: tegra: Fix refcounting of gate clocks clk: tegra30: Use 300MHz for video decoder by default * clk-imx: clk: imx8mq: remove SYS PLL 1/2 clock gates clk: imx: scu: Do not enable runtime PM for CPU clks clk: imx: scu: add parent save and restore clk: imx: scu: Only save DC SS clock using non-cached clock rate clk: imx: scu: Add A72 frequency scaling support clk: imx: scu: Add A53 frequency scaling support clk: imx: scu: bypass pi_pll enable status restore clk: imx: scu: detach pd if can't power up clk: imx: scu: bypass cpu clock save and restore clk: imx: scu: add parallel port clock ops clk: imx: scu: add more scu clocks clk: imx: scu: add enet rgmii gpr clocks clk: imx8qm: add clock valid resource checking clk: imx8qxp: add clock valid checking mechnism clk: imx: scu: add gpr clocks support clk: imx: scu: remove legacy scu clock binding support dt-bindings: arm: imx: scu: drop deprecated legacy clock binding dt-bindings: arm: imx: scu: fix naming typo of clk compatible string clk: imx: Remove the audio ipg clock from imx8mp
2021-06-29Merge branches 'clk-qcom', 'clk-versatile', 'clk-renesas', 'clk-sifive' and ↵Stephen Boyd
'clk-ti' into clk-next - duty cycle setting support on qcom clks - qcom MDM9607 GCC - qcom sc8180x display clks - qcom SM6125 GCC - Add TI am33xx spread spectrum clock support * clk-qcom: (22 commits) clk: qcom: clk-alpha-pll: fix CAL_L write in alpha_pll_fabia_prepare clk: qcom: Add camera clock controller driver for SM8250 dt-bindings: clock: add QCOM SM8250 camera clock bindings clk: qcom: clk-alpha-pll: add support for zonda pll clk/qcom: Remove unused variables clk: qcom: smd-rpmcc: Add support for MSM8226 rpm clocks clk: qcom: gcc: Add support for Global Clock controller found on MSM8226 dt-bindings: clock: qcom: Add MSM8226 GCC clock bindings clk: qcom: Add SM6125 (TRINKET) GCC driver dt-bindings: clk: qcom: gcc-sm6125: Document SM6125 GCC driver clk: qcom: gcc: Add support for a new frequency for SC7280 clk: qcom: smd-rpm: Fix wrongly assigned RPM_SMD_PNOC_CLK dt-bindings: clock: qcom: rpmcc: Document MSM8226 compatible clk: qcom: dispcc-sm8250: Add EDP clocks clk: qcom: dispcc-sm8250: Add sc8180x support clk: qcom: smd-rpm: De-duplicate identical entries clk: qcom: smd-rpm: Switch to parent_data clk: qcom: Add MDM9607 GCC driver dt-bindings: clock: Add MDM9607 GCC clock bindings clk: qcom: cleanup some dev_err_probe() calls ... * clk-versatile: clk: versatile: Depend on HAS_IOMEM clk: versatile: remove dependency on ARCH_* * clk-renesas: (22 commits) clk: renesas: Add support for R9A07G044 SoC clk: renesas: Add CPG core wrapper for RZ/G2L SoC dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver dt-bindings: clock: Add r9a07g044 CPG Clock Definitions clk: renesas: r8a77995: Add ZA2 clock clk: renesas: cpg-mssr: Make srstclr[] comment block consistent clk: renesas: cpg-mssr: Remove unused [RM]MSTPCR() definitions clk: renesas: r9a06g032: Switch to .determine_rate() clk: renesas: div6: Implement range checking clk: renesas: div6: Consider all parents for requested rate clk: renesas: div6: Switch to .determine_rate() clk: renesas: div6: Simplify src mask handling clk: renesas: div6: Use clamp() instead of clamp_t() clk: renesas: rcar-usb2-clock-sel: Fix error handling in .probe() clk: renesas: r8a779a0: Add ISPCS clocks clk: renesas: rcar-gen3: Add boost support to Z clocks clk: renesas: rcar-gen3: Add custom clock for PLLs clk: renesas: rcar-gen3: Increase Z clock accuracy clk: renesas: rcar-gen3: Grammar s/dependent of/dependent on/ clk: renesas: rcar-gen3: Remove superfluous masking in cpg_z_clk_set_rate() ... * clk-sifive: clk: analogbits: fix doc warning in wrpll-cln28hpc.c clk: sifive: Fix kernel-doc * clk-ti: drivers: ti: remove redundant error message in adpll.c clk: keystone: syscon-clk: Add support for AM64 specific epwm-tbclk dt-bindings: clock: ehrpwm: Add support for AM64 specific compatible clk: ti: add am33xx/am43xx spread spectrum clock support ARM: dts: am43xx-clocks: add spread spectrum support ARM: dts: am33xx-clocks: add spread spectrum support dt-bindings: ti: dpll: add spread spectrum support clk: ti: fix typo in routine description
2021-06-27drivers: ti: remove redundant error message in adpll.cYu Jiahua
There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by: Yu Jiahua <yujiahua1@huawei.com> Link: https://lore.kernel.org/r/20210616034826.37276-1-yujiahua1@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: clk-alpha-pll: fix CAL_L write in alpha_pll_fabia_prepareJonathan Marek
Caught this when looking at alpha-pll code. Untested but it is clear that this was intended to write to PLL_CAL_L_VAL and not PLL_ALPHA_VAL. Fixes: 691865bad627 ("clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibration") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20210609022852.4151-1-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: Add camera clock controller driver for SM8250Jonathan Marek
Add support for the camera clock controller found on SM8250. Based on the downstream driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Robert Foss <robert.foss@linaro.org> Link: https://lore.kernel.org/r/20210609022051.2171-4-jonathan@marek.ca [sboyd@kernel.org: Add UL to avoid decimal problems] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: clk-alpha-pll: add support for zonda pllJonathan Marek
Ported over from the downstream driver. Will be used by SM8250 CAMCC. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20210609022051.2171-2-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk/qcom: Remove unused variablesPu Lehui
Fix gcc '-Wunused-const-variable' warnings: drivers/clk/qcom/gcc-mdm9607.c:122:37: warning: 'gcc_xo_gpll0_gpll1' defined but not used [-Wunused-const-variable=] drivers/clk/qcom/gcc-mdm9607.c:116:32: warning: 'gcc_xo_gpll0_gpll1_map' defined but not used [-Wunused-const-variable=] drivers/clk/qcom/gcc-mdm9607.c:42:37: warning: 'gcc_xo_sleep' defined but not used [-Wunused-const-variable=] drivers/clk/qcom/gcc-mdm9607.c:37:32: warning: 'gcc_xo_sleep_map' defined but not used [-Wunused-const-variable=] Let's remove them. Signed-off-by: Pu Lehui <pulehui@huawei.com> Link: https://lore.kernel.org/r/20210609061848.87415-1-pulehui@huawei.com Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: smd-rpmcc: Add support for MSM8226 rpm clocksBartosz Dudziak
Add compatible for rpm smd clocks, PMIC and bus clocks which are required on MSM8226 for clients to vote on. Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> Link: https://lore.kernel.org/r/20210605104040.12960-1-bartosz.dudziak@snejp.pl Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: gcc: Add support for Global Clock controller found on MSM8226Bartosz Dudziak
Modify existing MSM8974 driver to support MSM8226 SoC. Override frequencies which are different in this older chip. Register all the clocks to the framework for the clients to be able to request for them. Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> Link: https://lore.kernel.org/r/20210418122909.71434-3-bartosz.dudziak@snejp.pl Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: Add SM6125 (TRINKET) GCC driverKonrad Dybcio
Add the clocks supported in global clock controller, which clock the peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks to the clock framework for the clients to be able to request for them. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Martin Botka <martin.botka@somainline.org> Link: https://lore.kernel.org/r/20210605121040.282053-2-martin.botka@somainline.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> [sboyd@kernel.org: Mark gcc_sm6125_hws array static] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: gcc: Add support for a new frequency for SC7280Taniya Das
There is a requirement to support 52MHz for qup clocks for bluetooth usecase, thus update the frequency table to support the frequency. Fixes: a3cc092196ef ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280") Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1624449471-9984-1-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-25clk: tegra: clk-tegra124-dfll-fcpu: don't use devm functions for regulatorAlexandru Ardelean
The purpose of the device-managed functions is to bind the life-time of an object to that of a parent device object. This is not the case for the 'vdd-cpu' regulator in this driver. A reference is obtained via devm_regulator_get() and immediately released with devm_regulator_put(). In this case, the usage of devm_ functions is slightly excessive, as the un-managed versions of these functions is a little cleaner (and slightly more economical in terms of allocation). This change converts the devm_regulator_{get,put}() to regulator_{get,put}() in the get_alignment_from_regulator() function of this driver. Signed-off-by: Alexandru Ardelean <aardelean@deviqon.com> Link: https://lore.kernel.org/r/20210624084737.42336-1-aardelean@deviqon.com Reviewed-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-22clk: keystone: syscon-clk: Add support for AM64 specific epwm-tbclkLokesh Vutla
AM64 has 9 instances of EPWM modules. And each instance has a clk to Timer-Base sub-module that can be controlled by Control module. Update the driver with all the 9 instance of clocks associated to ti,am64-epwm-tbclk. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210528045743.16537-3-lokeshvutla@ti.com Reviewed-by: Tero Kristo <kristo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-14clk: imx8mq: remove SYS PLL 1/2 clock gatesLucas Stach
Remove the PLL clock gates as the allowing to gate the sys1_pll_266m breaks the uSDHC module which is sporadically unable to enumerate devices after this change. Also it makes AMP clock management harder with no obvious benefit to Linux, so just revert the change. Link: https://lore.kernel.org/r/20210528180135.1640876-1-l.stach@pengutronix.de Fixes: b04383b6a558 ("clk: imx8mq: Define gates for pll1/2 fixed dividers") Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: Do not enable runtime PM for CPU clksNitin Garg
Since CPU clocks are managed by CPUFREQ and ATF, do not enable runtime PM otherwise rpm gets out of status as cpufreq also manages clock states. Signed-off-by: Nitin Garg <nitin.garg@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: add parent save and restoreDong Aisheng
Add clock parent save and restore. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: Only save DC SS clock using non-cached clock rateAnson Huang
Display sub-system has special clock settings in SCFW, the bypassed clock is used instead of PLL in Linux kernel clock tree, so when saving clock rate, need to save non-cached clock rate for Display sub-system's bypass clocks, and other clocks still use the cached clock rate which is with runtime PM ON. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: Add A72 frequency scaling supportAnson Huang
Add A72 clock to support cpufreq on A72 cluster. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: Add A53 frequency scaling supportAnson Huang
Add i.MX8QM cpufreq support for A53 cluster. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: bypass pi_pll enable status restoreDong Aisheng
PI PLL does not support enable/disable. So bypass it's enable status restore. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: detach pd if can't power upDong Aisheng
detach pd if can't power up as it may be allocated to a differet partition. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: bypass cpu clock save and restoreDong Aisheng
CPU clock is managed by ATF. No need save and restore. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: add parallel port clock opsGuoniu.zhou
Because digital pll for parallel interface is on by default, and not provide enable/disable function by scu, so add the related ops for this kind of clocks. Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: add more scu clocksDong Aisheng
Add more scu clocks used by i.MX8 platforms. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: add enet rgmii gpr clocksDong Aisheng
enet tx clk actually is sourced from a gpr divider, not default enet clk. Add enet grp clocks for user to use correctly. Cc: Abel Vesa <abel.vesa@nxp.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx8qm: add clock valid resource checkingDong Aisheng
Add imx8qm clock valid resource checking mechanism Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx8qxp: add clock valid checking mechnismDong Aisheng
clk-imx8qxp is a common SCU clock driver used by both QM and QXP platforms. The clock numbers vary a bit between those two platforms. This patch introduces a mechanism to only register the valid clocks for one platform by checking the clk resource id table. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: add gpr clocks supportDong Aisheng
SCU clock protocol supports a few clocks based on GPR controller registers including mux/divider/gate. Add a generic clock register API to support them all. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: scu: remove legacy scu clock binding supportDong Aisheng
Legacy scu clock binding are not maintained anymore, it has a very limited clocks supported during initial upstreaming and obviously unusable by products. So it's meaningless to keep it in kernel which worse the code readability. Remove it to keep code much cleaner. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-14clk: imx: Remove the audio ipg clock from imx8mpJacky Bai
There is no audio ipg clock on i.MX8MP, so remove this from the clock driver. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-06-10clk: renesas: Add support for R9A07G044 SoCLad Prabhakar
Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-10clk: renesas: Add CPG core wrapper for RZ/G2L SoCLad Prabhakar
Add CPG core wrapper for RZ/G2L family. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-06-08clk: vc5: fix output disabling when enabling a FODLuca Ceresoli
On 5P49V6965, when an output is enabled we enable the corresponding FOD. When this happens for the first time, and specifically when writing register VC5_OUT_DIV_CONTROL in vc5_clk_out_prepare(), all other outputs are stopped for a short time and then restarted. According to Renesas support this is intended: "The reason for that is VC6E has synced up all output function". This behaviour can be disabled at least on VersaClock 6E devices, of which only the 5P49V6965 is currently implemented by this driver. This requires writing bit 7 (bypass_sync{1..4}) in register 0x20..0x50. Those registers are named "Unused Factory Reserved Register", and the bits are documented as "Skip VDDO<N> verification", which does not clearly explain the relation to FOD sync. However according to Renesas support as well as my testing setting this bit does prevent disabling of all clock outputs when enabling a FOD. See "VersaClock ® 6E Family Register Descriptions and Programming Guide" (August 30, 2018), Table 116 "Power Up VDD check", page 58: https://www.renesas.com/us/en/document/mau/versaclock-6e-family-register-descriptions-and-programming-guide Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Reviewed-by: Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/20210527211647.1520720-1-luca@lucaceresoli.net Fixes: 2bda748e6ad8 ("clk: vc5: Add support for IDT VersaClock 5P49V6965") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-08clk: ti: add am33xx/am43xx spread spectrum clock supportDario Binacchi
The patch enables spread spectrum clocking (SSC) for MPU and LCD PLLs. As reported by the TI spruh73x/spruhl7x RM, SSC is only supported for the DISP/LCD and MPU PLLs on am33xx/am43xx. SSC is not supported for DDR, PER, and CORE PLLs. Calculating the required values and setting the registers accordingly was taken from the set_mpu_spreadspectrum routine contained in the arch/arm/mach-omap2/am33xx/clock_am33xx.c file of the u-boot project. In locked condition, DPLL output clock = CLKINP *[M/N]. In case of SSC enabled, the reference manual explains that there is a restriction of range of M values. Since the omap2_dpll_round_rate routine attempts to select the minimum possible N, the value of M obtained is not guaranteed to be within the range required. With the new "ti,min-div" parameter it is possible to increase N and consequently M to satisfy the constraint imposed by SSC. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Tero Kristo <kristo@kernel.org> Link: https://lore.kernel.org/r/20210606202253.31649-6-dariobin@libero.it Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-08clk: ti: fix typo in routine descriptionDario Binacchi
Replace _omap3_noncore_dpll_program with omap3_noncore_dpll_program. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20210606202253.31649-2-dariobin@libero.it Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-08clk: qcom: smd-rpm: Fix wrongly assigned RPM_SMD_PNOC_CLKKonrad Dybcio
During my big cleanup I managed to assign an AO clock to its non-AO binding. Fix this. Reported-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210606192657.51037-1-konrad.dybcio@somainline.org Fixes: a0384ecfe2aa ("clk: qcom: smd-rpm: De-duplicate identical entries") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-08clkdev: remove unused clkdev_alloc() interfacesArnd Bergmann
The last user of clkdev_alloc() and clkdev_hw_alloc() was removed last year, so everything now calls clkdev_create() and clkdev_hw_create() instead. Removing the unused functions lets the compiler optimize the remaining ones slightly better. Fixes: e5006671acc7 ("clk: versatile: Drop the legacy IM-PD1 clock code") Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-06-08clkdev: remove CONFIG_CLKDEV_LOOKUPArnd Bergmann
This option is now synonymous with CONFIG_HAVE_CLK, so use the latter globally. Any out-of-tree platform ports that still use a private clk_get()/clk_put() implementation should move to CONFIG_COMMON_CLK. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-06-04clk: versatile: Depend on HAS_IOMEMStephen Boyd
kbuild robot reports that s390 fails to build this driver with COMPILE_TEST. Let's depend on HAS_IOMEM so that s390 doesn't try to build it. Cc: Lee Jones <lee.jones@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reported-by: kernel test robot <lkp@intel.com> Fixes: 419b3ab6987f ("clk: versatile: remove dependency on ARCH_*") Link: https://lore.kernel.org/r/20210604192321.2594519-1-sboyd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-02clk: tegra: tegra124-emc: Fix clock imbalance in emc_set_timing()Yang Yingliang
After calling clk_prepare_enable(), clk_disable_unprepare() needs be called when prepare_timing_change() failed. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-06-02clk: qcom: dispcc-sm8250: Add EDP clocksBjorn Andersson
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210511041719.591969-2-bjorn.andersson@linaro.org Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-02clk: qcom: dispcc-sm8250: Add sc8180x supportBjorn Andersson
The display clock controller in SC8180x is reused from SM8150, so add the necessary compatible and wire up the driver to enable this. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210511041719.591969-1-bjorn.andersson@linaro.org Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-02clk: qcom: smd-rpm: De-duplicate identical entriesKonrad Dybcio
It makes negative sense to keep repeating the same definitions over and over and over and over again, just with changed names.. De-duplicate to make for a drastically smaller file size. This makes the object file size 55% smaller according to bloat-o-meter: Total: Before=70713, After=31353, chg -55.66% Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210524225456.398817-2-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-02clk: qcom: smd-rpm: Switch to parent_dataKonrad Dybcio
Switch to parent_data and with that fix the longstanding issue where if there wasn't a clock precisely named "xo_board", rpmcc would not play along well. This started to show lately when "xo_board" was being changed to "xo-board" so as to align with DTS naming spec. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210524225456.398817-1-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-02clk: qcom: Add MDM9607 GCC driverKonrad Dybcio
Add Global Clock Controller (GCC) support for MDM9607 SoC. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210313020310.386152-2-konrad.dybcio@somainline.org [sboyd@kernel.org: Drop clk.h include] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-01clk: analogbits: fix doc warning in wrpll-cln28hpc.cYang Yingliang
Fix the following make W=1 warning: drivers/clk/analogbits/wrpll-cln28hpc.c:227: warning: expecting prototype for wrpll_configure(). Prototype was for wrpll_configure_for_rate() instead Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20210601114154.3163327-1-yangyingliang@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-01clk: sifive: Fix kernel-docYang Li
Fix function name in sifive-prci.c kernel-doc comment to remove a warning. drivers/clk/sifive/sifive-prci.c:573: warning: expecting prototype for sifive_prci_init(). Prototype was for sifive_prci_probe() instead Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/1621851730-32287-1-git-send-email-yang.lee@linux.alibaba.com Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-01clk: versatile: remove dependency on ARCH_*Peter Collingbourne
It is now possible to build a modular kernel for vexpress by not setting CONFIG_ARCH_VEXPRESS=y and instead setting =m on the drivers that it normally implies. This is with the exception of CLK_VEXPRESS_OSC which is currently hidden behind a dependency on one of several ARCH_* variables. Remove that dependency so that CLK_VEXPRESS_OSC may be enabled without it. Signed-off-by: Peter Collingbourne <pcc@google.com> Link: https://linux-review.googlesource.com/id/I435a21e2e5f6187db54f4ef2079b60028ab2ea69 Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210520161702.3746174-1-lee.jones@linaro.org Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-01clk: qcom: cleanup some dev_err_probe() callsDan Carpenter
The dev_err_probe() function prints an error message if the error code is not -EPROBE_DEFER. If we know the error code in is -ENODEV then there is no reason to check. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/YJotlJBJ1CVAgvMT@mwanda Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-01clk: qcom: Simplify usage of dev_err_probe()Uwe Kleine-König
dev_err_probe() returns the error code passed as second parameter. Also if the error code is -EPROBE_DEFER dev_err_probe() is silent, so there is no need to check for this value before calling dev_err_probe(). Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org> Link: https://lore.kernel.org/r/20210427164522.2886825-1-uwe@kleine-koenig.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 18:10:33 +0000