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The reset value of the uSOF cycle period is incorrect. Set it to
60,000 bits. Without this, several commercial USB flash memory
devices and hubs fail to work properly.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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Additional PHY tuning is needed to obtain compliant 'eye' diagram
electrical characteristics.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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The UCTL clock initialization will cause the ehci and ohci blocks to
become inoperable if the clocks are reinitialized.
Check to see if the clocks have already been initialized.
Also use a mutex to protect the clock initialization code so that
there can be no attempt to use the clocks before they are fully
configured.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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The OCTEON II SOC has USB EHCI and OHCI controllers connected directly
to the internal I/O bus. This patch adds the necessary 'glue' logic
to allow ehci-hcd and ohci-hcd drivers to work on OCTEON II.
The OCTEON normally runs big-endian, and the ehci/ohci internal
registers have host endianness, so we need to select
USB_EHCI_BIG_ENDIAN_MMIO.
The ehci and ohci blocks share a common clocking and PHY
infrastructure. Initialization of the host controller and PHY clocks
is common between the two and is factored out into the
octeon2-common.c file.
Setting of USB_ARCH_HAS_OHCI and USB_ARCH_HAS_EHCI is done in
arch/mips/Kconfig in a following patch.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-usb@vger.kernel.org
To: dbrownell@users.sourceforge.net
Patchwork: http://patchwork.linux-mips.org/patch/1675/
Acked-by: Greg Kroah-Hartman <gregkh@suse.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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