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path: root/drivers/spi/spi-pic32-sqi.c
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2016-08-08spi: pic32-sqi: use list_move_tail and list_moveWei Yongjun
Using list_move_tail() and list_move() to simplify the code. Signed-off-by: Wei Yongjun <weiyj.lk@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-07-24spi: pic32-sqi: fixup wait_for_completion_timeout return handlingNicholas Mc Guire
wait_for_completion_timeout returns unsigned long not int so the check for <= 0 should be == 0 here, and the type unsigned long. The function return is set to -ETIMEDOUT to reflect the actual problem. Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-05-06spi: pic32-sqi: Remove pic32_sqi_setup and pic32_sqi_cleanupAxel Lin
Current code does not use ctldata at all, so remove spi_set_ctldata call. spi_setup() will set spi->bits_per_word = 8 if it was not set, so remove !spi->max_speed_hz checking. The spi core allows absent of spi->max_speed_hz setting, if it was not set spi_setup() assigns spi->master->max_speed_hz to it. spi core allows spi->max_speed_hz > spi->master->max_speed_hz, in this case spi core will limit the transfer speed to ensure xfer->speed_hz won't greater than spi->master->max_speed_hz so remove checking if spi->max_speed_hz is higher than spi->master->max_speed_hz. As a result, both pic32_sqi_setup() and pic32_sqi_cleanup() can be removed. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-04-22spi: pic32-sqi: silence array overflow warningDan Carpenter
We read one element beyond the end of the array when we access "rdesc[i + 1]" so it causes a static checker warning. It's harmless because we write over it again on the next line. But let's just silence the warning. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Purna Chandra Mandal <purna.mandal@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-04-18spi: pic32-sqi: add SPI driver for PIC32 SQI controller.Purna Chandra Mandal
This driver implements SPI master interface for Quad SPI controller, specifically for accessing quad SPI flash. It uses descriptor-based DMA transfer mode and supports half-duplex communication for single, dual and quad SPI transactions. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Mark Brown <broonie@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>