summaryrefslogtreecommitdiff
path: root/drivers/spi/spi-cadence.c
AgeCommit message (Collapse)Author
2021-01-15spi: cadence: cache reference clock rate during probeMichael Hennerich
The issue is that using SPI from a callback under the CCF lock will deadlock, since this code uses clk_get_rate(). Fixes: c474b38665463 ("spi: Add driver for Cadence SPI controller") Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20210114154217.51996-1-alexandru.ardelean@analog.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-10-09spi: cadence: Add SPI transfer delaysDaniel Mack
When processing an SPI transfer, honor the delay that might be passed along with it. Signed-off-by: Daniel Mack <daniel@zonque.org> Link: https://lore.kernel.org/r/20201009100309.381279-1-daniel@zonque.org Signed-off-by: Mark Brown <broonie@kernel.org>
2020-07-22spi: spi-cadence: add support for chip select highShreyas Joshi
The spi cadence driver should support spi-cs-high in mode bits so that the peripherals that needs the chip select to be high active can use it. Add the SPI-CS-HIGH flag in the supported mode bits. Signed-off-by: Shreyas Joshi <shreyas.joshi@biamp.com> Link: https://lore.kernel.org/r/20200710211655.1564-1-shreyas.joshi@biamp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-11-27spi: cadence: Correct handling of native chipselectCharles Keepax
To fix a regression on the Cadence SPI driver, this patch reverts commit 6046f5407ff0 ("spi: cadence: Fix default polarity of native chipselect"). This patch was not the correct fix for the issue. The SPI framework calls the set_cs line with the logic level it desires on the chip select line, as such the old is_high handling was correct. However, this was broken by the fact that before commit 3e5ec1db8bfe ("spi: Fix SPI_CS_HIGH setting when using native and GPIO CS") all controllers that offered the use of a GPIO chip select had SPI_CS_HIGH applied, even for hardware chip selects. This caused the value passed into the driver to be inverted. Which unfortunately makes it look like a logical enable the chip select value. Since the core was corrected to not unconditionally apply SPI_CS_HIGH, the Cadence driver, whilst using the hardware chip select, will deselect the chip select every time we attempt to communicate with the device, which results in failed communications. Fixes: 3e5ec1db8bfe ("spi: Fix SPI_CS_HIGH setting when using native and GPIO CS") Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191126164140.6240-1-ckeepax@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-09-04spi: cadence: use devm_platform_ioremap_resource() to simplify codeYueHaibing
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20190904135918.25352-9-yuehaibing@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-08-02spi: Remove dev_err() usage after platform_get_irq()Stephen Boyd
We don't need dev_err() messages when platform_get_irq() fails now that platform_get_irq() prints an error message itself when something goes wrong. Let's remove these prints with a simple semantic patch. // <smpl> @@ expression ret; struct platform_device *E; @@ ret = ( platform_get_irq(E, ...) | platform_get_irq_byname(E, ...) ); if ( \( ret < 0 \| ret <= 0 \) ) { ( -if (ret != -EPROBE_DEFER) -{ ... -dev_err(...); -... } | ... -dev_err(...); ) ... } // </smpl> While we're here, remove braces on if statements that only have one statement (manually). Cc: Mark Brown <broonie@kernel.org> Cc: linux-spi@vger.kernel.org Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20190730181557.90391-42-swboyd@chromium.org Signed-off-by: Mark Brown <broonie@kernel.org>
2019-05-24treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 39Thomas Gleixner
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 2 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190520170857.824091446@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-01-24spi: cadence: Fix default polarity of native chipselectLinus Walleij
The Cadence controller also supports platforms specifying native chipselects. When I enforce the use of high CS for drivers opting in for using GPIO descriptors, I inadvertedly switched the driver to also use active high chip select for native chip selects. Fix this by inverting the logic in the callback for the native chip select. Rename the parameter from "is_high" (which is interpreted as being high when 0, which is confusing, I will not make any drug-related jokes here) to "enabled" which is more intuitive, especially now that it is true when CS is supposed to be enabled. Cc: Wei Yongjun <weiyongjun1@huawei.com> Fixes: cfeefa79dc37 ("spi: cadence: Convert to use CS GPIO descriptors") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-14spi: cadence: Correct initialisation of runtime PMCharles Keepax
Currently the driver calls pm_runtime_put_autosuspend but without ever having done a pm_runtime_get, this causes the reference count in the pm runtime core to become -1. The bad reference count causes the core to sometimes suspend whilst an active SPI transfer is in progress. arizona spi0.1: SPI transfer timed out spi_master spi0: failed to transfer one message from queue The correct proceedure is to do all the initialisation that requires the hardware to be powered up before enabling the PM runtime, then enable the PM runtime having called pm_runtime_set_active to inform it that the hardware is currently powered up. The core will then power it down at it's leisure and no explicit pm_runtime_put is required. Fixes: d36ccd9f7ea4 ("spi: cadence: Runtime pm adaptation") Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-09spi: cadence: Convert to use CS GPIO descriptorsLinus Walleij
This converts the Cadence SPI master driver to use GPIO descriptors for chip select handling. The Cadence driver was allocating a state container just to hold the requested GPIO line and contained lots of polarity inversion code. As this is all handled by gpiolib and a simple devm_* request in the core, and as the driver is fully device tree only, most of this code chunk goes away in favour of central handling. The setup/cleanup callbacks goes away. This driver does NOT drive the CS line by setting the value of the GPIO so it relies on the SPI core to do this, which should work just fine with the descriptors. Cc: Wei Yongjun <weiyongjun1@huawei.com> Cc: Janek Kotas <jank@cadence.com> Cc: Linuxarm <linuxarm@huawei.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-07-11spi: cadence: Fix missing clk_disable_unprepare() on error in ↵Wei Yongjun
cnds_runtime_resume() Fix the missing clk_disable_unprepare() before return from cnds_runtime_resume() in the error handling case. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-06-18spi: cadence: Change usleep_range() to udelay(), for atomic contextJanek Kotas
The path "spi: cadence: Add usleep_range() for cdns_spi_fill_tx_fifo()" added a usleep_range() function call, which cannot be used in atomic context. However the cdns_spi_fill_tx_fifo() function can be called during an interrupt which may result in a kernel panic: BUG: scheduling while atomic: grep/561/0x00010002 Modules linked in: Preemption disabled at: [<ffffff800858ea28>] wait_for_common+0x48/0x178 CPU: 0 PID: 561 Comm: grep Not tainted 4.17.0 #1 Hardware name: Cadence CSP (DT) Call trace: dump_backtrace+0x0/0x198 show_stack+0x14/0x20 dump_stack+0x8c/0xac __schedule_bug+0x6c/0xb8 __schedule+0x570/0x5d8 schedule+0x34/0x98 schedule_hrtimeout_range_clock+0x98/0x110 schedule_hrtimeout_range+0x10/0x18 usleep_range+0x64/0x98 cdns_spi_fill_tx_fifo+0x70/0xb0 cdns_spi_irq+0xd0/0xe0 __handle_irq_event_percpu+0x9c/0x128 handle_irq_event_percpu+0x34/0x88 handle_irq_event+0x48/0x78 handle_fasteoi_irq+0xbc/0x1b0 generic_handle_irq+0x24/0x38 __handle_domain_irq+0x84/0xf8 gic_handle_irq+0xc4/0x180 This patch replaces the function call with udelay() which can be used in an atomic context, like an interrupt. Signed-off-by: Jan Kotas <jank@cadence.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
2018-06-04Merge branch 'spi-4.17' into spi-4.18 for the merge windowMark Brown
2018-04-20spi: simplify getting .drvdataWolfram Sang
We should get drvdata from struct device directly. Going via platform_device is an unneeded step back and forth. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-04-18spi: cadence: Add usleep_range() for cdns_spi_fill_tx_fifo()sxauwsk
In case of xspi work in busy condition, may send bytes failed. once something wrong, spi controller did't work any more My test found this situation appear in both of read/write process. so when TX FIFO is full, add one byte delay before send data; Signed-off-by: sxauwsk <sxauwsk@163.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-08-08spi: cadence: Add support for context lossShubhrajyoti Datta
Context could be lost across the suspend and resume. Reinit the driver to tide over. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-08-08spi: cadence: change sequence of calling runtime_enableNaga Sureshkumar Relli
call pm_runtime_enable after set_active other wise it will enable clock always. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-04-26spi: cadence: Allow for GPIO pins to be used as chipselectsMoritz Fischer
This adds support for using GPIOs for chipselects as described by the default dt-bindings. Signed-off-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-04-18spi: cadence: mark pm functions __maybe_unusedArnd Bergmann
The newly added runtime PM support for the cadence spi driver causes harmless warnings when PM is disabled: drivers/spi/spi-cadence.c:681:12: warning: 'cnds_runtime_suspend' defined but not used drivers/spi/spi-cadence.c:652:12: warning: 'cnds_runtime_resume' defined but not used This adds __maybe_unused annotations to the respective functions to shut up the warnings, while leaving the code in place for compile testing and avoiding ugly #ifdefs. Fixes: d36ccd9f7ea4 ("spi: cadence: Runtime pm adaptation") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-04-06spi: cadence: Fix some checkpatch warningsShubhrajyoti Datta
No functional change. Fixing some style related issues CHECK: multiple assignments should be avoided + new_ctrl_reg = ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); CHECK: Alignment should match open parenthesis +static void cdns_spi_config_clock_freq(struct spi_device *spi, + struct spi_transfer *transfer) CHECK: Please use a blank line after function/struct/union/enum declarations +} +static int cdns_prepare_message(struct spi_master *master, Signed-off-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-04-05spi: cadence: Return the error code for cdns_spi_suspend and cdns_spi_resumeShubhrajyoti Datta
Return the error code for cdns_spi_suspend and cdns_spi_resume. Also fixes a comment where which claims that the error code is returned. Signed-off-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-04-05spi: cadence: Remove the clock enable and disable from suspend and resumeShubhrajyoti Datta
Now that the clocks are enabled and disabled per transaction , remove the clock enable and disable from resume and suspend hooks. Signed-off-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-04-05spi: cadence: Runtime pm adaptationShubhrajyoti Datta
Currently the clocks are enabled at probe and disabled at remove. This patch moves the clock enable to the start of transaction and disables at the end. Signed-off-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-04-05spi: cadance: Fix the DocumentationShubhrajyoti Datta
cdns_spi_chipselect has parameter is_high however the comment describes it as is_on. Also fixes the below warning. drivers/spi/spi-cadence.c:182: warning: No description found for parameter 'is_high' drivers/spi/spi-cadence.c:182: warning: Excess function parameter 'is_on' description in 'cdns_spi_chipselect' Signed-off-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-04-05spi: cadence: Fix probe error handlingShubhrajyoti Datta
The clock disabling is missed out in some error cases at probe. Fix the same. Signed-off-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-04-05spi: cadence: Remove _MASK and _OFFSET suffixShubhrajyoti Datta
Remove the _MASK and _OFFSET from the macros. It improves readability, removes some checkpatch error for exceeding 80 chars and also prevents some linebreaks. Signed-off-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-04-05spi: cadence: Fix a check patch warningShubhrajyoti Datta
CHECK: Comparison to NULL could be written "!master" + if (master == NULL) Signed-off-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-01-05spi: cadence: use to_platform_device()Geliang Tang
Use to_platform_device() instead of open-coding it. Signed-off-by: Geliang Tang <geliangtang@163.com> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-12-08Merge remote-tracking branches 'spi/topic/atmel', 'spi/topic/cadence', ↵Mark Brown
'spi/topic/dw' and 'spi/topic/fsl-cpm' into spi-next
2014-11-28spi: cadence: Fix 3-to-8 mux modeLars-Peter Clausen
In 3-to-8 mux mode for the CS pins we need to set the PERI_SEL bit in the control register. Currently the driver never sets this bit even when configured for 3-to-8 mux mode. This patch adds code which sets the bit during device initialization when necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-11-28spi: cadence: Init HW after reading devicetree attributesPaul Cercueil
This will make it possible to use the settings specified in the devicetree to configure the hardware. Signed-off-by: Paul Cercueil <paul.cercueil@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-08-16spi: cadence: Remove .owner field for driverMichal Simek
There is no need to init .owner field. Based on the patch from Peter Griffin <peter.griffin@linaro.org> "mmc: remove .owner field for drivers using module_platform_driver" This patch removes the superflous .owner field for drivers which use the module_platform_driver API, as this is overriden in platform_driver_register anyway." Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2014-08-04Merge remote-tracking branches 'spi/topic/adi-v3', 'spi/topic/atmel', ↵Mark Brown
'spi/topic/cleanup' and 'spi/topic/davinci' into spi-next
2014-07-11spi: cadence: Configure SPI clock in the prepare_message() callbackLars-Peter Clausen
Currently the cadence SPI driver does the SPI clock configuration (setup CPOL and CPHA) in the prepare_transfer_hardware() callback. The prepare_transfer_hardware() callback is only called though when the controller transitions from a idle state to a non-idle state. Such a transitions happens when the message queue goes from empty to non-empty. If multiple messages from different SPI slaves with different clock settings are in the message queue the clock settings will not be properly updated when switching from one slave device to another. Instead do the updating of the clock configuration in the prepare_message() callback which will be called for each individual message. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@linaro.org>
2014-07-11spi: cadence: Make sure that clock polarity changes are appliedLars-Peter Clausen
It seems that the cadence SPI controller does not immediately change the clock polarity setting when writing the CR register. Instead the change is delayed until the next transfer starts. This happens after the chip select line has already been asserted. As a result the first transfer after a clock polarity change will generate spurious clock transitions which typically results in the SPI slave not being able to properly understand the message. Toggling the ER register seems to cause the SPI controller to apply the clock polarity changes, so implement this as a workaround to fix the issue. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@linaro.org>
2014-06-06spi: cadence: Make of_device_id array constJingoo Han
Make of_device_id array const, because all OF functions handle it as const. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2014-04-14spi: Add driver for Cadence SPI controllerHarini Katakam
Add driver for Cadence SPI controller. This is used in Xilinx Zynq. Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Mark Brown <broonie@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-02 23:02:37 +0000