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2016-11-29soc: fsl: add GUTS driver for QorIQ platformsyangbo lu
The global utilities block controls power management, I/O device enabling, power-onreset(POR) configuration monitoring, alternate function selection for multiplexed signals,and clock control. This patch adds a driver to manage and access global utilities block. Initially only reading SVR and registering soc device are supported. Other guts accesses, such as reading RCW, should eventually be moved into this driver as well. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-11-23soc/qman: Handle endianness of h/w descriptorsClaudiu Manoil
The hardware descriptors have big endian (BE) format. Provide proper endianness handling for the remaining descriptor fields, to ensure they are correctly accessed by non-BE CPUs too. Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-23soc: renesas: Identify SoC and register with the SoC busGeert Uytterhoeven
Identify the SoC type and revision, and register this information with the SoC bus, so it is available under /sys/devices/soc0/, and can be checked where needed using soc_device_match(). Identification is done using the Product Register or Common Chip Code Register, as declared in DT (PRR only for now), or using a hardcoded fallback if missing. Example: Detected Renesas R-Car Gen2 r8a7791 ES1.0 ... # cat /sys/devices/soc0/{machine,family,soc_id,revision} Koelsch R-Car Gen2 r8a7791 ES1.0 Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-11-23soc: renesas: rcar-sysc: add R8A7745 supportSergei Shtylyov
Add support for RZ/G1E (R8A7745) SoC power areas to the R-Car SYSC driver. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-11-23soc/qman: Clean up CGR CSCN target update operationsClaudiu Manoil
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-23soc/qman: Change remaining contextB into context_bClaudiu Manoil
There are multiple occurences of both contextB and context_b in different h/w descriptors, referring to the same descriptor field known as "Context B". Stick with the "context_b" naming, for obvious reasons including consistency (see also context_a). Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-23soc/qbman: Handle endianness of qm/bm_in/out()Claudiu Manoil
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-23soc/qman: Drop unused field from eqcr/dqrr descriptorsClaudiu Manoil
ORP ("Order Restoration Point") mechanism not supported. Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-23soc/qman: Fix accesses to fqid, cleanupClaudiu Manoil
Preventively mask every access to the 'fqid' h/w field, since it is defined as a 24-bit field, for every h/w descriptor. Add generic accessors for this field to ensure correct access. Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-23soc/qman: Remove unused struct qm_mcc* layoutsClaudiu Manoil
1. qm_mcc_querywq layout not used for now, so drop it; 2. queryfq, queryfq_np and alterfq are used only for accesses to the 'fqid' field, so replace these with a generic 'fq' layout. As a consequence, 'querycgr' turns into 'cgr' following the same reasoning above and for consistent naming. Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-23soc/qman: Remove redundant checks from qman_create_cgr()Claudiu Manoil
opts is checked redundantly. Move local_opts declaration inside its usage scope. Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-23soc/qman: test: Don't use dummy platform device for dma mappingClaudiu Manoil
Replace dummy platform device hack with a reference to a portal's platform device, in order to dma map the test frame for this small unit test. The 2 qman symbols need to be exported because this self test is a kernel module. Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-23soc/qman: Don't add a new platform device for dma mappingClaudiu Manoil
The qman portals are platform devices themselves, so they should handle dma mappings. Creating a dummy platform device in order to support dma mapping operations is not justified (and not portable). Instead, do the mapping against the first portal that has been initialised. Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-23soc/qman: test: Fix implementation of fd_cmp()Claudiu Manoil
This function must only return the truth value of whether two frame descriptors are different or not. It does NOT have to compute some obscure difference between fd fields and return it as an int, making sparse complain about type conversions in the process. Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-23soc/qman: Fix direct access to fd's addr_lo, use proper accesorClaudiu Manoil
Use the proper accessor to get the FD address. Accessing the internal field "addr_lo" directly is not portable and error prone. Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-23soc/qbman: Fix resource leak on portal probing error pathClaudiu Manoil
In case init_pcfg() returns with error the CI region must be unmapped too. Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-23soc/qman: Fix h/w resource cleanup error path handlingClaudiu Manoil
qman_query_fq*() may return other error codes apart from -ERANGE, in which cases the error handling done by the resource cleanup callers would be wrong. The patch fixes the handling of those cases, and cleans up related code inside the resource cleanup & release handlers (i.e. replace hardcoded fqid value with corresponding define). Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-23soc/qman: Replace of_get_property() with portable equivalentMadalin Bucur
Use arch portable of_property_read_u32() instead, which takes care of endianness conversions. Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-23soc/qman: Check ioremap return valueMadalin Bucur
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-22soc/fsl: fix spelling mistakes in critical error messagesColin Ian King
Trivial fix to spelling mistake "uncommited" to "uncommitted" in critical error messages. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-18Merge tag 'tegra-for-4.10-soc' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers soc: tegra: Core SoC changes for v4.10-rc1 This contains mostly cleanup and new feature work on the power management controller as well as the addition of a Kconfig symbol for the new Tegra186 (Parker) SoC generation. * tag 'tegra-for-4.10-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: pmc: Use consistent naming for PM domains soc/tegra: pmc: Remove genpd when adding provider fails soc/tegra: pmc: Check return code for pm_genpd_init() soc/tegra: pmc: Clean-up I/O rail error messages soc/tegra: pmc: Simplify IO rail bit handling soc/tegra: pmc: Guard against uninitialised PMC clock soc/tegra: pmc: Add I/O pad voltage support soc/tegra: pmc: Use consistent ordering of bit definitions soc/tegra: pmc: Correct type of variable for tegra_pmc_readl() soc/tegra: pmc: Use BIT macro for register field definition Signed-off-by: Olof Johansson <olof@lixom.net>
2016-11-18Merge tag 'tegra-for-4.10-mailbox' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers mailbox: Add Tegra HSP driver This contains the device tree bindings and a driver for the Tegra HSP, a hardware block that provides hardware synchronization primitives and is the foundation for inter-processor communication between CPU and BPMP. * tag 'tegra-for-4.10-mailbox' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: mailbox: tegra-hsp: Use after free in tegra_hsp_remove_doorbells() mailbox: Add Tegra HSP driver dt-bindings: mailbox: Add Tegra HSP binding soc/tegra: Add Tegra186 support Signed-off-by: Olof Johansson <olof@lixom.net>
2016-11-17Merge tag 'v4.9-next-soc' of https://github.com/mbgg/linux-mediatek into ↵Olof Johansson
next/drivers - prepare mtk-scpsys to for multi soc support - add support for mt2701 to mtk-scpsys * tag 'v4.9-next-soc' of https://github.com/mbgg/linux-mediatek: soc: mediatek: Add MT2701 scpsys driver soc: mediatek: Refine scpsys to support multiple platform Signed-off-by: Olof Johansson <olof@lixom.net>
2016-11-17Merge tag 'v4.10-rockchip-drivers1' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/drivers Changes to the power-domain driver including counter presets now being set by firmware on the rk3399, avoiding infite loops when powering on/off a domain and actually returning an error if power-domain addition fails. The last part requires usage of the (new in 4.9-rc1) pm_genpd_remove functionality as well. * tag 'v4.10-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: soc: rockchip: power-domain: Handle errors from of_genpd_add_provider_onecell soc: rockchip: power-domain: use pm_genpd_remove in error cleanup soc: rockchip: power-domain: avoid infinite loop soc: rockchip: power-domain: Don't (incorrectly) set rk3399 up/down counts Signed-off-by: Olof Johansson <olof@lixom.net>
2016-11-15soc/tegra: pmc: Use consistent naming for PM domainsThierry Reding
The various error messages refer to the PM domains as "power domain", "genpd" and "PM domain". That's confusing, so convert all error messages to use the most prominent: "PM domain". Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15soc/tegra: pmc: Remove genpd when adding provider failsJon Hunter
Commit 3fe577107ccf ("PM / Domains: Add support for removing PM domains") add support for removing PM domains. Update the Tegra PMC driver to remove PM domains if we fail to add a provider for the PM domain. Please note that the code under 'power_on_cleanup' label does not really belong in the clean-up error path for tegra_powergate_add(). To keep the error path simple, remove this label and move the associated code to where it needs to be invoked. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15soc/tegra: pmc: Check return code for pm_genpd_init()Jon Hunter
Commit 7eb231c337e0 ("PM / Domains: Convert pm_genpd_init() to return an error code") updated pm_genpd_init() to return an error code. Update the Tegra PMC driver to check the return value from pm_genpd_init() and handle any errors returned. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> [treding@nvidia.com: use pr_err() instead of dev_err()] Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15soc/tegra: pmc: Clean-up I/O rail error messagesThierry Reding
Use pr_err() instead of dev_err() when the pmc->dev field has not been initialized yet and add a few missing error messages as well as remove duplicate ones. Based on work by Jon Hunter <jonathanh@nvidia.com>. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15soc/tegra: pmc: Simplify IO rail bit handlingJon Hunter
The function tegra_io_rail_prepare() converts the IO rail ID into a bit position that is used to check the status and control the IO rail in the PMC registers. However, rather than converting to a bit position it is more useful to convert to a bit-mask because this is what is actually used. By doing so the BIT() marco only needs to be used once and we can use the IO_DPD_REQ_CODE_MASK when checking for erroneous rail IDs. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> [treding@nvidia.com: rebase and rename bit -> mask] Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15soc/tegra: pmc: Guard against uninitialised PMC clockJon Hunter
It is possible for the public functions, tegra_io_rail_power_on/off() to be called before the PMC device has been probed. If this happens then the pmc->clk member will not be initialised and the call to clk_get_rate() in tegra_io_rail_prepare() will return zero and lead to a divide-by-zero exception. The function clk_get_rate() will return zero if a NULl clk pointer is passed. Therefore, rather that checking if pmc->clk is initialised, fix this by checking the return value for clk_get_rate() to make sure it is not zero. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15soc/tegra: pmc: Add I/O pad voltage supportLaxman Dewangan
I/O pins on Tegra SoCs are grouped into so-called I/O pads. Each such pad can be used to control the common voltage signal level and power state of the pins in the given pad. I/O pads can be powered down even if the system is active, which can save power from that I/O interface. For SoC generations prior to Tegra124 the I/O pad voltage is automatically detected and hence the system software doesn't need to configure it. However, starting with Tegra210 the detection logic has been removed, so explicit control of the I/O pad voltage by system software is required. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15soc/tegra: pmc: Use consistent ordering of bit definitionsThierry Reding
Bit definitions are sorted in decreasing order by offset. Apply the same ordering to all definitions. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15soc/tegra: pmc: Correct type of variable for tegra_pmc_readl()Laxman Dewangan
The function tegra_pmc_readl() returns the u32 type data and hence change the data type of variable where this data is stored to u32 type. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15soc/tegra: pmc: Use BIT macro for register field definitionLaxman Dewangan
Use BIT macro for register field definition and make constant as U when using in shift operator like (3 << 30) to (3U << 30) Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15soc/tegra: Add Tegra186 supportJoseph Lo
The Tegra186 features a combination of Denver and Cortex-A57 CPU cores and a GPU based on the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU used for audio processing, hardware video encoders and decoders with multi-format support, ISP for image capture processing and BPMP for power management. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-11soc: rockchip: power-domain: Handle errors from of_genpd_add_provider_onecellTomeu Vizoso
It was a bit surprising that the device was reported to have probed just fine, but the provider hadn't been registered. So handle any errors when registering the provider and fail the probe accordingly. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Cc: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-11soc: rockchip: power-domain: use pm_genpd_remove in error cleanupHeiko Stuebner
The newly introduced pm_genpd_remove reverts the initialization done by pm_genpd_init and is necessary in the error path of the rockchip power-domain driver. Without it the driver will in the error case cleanup the devm-allocated structures including the elements referenced in the gpd_list thus making deactivation of unused domains (and probably later genpd accesses as well) fail by accessing invalid pointers. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-02soc: renesas: Add R-Car RST driverGeert Uytterhoeven
Add a driver for the Renesas R-Car Gen1 RESET/WDT and R-Car Gen2/Gen3 and RZ/G RST module. For now this driver just provides an API to obtain the state of the mode pins, as latched at reset time. As this is typically called from the probe function of a clock driver, which can run much earlier than any initcall, calling rcar_rst_read_mode_pins() just forces an early initialization of the driver. Despite the current simple and almost identical handling for all supported SoCs, the driver matches against SoC-specific compatible values, as the features provided by the hardware module differ a lot across the various SoC families and members. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2016-11-02soc: rockchip: power-domain: avoid infinite loopCaesar Wang
In some cases, we have met the infinite loop in rockchip_pmu_set_idle_request() or rockchip_do_pmu_set_power_domain(). As the crosbug.com/p/57351 reported, the boot hangs right after this [1.629163] bootconsole [uart8250] disabled [1.639286] [drm:drm_core_init] Initialized drm 1.1.0 20060810 [1.645926] [drm:drm_get_platform_dev] Initialized vgem 1.0.0 20120112.. [1.654558] iommu: Adding device ff8f0000.vop to group 0 [1.660569] iommu: Adding device ff900000.vop to group 1 <hang> This patch adds the error message and timeout to avoid infinite loop if it fails to get the ack. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-10-31soc: mediatek: Add MT2701 scpsys driverShunli Wang
Add scpsys driver for MT2701. mtk-scpsys now supports MT8173 (arm64) and MT2701 (arm). So it should be enabled on both arm64 and arm platforms. Signed-off-by: Shunli Wang <shunli.wang@mediatek.com> Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-10-31soc: mediatek: Refine scpsys to support multiple platformJames Liao
Refine scpsys driver common code to support multiple SoC / platform. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-10-17soc: renesas: rcar-sysc: add R8A7743 supportSergei Shtylyov
Add support for RZ/G1M (R8A7743) SoC power areas to the R-Car SYSC driver. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-10-16soc: rockchip: power-domain: Don't (incorrectly) set rk3399 up/down countsDouglas Anderson
On rk3288 it was important that powerdown and powerup counts for the CPU/GPU in the kernel because: * The power on default was crazy long. * We couldn't rely on the firmware to set this up because really this wasn't the firmware's job--the kernel was the only one that really cared about bringing up / down CPUs and the GPU and doing suspend / resume (which involves bringing up / down CPUs). On newer ARM systems (like rk3399) ARM Trusted Firmware is in charge of bringing up and down the CPUs and it really should be in charge of setting all these counts right. After all ATF is in charge of suspend / resume and CPU up / down. Let's get out of the way and let ATF do its job. A few other motivations for doing this: * Depending on another configuration (PMU_24M_EN_CFG) these counts can be either in 24M or 32k cycles. Thus, though ATF isn't really so involved in bringing up the GPU, ATF should probably manage the counts for everything so it can also manage the 24M / 32k choice. * It turns out that (right now) 24M mode is broken on rk3399 and not being used. That means that the count the kernel was programming in (24) was not 1 us (which it seems was intended) but was actually .75 ms * On rk3399 there are actually 2 separate registers for setting CPU up/down time plus 1 register for GPU up/down time. The curent kernel code actually was putting the register for the "little" cores in the "CPU" slot and the register for the "big" cores in the "GPU" slot. It was never initting the GPU counts. Note: this change assumes that ATF will actually set these values at boot, as I'm proposing in <http://crosreview.com/372381>. Signed-off-by: Douglas Anderson <dianders@chromium.org> [ATF change has landed] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-10-14Merge tag 'powerpc-4.9-2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull more powerpc updates from Michael Ellerman: "Some more powerpc updates for 4.9: Freescale updates from Scott Wood: - qbman support (a prerequisite for datapath drivers such as ethernet) - a PCI DMA fix+improvement - reset handler changes - more 8xx optimizations - some cleanups and fixes.' Fixes: - selftests/powerpc: Add missing binaries to .gitignores (Michael Ellerman) - selftests/powerpc: Fix build break caused by EXPORT_SYMBOL changes (Michael Ellerman) - powerpc/pseries: Fix stack corruption in htpe code (Laurent Dufour) - powerpc/64s: Fix power4_fixup_nap placement (Nicholas Piggin) - powerpc/64: Fix incorrect return value from __copy_tofrom_user (Paul Mackerras) - powerpc/mm/hash64: Fix might_have_hea() check (Michael Ellerman) Other: - MAINTAINERS: Remove myself from PA Semi entries (Olof Johansson) - MAINTAINERS: Drop separate pseries entry (Michael Ellerman) - MAINTAINERS: Update powerpc website & add selftests (Michael Ellerman): * tag 'powerpc-4.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (35 commits) powerpc/mm/hash64: Fix might_have_hea() check powerpc/64: Fix incorrect return value from __copy_tofrom_user powerpc/64s: Fix power4_fixup_nap placement powerpc/pseries: Fix stack corruption in htpe code selftests/powerpc: Fix build break caused by EXPORT_SYMBOL changes MAINTAINERS: Update powerpc website & add selftests MAINTAINERS: Drop separate pseries entry MAINTAINERS: Remove myself from PA Semi entries selftests/powerpc: Add missing binaries to .gitignores arch/powerpc: Add CONFIG_FSL_DPAA to corenetXX_smp_defconfig soc/qman: Add self-test for QMan driver soc/bman: Add self-test for BMan driver soc/fsl: Introduce DPAA 1.x QMan device driver soc/fsl: Introduce DPAA 1.x BMan device driver powerpc/8xx: make user addr DTLB miss the short path powerpc/8xx: Move additional DTLBMiss handlers out of exception area powerpc/8xx: use r3 to scratch CR in ITLBmiss soc/fsl/qe: fix gpio save_regs functions powerpc/8xx: add dedicated machine check handler powerpc/8xx: add system_reset_exception ...
2016-10-07Merge tag 'armsoc-drivers' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Arnd Bergmann: "Driver updates for ARM SoCs, including a couple of newly added drivers: - The Qualcomm external bus interface 2 (EBI2), used in some of their mobile phone chips for connecting flash memory, LCD displays or other peripherals - Secure monitor firmware for Amlogic SoCs, and an NVMEM driver for the EFUSE based on that firmware interface. - Perf support for the AppliedMicro X-Gene performance monitor unit - Reset driver for STMicroelectronics STM32 - Reset driver for SocioNext UniPhier SoCs Aside from these, there are minor updates to SoC-specific bus, clocksource, firmware, pinctrl, reset, rtc and pmic drivers" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (50 commits) bus: qcom-ebi2: depend on HAS_IOMEM pinctrl: mvebu: orion5x: Generalise mv88f5181l support for 88f5181 clk: mvebu: Add clk support for the orion5x SoC mv88f5181 dt-bindings: EXYNOS: Add Exynos5433 PMU compatible clocksource: exynos_mct: Add the support for ARM64 perf: xgene: Add APM X-Gene SoC Performance Monitoring Unit driver Documentation: Add documentation for APM X-Gene SoC PMU DTS binding MAINTAINERS: Add entry for APM X-Gene SoC PMU driver bus: qcom: add EBI2 driver bus: qcom: add EBI2 device tree bindings rtc: rtc-pm8xxx: Add support for pm8018 rtc nvmem: amlogic: Add Amlogic Meson EFUSE driver firmware: Amlogic: Add secure monitor driver soc: qcom: smd: Reset rx tail rather than tx memory: atmel-sdramc: fix a possible NULL dereference reset: hi6220: allow to compile test driver on other architectures reset: zynq: add driver Kconfig option reset: sunxi: add driver Kconfig option reset: stm32: add driver Kconfig option reset: socfpga: add driver Kconfig option ...
2016-09-25arch/powerpc: Add CONFIG_FSL_DPAA to corenetXX_smp_defconfigClaudiu Manoil
Enable the drivers on the powerpc arch. Signed-off-by: Roy Pledge <roy.pledge@nxp.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-09-25soc/qman: Add self-test for QMan driverClaudiu Manoil
Add self tests for the DPAA 1.x Queue Manager driver. The tests ensure that the driver can properly enqueue and dequeue to/from frame queues using the QMan portal infrastructure. Signed-off-by: Roy Pledge <roy.pledge@nxp.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-09-25soc/bman: Add self-test for BMan driverClaudiu Manoil
Add a self test for the DPAA 1.x Buffer Manager driver. This test ensures that the driver can properly acquire and release buffers using the BMan portal infrastructure. Signed-off-by: Roy Pledge <roy.pledge@nxp.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-09-25soc/fsl: Introduce DPAA 1.x QMan device driverClaudiu Manoil
This driver enables the Freescale DPAA 1.x Queue Manager block. QMan is a hardware accelerator that manages frame queues. It allows CPUs and other accelerators connected to the SoC datapath to enqueue and dequeue ethernet frames, thus providing the infrastructure for data exchange among CPUs and datapath accelerators. Signed-off-by: Roy Pledge <roy.pledge@nxp.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2016-09-25soc/fsl: Introduce DPAA 1.x BMan device driverClaudiu Manoil
This driver enables the Freescale DPAA 1.x Buffer Manager block. BMan is a hardware accelerator that manages buffer pools. It allows CPUs and other accelerators connected to the SoC datapath to acquire and release buffers during data processing. Signed-off-by: Roy Pledge <roy.pledge@nxp.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>