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Age	Commit message (Collapse)	Author
2018-01-16	soc: xilinx: Fix Kconfig alignment	Michal Simek
	Tabs should be used for alignment instead of spaces. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-16	soc: xilinx: xlnx_vcu: Use bitwise & rather than logical && on clkoutdiv	Gustavo A. R. Silva
	Currently clkoutdiv is being operated on by a logical && operator rather than a bitwise & operator. This looks incorrect as these should be bit flag operations. Addresses-Coverity-ID: 1463959 ("Logical vs. bitwise operator") Fixes: cee8113a295a ("soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver") Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Acked-by: Dhaval Shah <dshah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-16	soc: xilinx: xlnx_vcu: Depends on HAS_IOMEM for xlnx_vcu	Dhaval Shah
	xlnx_vcu driver uses devm_ioremap_nocache, which is included only when HAS_IOMEM is enabled. drivers/soc/xilinx/xlnx_vcu.o: In function `xvcu_probe': xlnx_vcu.c:(.text+0x116): undefined reference to `devm_ioremap_nocache' xlnx_vcu.c:(.text+0x1ae): undefined reference to `devm_ioremap_nocache' Signed-off-by: Dhaval Shah <dshah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-08	soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver	Dhaval Shah
	Xilinx ZYNQMP logicoreIP Init driver is based on the new LogiCoreIP design created. This driver provides the processing system and programmable logic isolation. Set the frequency based on the clock information get from the logicoreIP register set. Signed-off-by: Dhaval Shah <dshah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-08	soc: xilinx: Create folder structure for soc specific drivers	Michal Simek
	Create directory structure with Makefile/Kconfig for adding xilinx soc specific drivers. Signed-off-by: Michal Simek <michal.simek@xilinx.com>