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2018-06-11Merge tag 'armsoc-drivers' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Olof Johansson: "This contains platform-related driver updates for ARM and ARM64. Highlights: - ARM SCMI (System Control & Management Interface) driver cleanups - Hisilicon support for LPC bus w/ ACPI - Reset driver updates for several platforms: Uniphier, - Rockchip power domain bindings and hardware descriptions for several SoCs. - Tegra memory controller reset improvements" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (59 commits) ARM: tegra: fix compile-testing PCI host driver soc: rockchip: power-domain: add power domain support for px30 dt-bindings: power: add binding for px30 power domains dt-bindings: power: add PX30 SoCs header for power-domain soc: rockchip: power-domain: add power domain support for rk3228 dt-bindings: power: add binding for rk3228 power domains dt-bindings: power: add RK3228 SoCs header for power-domain soc: rockchip: power-domain: add power domain support for rk3128 dt-bindings: power: add binding for rk3128 power domains dt-bindings: power: add RK3128 SoCs header for power-domain soc: rockchip: power-domain: add power domain support for rk3036 dt-bindings: power: add binding for rk3036 power domains dt-bindings: power: add RK3036 SoCs header for power-domain dt-bindings: memory: tegra: Remove Tegra114 SATA and AFI reset definitions memory: tegra: Remove Tegra114 SATA and AFI reset definitions memory: tegra: Register SMMU after MC driver became ready soc: mediatek: remove unneeded semicolon soc: mediatek: add a fixed wait for SRAM stable soc: mediatek: introduce a CAPS flag for scp_domain_data soc: mediatek: reuse regmap_read_poll_timeout helpers ...
2018-06-09Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This time we have a good set of changes to the core framework that do some general cleanups, but nothing too major. The majority of the diff goes to two SoCs, Actions Semi and Qualcomm. A brand new driver is introduced for Actions Semi so it takes up some lines to add all the different types, and the Qualcomm diff is there because we add support for two SoCs and it's quite a bit of data. Otherwise the big driver updates are on TI Davinci and Amlogic platforms. And then the long tail of driver updates for various fixes and stuff follows after that. Core: - debugfs cleanups removing error checking and an unused provider API - Removal of a clk init typedef that isn't used - Usage of match_string() to simplify parent string name matching - OF clk helpers moved to their own file (linux/of_clk.h) - Make clk warnings more readable across kernel versions New Drivers: - Qualcomm SDM845 GCC and Video clk controllers - Qualcomm MSM8998 GCC - Actions Semi S900 SoC support - Nuvoton npcm750 microcontroller clks - Amlogic axg AO clock controller Removed Drivers: - Deprecated Rockchip clk-gate driver Updates: - debugfs functions stopped checking return values - Support for the MSIOF module clocks on Rensas R-Car M3-N - Support for the new Rensas RZ/G1C and R-Car E3 SoCs - Qualcomm GDSC, RCG, and PLL updates for clk changes in new SoCs - Berlin and Amlogic SPDX tagging - Usage of of_clk_get_parent_count() in more places - Proper implementation of the CDEV1/2 clocks on Tegra20 - Allwinner H6 PRCM clock support and R40 EMAC support - Add critical flag to meson8b's fdiv2 as temporary fixup for ethernet - Round closest support for meson's mpll driver - Support for meson8b nand clocks and gxbb video decoder clocks - Mediatek mali clks - STM32MP1 fixes - Uniphier LD11/LD20 stream demux system clock" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits) clk: qcom: Export clk_fabia_pll_configure() clk: bcm: Update and add Stingray clock entries dt-bindings: clk: Update Stingray binding doc clk-si544: Properly round requested frequency to nearest match clk: ingenic: jz4770: Add 150us delay after enabling VPU clock clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle clk: ingenic: jz4770: Change OTG from custom to standard gated clock clk: ingenic: Support specifying "wait for clock stable" delay clk: ingenic: Add support for clocks whose gate bit is inverted clk: use match_string() helper clk: bcm2835: use match_string() helper clk: Return void from debug_init op clk: remove clk_debugfs_add_file() clk: tegra: no need to check return value of debugfs_create functions clk: davinci: no need to check return value of debugfs_create functions clk: bcm2835: no need to check return value of debugfs_create functions clk: no need to check return value of debugfs_create functions clk: imx6: add EPIT clock support clk: mvebu: use correct bit for 98DX3236 NAND ...
2018-06-06treewide: Use struct_size() for devm_kmalloc() and friendsKees Cook
Replaces open-coded struct size calculations with struct_size() for devm_*, f2fs_*, and sock_* allocations. Automatically generated (and manually adjusted) from the following Coccinelle script: // Direct reference to struct field. @@ identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc"; expression HANDLE; expression GFP; identifier VAR, ELEMENT; expression COUNT; @@ - alloc(HANDLE, sizeof(*VAR) + COUNT * sizeof(*VAR->ELEMENT), GFP) + alloc(HANDLE, struct_size(VAR, ELEMENT, COUNT), GFP) // mr = kzalloc(sizeof(*mr) + m * sizeof(mr->map[0]), GFP_KERNEL); @@ identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc"; expression HANDLE; expression GFP; identifier VAR, ELEMENT; expression COUNT; @@ - alloc(HANDLE, sizeof(*VAR) + COUNT * sizeof(VAR->ELEMENT[0]), GFP) + alloc(HANDLE, struct_size(VAR, ELEMENT, COUNT), GFP) // Same pattern, but can't trivially locate the trailing element name, // or variable name. @@ identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc"; expression HANDLE; expression GFP; expression SOMETHING, COUNT, ELEMENT; @@ - alloc(HANDLE, sizeof(SOMETHING) + COUNT * sizeof(ELEMENT), GFP) + alloc(HANDLE, CHECKME_struct_size(&SOMETHING, ELEMENT, COUNT), GFP) Signed-off-by: Kees Cook <keescook@chromium.org>
2018-05-23soc: rockchip: power-domain: add power domain support for px30Finley Xiao
This driver is modified to support PX30 SoC. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-05-23soc: rockchip: power-domain: add power domain support for rk3228Elaine Zhang
This driver is modified to support RK3228 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-05-23soc: rockchip: power-domain: add power domain support for rk3128Elaine Zhang
This driver is modified to support RK3128 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-05-23soc: rockchip: power-domain: add power domain support for rk3036Caesar Wang
This driver is modified to support RK3036 SoC. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-05-14soc: rockchip: power-domain: Fix wrong value when power up pd with writemaskFinley Xiao
Solve the pd could only ever turn off but never turn them on again, if the pd registers have the writemask bits. So far this affects the rk3328 only. Fixes: 79bb17ce8edb ("soc: rockchip: power-domain: Support domain control in hiword-registers") Cc: stable@vger.kernel.org Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-05-02soc: rockchip: power-domain: Use of_clk_get_parent_count() instead of open ↵Geert Uytterhoeven
coding As of_clk_get_parent_count() returns zero on failure, while of_count_phandle_with_args() might return a negative error code, this also fixes the issue of possibly using a negative number in the allocation below. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-05soc: rockchip: power-domain: Add a sanity check on pd->num_clksJeffy Chen
The of_count_phandle_with_args() can fail and return error(for example, rk3399 pd_vio doesn't have clocks). That would break the pd probe. Add a sanity check on pd->num_clks to avoid that. Fixes: 65084121d59d ("soc: rockchip: power-domain: use clk_bulk APIs") Reported-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Tested-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-03-05soc: rockchip: power-domain: use clk_bulk APIsJeffy Chen
Use clk_bulk APIs, and also add error handling for clk enable. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-03-05soc: rockchip: disable jtag switching for RK3128 SoCsXiao Yao
Disable IO function switching between sdmmc and jtag for RK3128 SoCs. Signed-off-by: Xiao Yao <xiaoyao@rock-chips.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-02-12soc: rockchip: disable jtag switching for RK3228/RK3229 SoCsShawn Lin
Disable IO function switching between sdmmc and jtag for RK3228 and RK3229 SoCs. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-11-08soc: rockchip: power-domain: Use GENPD_FLAG_ACTIVE_WAKEUPGeert Uytterhoeven
Set the newly introduced GENPD_FLAG_ACTIVE_WAKEUP, which allows to remove the driver's own flag-based callback. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2017-07-20soc: rockchip: power-domain: add power domain support for rk3366Elaine Zhang
This driver is modified to support RK3366 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-07-16soc: rockchip: disable jtag switching for RK3328 SocShawn Lin
Disable IO function switching between sdmmc and jtag for RK3328 Soc. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-06soc: rockchip: add driver handling grf setupHeiko Stuebner
The General Register Files are an area of registers containing a lot of single-bit settings for numerous components as well full components like usbphy control. Therefore all used components are accessed via the syscon provided by the grf nodes or from the sub-devices created through the simple-mfd created from the grf node. Some settings are not used by anything but will need to be set up according to expectations on the kernel side. Best example is the force_jtag setting, which defaults to on and results in the soc switching the pin-outputs between jtag and sdmmc automatically depending on the card-detect status. This conflicts heavily with how the dw_mmc driver expects to do its work and also with the clock-controller, which has most likely deactivated the jtag clock due to it being unused. So far the handling of this setting was living in the mach-rockchip code for the arm32-based rk3288 but that of course doesn't work for arm64 socs and would also look ugly for further arm32 socs. Also always disabling this setting is quite specific to linux and its subsystems, other operating systems might prefer other settings, so that the bootloader cannot really set a sane default for all. So introduce a top-level driver for the grf that handles these settings that need to be a certain way but nobody cares about. Other needed settings might surface in the future and can then be added here, but only as a last option. Ideally general GRF settings should be handled in the driver needing them. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2017-01-05soc: rockchip: power-domain: add power domain support for rk3328Elaine Zhang
The rk3328 uses the newly introduced support for power-domain control in hiword-mask registers. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-05soc: rockchip: power-domain: Support domain control in hiword-registersElaine Zhang
New Rockchips SoCs may have their power-domain control in registers using a writemask-based access scheme (upper 16bit being the write mask). So add a DOMAIN_M type and handle this case accordingly. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-11soc: rockchip: power-domain: Handle errors from of_genpd_add_provider_onecellTomeu Vizoso
It was a bit surprising that the device was reported to have probed just fine, but the provider hadn't been registered. So handle any errors when registering the provider and fail the probe accordingly. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Cc: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-11soc: rockchip: power-domain: use pm_genpd_remove in error cleanupHeiko Stuebner
The newly introduced pm_genpd_remove reverts the initialization done by pm_genpd_init and is necessary in the error path of the rockchip power-domain driver. Without it the driver will in the error case cleanup the devm-allocated structures including the elements referenced in the gpd_list thus making deactivation of unused domains (and probably later genpd accesses as well) fail by accessing invalid pointers. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-02soc: rockchip: power-domain: avoid infinite loopCaesar Wang
In some cases, we have met the infinite loop in rockchip_pmu_set_idle_request() or rockchip_do_pmu_set_power_domain(). As the crosbug.com/p/57351 reported, the boot hangs right after this [1.629163] bootconsole [uart8250] disabled [1.639286] [drm:drm_core_init] Initialized drm 1.1.0 20060810 [1.645926] [drm:drm_get_platform_dev] Initialized vgem 1.0.0 20120112.. [1.654558] iommu: Adding device ff8f0000.vop to group 0 [1.660569] iommu: Adding device ff900000.vop to group 1 <hang> This patch adds the error message and timeout to avoid infinite loop if it fails to get the ack. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-10-16soc: rockchip: power-domain: Don't (incorrectly) set rk3399 up/down countsDouglas Anderson
On rk3288 it was important that powerdown and powerup counts for the CPU/GPU in the kernel because: * The power on default was crazy long. * We couldn't rely on the firmware to set this up because really this wasn't the firmware's job--the kernel was the only one that really cared about bringing up / down CPUs and the GPU and doing suspend / resume (which involves bringing up / down CPUs). On newer ARM systems (like rk3399) ARM Trusted Firmware is in charge of bringing up and down the CPUs and it really should be in charge of setting all these counts right. After all ATF is in charge of suspend / resume and CPU up / down. Let's get out of the way and let ATF do its job. A few other motivations for doing this: * Depending on another configuration (PMU_24M_EN_CFG) these counts can be either in 24M or 32k cycles. Thus, though ATF isn't really so involved in bringing up the GPU, ATF should probably manage the counts for everything so it can also manage the 24M / 32k choice. * It turns out that (right now) 24M mode is broken on rk3399 and not being used. That means that the count the kernel was programming in (24) was not 1 us (which it seems was intended) but was actually .75 ms * On rk3399 there are actually 2 separate registers for setting CPU up/down time plus 1 register for GPU up/down time. The curent kernel code actually was putting the register for the "little" cores in the "CPU" slot and the register for the "big" cores in the "GPU" slot. It was never initting the GPU counts. Note: this change assumes that ATF will actually set these values at boot, as I'm proposing in <http://crosreview.com/372381>. Signed-off-by: Douglas Anderson <dianders@chromium.org> [ATF change has landed] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-19soc: rockchip: support active_wakeup for rockchip power-domainsElaine Zhang
Register gpd_dev_ops.active_wakeup function to support keep power during suspend state. And add flag to each power domain to decide whether keep power during suspend or not. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-21soc: rockchip: power-domain: support qos save and restoreElaine Zhang
support qos save and restore when power domain on/off. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-12soc: rockchip: power-domain: check the existing of regmapShawn Lin
Check return value of syscon_node_to_regmap for rockchip_pm_domain_probe. If err value is returned, probe procedure should abort. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-28soc: rockchip: power-domain: Modify power domain driver for rk3399Elaine Zhang
This driver is modified to support RK3399 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> [small indentation fixups] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-28soc: rockchip: power-domain: add support for sub-power domainsElaine Zhang
This patch adds support for making one power domain a sub-domain of other domain. This is useful for modeling power dependences, which needs to have more than one power domain enabled to be operational. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> [restructured error handling in subdomain-addition] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-28soc: rockchip: power-domain: allow domains only handling idle requestsElaine Zhang
On some Rockchip SoC there exist child-domains only handling their idle state with the actual power-state handled by a (shared) parent- domain. So allow such types of domains. For them, we can determine their state (on/off) by checking the inverse idle-state instead. There exist one special case if both idle as well power handling were set as not present, but as the domain-data is defined in the code itself, we can expect the reasonable developer to define them in a correct way, without adding more checks. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-28soc: rockchip: power-domain: make idle handling optionalElaine Zhang
Not all new socs need to handle idle states on domain state changes, so add the possibility to make them optional. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-02soc: rockchip: power-domain: fix err handle while probingShawn Lin
If we fail to probe the driver, we should not directly break from the for_each_available_child_of_node since it calls of_node_get while iterating. This patch add of_node_put to fix the unbalanced call pair. Fixes: 7c696693a4f5 ("soc: rockchip: power-domain: Add power domain driver") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-25soc: rockchip: power-domain: Modify power domain driver for rk3368zhangqing
This driver is modified to support RK3368 SoC. Signed-off-by: zhangqing <zhangqing@rock-chips.com> Reviewed-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-10-16soc: rockchip: power-domain: don't try to print the clock name in error caseHeiko Stuebner
When we never got the the clock-reference, i.e. when IS_ERR(clk) is true, don't try to print the clock name via %pC as this of course produces a null-pointer-dereference in __clk_get_name(). Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Caesar Wang <wxt@rock-chips.com>
2015-10-11soc: rockchip: Restrict to ARCH_ROCKCHIPThierry Reding
By definition this directory contains drivers that are specific to the Rockchip architecture. All Kconfig options should therefore depend on ARCH_ROCKCHIP to avoid exposing these symbols on other architectures. For example, this options currently shows up as new when doing an incremental build on PowerPC. Signed-off-by: Thierry Reding <treding@nvidia.com> [add COMPILE_TEST alternative condition] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-10-06soc: rockchip: power-domain: Add power domain driverCaesar Wang
This driver is found on RK3288 SoCs. In order to meet high performance and low power requirements, a power management unit is designed or saving power when RK3288 in low power mode. The RK3288 PMU is dedicated for managing the power of the whole chip. PMU can work in the Low Power Mode by setting bit[0] of PMU_PWRMODE_CON register. After setting the register, PMU would enter the Low Power mode. In the low power mode, pmu will auto power on/off the specified power domain, send idle req to specified power domain, shut down/up pll and so on. All of above are configurable by setting corresponding registers. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> [replace dsb() with dsb(sy) for arm64 buildability; sy is the default, so no functional change; adapt to per-user clocks in genpd] Signed-off-by: Heiko Stuebner <heiko@sntech.de>