| Age | Commit message (Collapse) | Author |
|---|
|
Refactor idt82p33_xfer and use i2c_master_send for write operation.
Because some I2C controllers are only working with single-burst write
transaction.
Signed-off-by: Min Li <min.li.xe@renesas.com>
Acked-by: Richard Cochran <richardcochran@gmail.com>
Link: https://lore.kernel.org/r/1604634729-24960-2-git-send-email-min.li.xe@renesas.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
|
Add idt82p33_adjphase() to support PHC write phase mode.
Signed-off-by: Min Li <min.li.xe@renesas.com>
Acked-by: Richard Cochran <richardcochran@gmail.com>
Link: https://lore.kernel.org/r/1604634729-24960-1-git-send-email-min.li.xe@renesas.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
|
The IDT 82P33 Synchronization Management Unit (SMU) family provides
tools to manage timing references, clock sources and
timing paths for IEEE 1588 / Precision Time Protocol (PTP) and
Synchronous Ethernet (SyncE) based clocks. The device supports up
to three independent timing paths that control: PTP clock synthesis;
SyncE clock generation; and general purpose frequency translation.
The device supports physical layer timing with Digital PLLs (DPLLs)
and it supports packet based timing with Digitally Controlled
Oscillators (DCOs). This patch adds support for ptp clock based on
the device.
Changes since v1:
- As suggested by Richard Cochran:
1. Replace _mask_bit_count with the existing hweight8
2. Prefix all functions with idt82p33
3. Fix white space issues in Kconfig and Makefile
4. Remove forward declaration
5. Use adjfine instead of adjfreq for better resolution
- As suggested by David Miller:
1. Replace CHAN_INIT macro with a static function
idt82p33_channel_init
2. Employ reverse christmas tree ordering for local
variables
3. Fix indentation problem by appropriate number of
TAB then SPACE character
Signed-off-by: Min Li <min.li.xe@renesas.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
