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2019-05-21treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13Thomas Gleixner
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details [based] [from] [clk] [highbank] [c] you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 355 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190519154041.837383322@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-21treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 4Thomas Gleixner
Based on 1 normalized pattern(s): licensed under gplv2 or later extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 118 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190519154040.961286471@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner
Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-21treewide: Add SPDX license identifier for more missed filesThomas Gleixner
Add SPDX license identifiers to all files which: - Have no license information of any form - Have MODULE_LICENCE("GPL*") inside which was used in the initial scan/conversion to ignore the file These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-14Merge tag 'mfd-next-5.2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd Pull MFD updates from Lee Jones: "Core Framework: - Document (kerneldoc) core mfd_add_devices() API New Drivers: - Altera SOCFPGA System Manager - Maxim MAX77650/77651 PMIC - Maxim MAX77663 PMIC - ST Multi-Function eXpander (STMFX) New Device Support: - LEDs support in Intel Cherry Trail Whiskey Cove PMIC - RTC support in SAMSUNG Electronics S2MPA01 PMIC - SAM9X60 support in Atmel HLCDC (High-end LCD Controller) - USB X-Powers AXP 8xx PMICs - Integrated Sensor Hub (ISH) in ChromeOS EC - USB PD Logger in ChromeOS EC - AXP223 in X-Powers AXP series PMICs - Power Supply in X-Powers AXP 803 PMICs - Comet Lake in Intel Low Power Subsystem - Fingerprint MCU in ChromeOS EC - Touchpad MCU in ChromeOS EC - Move TI LM3532 support to LED New Functionality: - max77650, max77620: Add/extend DT support - max77620 power-off - syscon clocking - croc_ec host sleep event Fix-ups: - Trivial; Formatting, spelling, etc; Kconfig, sec-core, ab8500-debugfs - Remove unused functionality; rk808, da9063-* - SPDX conversion; da9063-*, atmel-*, - Adapt/add new register definitions; cs47l35-tables, cs47l90-tables, imx6q-iomuxc-gpr - Fix-up DT bindings; ti-lmu, cirrus,lochnagar - Simply obtaining driver data; ssbi, t7l66xb, tc6387xb, tc6393xb Bug Fixes: - Fix incorrect defined values; max77620, da9063 - Fix device initialisation; twl6040 - Reset device on init; intel-lpss - Fix build warnings when !OF; sun6i-prcm - Register OF match tables; tps65912-spi - Fix DMI matching; intel_quark_i2c_gpio" * tag 'mfd-next-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (65 commits) mfd: Use dev_get_drvdata() directly mfd: cros_ec: Instantiate properly CrOS Touchpad MCU device mfd: cros_ec: Instantiate properly CrOS FP MCU device mfd: cros_ec: Update the EC feature codes mfd: intel-lpss: Add Intel Comet Lake PCI IDs mfd: lochnagar: Add links to binding docs for sound and hwmon mfd: ab8500-debugfs: Fix a typo ("deubgfs") mfd: imx6sx: Add MQS register definition for iomuxc gpr dt-bindings: mfd: LMU: Fix lm3632 dt binding example mfd: intel_quark_i2c_gpio: Adjust IOT2000 matching mfd: da9063: Fix OTP control register names to match datasheets for DA9063/63L mfd: tps65912-spi: Add missing of table registration mfd: axp20x: Add USB power supply mfd cell to AXP803 mfd: sun6i-prcm: Fix build warning for non-OF configurations mfd: intel-lpss: Set the device in reset state when init platform/chrome: Add support for v1 of host sleep event mfd: cros_ec: Add host_sleep_event_v1 command mfd: cros_ec: Instantiate the CrOS USB PD logger driver mfd: cs47l90: Make DAC_AEC_CONTROL_2 readable mfd: cs47l35: Make DAC_AEC_CONTROL_2 readable ...
2019-05-13pinctrl: stmfx: Fix 'warn: bitwise AND condition is false here'Lee Jones
drivers/pinctrl/pinctrl-stmfx.c:441 stmfx_pinctrl_irq_set_type() warn: bitwise AND condition is false here Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-05-13pinctrl: stmfx: Fix 'warn: unsigned <VAR> is never less than zero'Lee Jones
smatch warnings: drivers/pinctrl/pinctrl-stmfx.c:225 stmfx_pinconf_get() warn: unsigned 'dir' is never less than zero. drivers/pinctrl/pinctrl-stmfx.c:228 stmfx_pinconf_get() warn: unsigned 'type' is never less than zero. drivers/pinctrl/pinctrl-stmfx.c:231 stmfx_pinconf_get() warn: unsigned 'pupd' is never less than zero. Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-05-11Merge tag 'gpio-v5.2-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull gpio updates from Linus Walleij: "This is the bulk of the GPIO changes for the v5.2 kernel cycle. A bit later than usual because I was ironing out my own mistakes. I'm holding some stuff back for the next kernel as a result, and this should be a healthy and well tested batch. Core changes: - The gpiolib MMIO driver has been enhanced to handle two direction registers, i.e. one register to set lines as input and one register to set lines as output. It turns out some silicon engineer thinks the ability to configure a line as input and output at the same time makes sense, this can be debated but includes a lot of analog electronics reasoning, and the registers are there and need to be handled consistently. Unsurprisingly, we enforce the lines to be either inputs or outputs in such schemes. - Send in the proper argument value to .set_config() dispatched to the pin control subsystem. Nobody used it before, now someone does, so fix it to work as expected. - The ACPI gpiolib portions can now handle pin bias setting (pull up or pull down). This has been in the ACPI spec for years and we finally have it properly integrated with Linux GPIOs. It was based on an observation from Andy Schevchenko that Thomas Petazzoni's changes to the core for biasing the PCA950x GPIO expander actually happen to fit hand-in-glove with what the ACPI core needed. Such nice synergies happen sometimes. New drivers: - A new driver for the Mellanox BlueField GPIO controller. This is using 64bit MMIO registers and can configure lines as inputs and outputs at the same time and after improving the MMIO library we handle it just fine. Interesting. - A new IXP4xx proper gpiochip driver with hierarchical interrupts should be coming in from the ARM SoC tree as well. Driver enhancements: - The PCA053x driver handles the CAT9554 GPIO expander. - The PCA053x driver handles the NXP PCAL6416 GPIO expander. - Wake-up support on PCA053x GPIO lines. - OMAP now does a nice asynchronous IRQ handling on wake-ups by letting everything wake up on edges, and this makes runtime PM work as expected too. Misc: - Several cleanups such as devres fixes. - Get rid of some languager comstructs that cause problems when compiling with LLVMs clang. - Documentation review and update" * tag 'gpio-v5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (85 commits) gpio: Update documentation docs: gpio: convert docs to ReST and rename to *.rst gpio: sch: Remove write-only core_base gpio: pxa: Make two symbols static gpiolib: acpi: Respect pin bias setting gpiolib: acpi: Add acpi_gpio_update_gpiod_lookup_flags() helper gpiolib: acpi: Set pin value, based on bias, more accurately gpiolib: acpi: Change type of dflags gpiolib: Introduce GPIO_LOOKUP_FLAGS_DEFAULT gpiolib: Make use of enum gpio_lookup_flags consistent gpiolib: Indent entry values of enum gpio_lookup_flags gpio: pca953x: add support for pca6416 dt-bindings: gpio: pca953x: document the nxp,pca6416 gpio: pca953x: add pcal6416 to the of_device_id table gpio: gpio-omap: Remove conditional pm_runtime handling for GPIO interrupts gpio: gpio-omap: configure edge detection for level IRQs for idle wakeup tracing: stop making gpio tracing configurable gpio: pca953x: Configure wake-up path when wake-up is enabled gpio: of: Optimize quirk checks gpio: mmio: Drop bgpio_dir_inverted ...
2019-05-10pinctrl: Kconfig: Fix STMFX GPIO expander Pinctrl/GPIO driver dependenciesAmelie Delaunay
module_i2c_driver and pinconf_generic_dt_node_to_map_pin are undeclared if CONFIG_I2C and CONFIG_OF are not enabled. Fixes: 1490d9f841b1 ("pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driver") Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-05-10pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driverAmelie Delaunay
This patch adds pinctrl/GPIO driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander. STMFX is an I2C slave controller, offering up to 24 GPIOs. The driver relies on generic pin config interface to configure the GPIOs. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-05-07pinctrl: mcp23s08: Do not complain about unsupported paramsJan Kundrát
It is expected that some of these operations won't work on each and every HW. Previously, even a simple `cat /sys/kernel/debug/pinctrl/spi1.1/pinconf-pins` caused excessive dmesg output. Signed-off-by: Jan Kundrát <jan.kundrat@cesnet.cz> Cc: Phil Reid <preid@electromag.com.au> Cc: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-03Merge tag 'intel-pinctrl-v5.2-1' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.2-1 Non-critical fixes for Intel Baytrail and Intel Cedarfork. Couple of fixes for all pinctrl-intel based drivers with regard to IRQ handling, i.e. moving PM calls to noirq level to avoid IRQ lose and restore ownership of pins to prevent IRQ masking side effect. The following is an automated git shortlog grouped by driver: baytrail: - Fix potential NULL pointer dereference cedarfork: - Update pin names according to v1.13c intel: - Increase readability of intel_gpio_update_pad_mode() - Retain HOSTSW_OWN for requested gpio pin - move gpio suspend/resume to noirq phase
2019-05-03pinctrl: Rework Kconfig dependency for BM1880 pinctrl driverManivannan Sadhasivam
Make the BM1880 SoC pinctrl driver depend on COMPILE_TEST to get compiler test coverage and also select this driver by default for ARCH_BITMAIN platform. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-03pinctrl: Add pinctrl support for BM1880 SoCManivannan Sadhasivam
Add pinctrl support for Bitmain BM1880 SoC. The driver only handles pinmuxing as the SoC is not capable of handling pinconf. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-03pinctrl: stm32: check irq controller availability at probeFabien Dessenne
It is not guaranteed that the IRQ controller driver is probed before the pin controller driver gets probed. Considering this, check for the irq domain availability during probe and return EPROBE_DEFER if needed. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-03pinctrl: mediatek: Add MT8516 Pinctrl driverFabien Parent
This commit adds the pinctrl driver for the MediaTek's MT8516 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Acked-by: Sean Wang <sean.wang@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-03pinctrl: zte: fix leaked of_node referencesWen Yang
The call to of_parse_phandle returns a node pointer with refcount incremented thus it must be explicitly decremented after the last usage. Detected by coccinelle with the following warnings: ./drivers/pinctrl/zte/pinctrl-zx.c:415:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 407, but without a corresponding object release within this function. ./drivers/pinctrl/zte/pinctrl-zx.c:422:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 407, but without a corresponding object release within this function. ./drivers/pinctrl/zte/pinctrl-zx.c:436:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 407, but without a corresponding object release within this function. ./drivers/pinctrl/zte/pinctrl-zx.c:444:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 407, but without a corresponding object release within this function. ./drivers/pinctrl/zte/pinctrl-zx.c:448:1-7: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 407, but without a corresponding object release within this function. Signed-off-by: Wen Yang <wen.yang99@zte.com.cn> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Jun Nie <jun.nie@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Cc: linux-kernel@vger.kernel.org Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-28pinctrl: intel: Increase readability of intel_gpio_update_pad_mode()Andy Shevchenko
We better to use usual pattern for read-modify-update, than doing some operations in definition block. No functional change. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-04-28pinctrl: intel: Retain HOSTSW_OWN for requested gpio pinChris Chiu
The touchpad of the ASUS laptops E403NA, X540NA, X541NA are not responsive after suspend/resume. The following error message shows after resume. i2c_hid i2c-ELAN1200:00: failed to reset device. On these laptops, the touchpad interrupt is connected via a GPIO pin which is controlled by Intel pinctrl. After system resumes, the GPIO is in ACPI mode and no longer works as an IRQ. This commit saves the HOSTSW_OWN value during suspend, make sure the HOSTSW_OWN mode remains the same after resume. Signed-off-by: Chris Chiu <chiu@endlessm.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-04-23pinctrl: pistachio: fix leaked of_node referencesWen Yang
The call to of_get_child_by_name returns a node pointer with refcount incremented thus it must be explicitly decremented after the last usage. Detected by coccinelle with the following warnings: ./drivers/pinctrl/pinctrl-pistachio.c:1422:1-7: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 1360, but without a corresponding object release within this function. Signed-off-by: Wen Yang <wen.yang99@zte.com.cn> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23pinctrl: sunxi: Support I/O bias voltage setting on H6Ondrej Jirman
H6 SoC has a "pio group withstand voltage mode" register (datasheet description), that needs to be used to select either 1.8V or 3.3V I/O mode, based on what voltage is powering the respective pin banks and is thus used for I/O signals. Add support for configuring this register according to the voltage of the pin bank regulator (if enabled). This is similar to the support for I/O bias voltage setting patch for A80 and the same concerns apply. See: commit 402bfb3c1352 ("Support I/O bias voltage setting on A80") Signed-off-by: Ondrej Jirman <megous@megous.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23pinctrl: sunxi: Prepare for alternative bias voltage setting methodsOndrej Jirman
H6 has a different I/O voltage bias setting method than A80. Prepare existing code for using alternative bias voltage setting methods. Signed-off-by: Ondrej Jirman <megous@megous.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23pinctrl: st: fix leaked of_node referencesWen Yang
The call to of_get_child_by_name returns a node pointer with refcount incremented thus it must be explicitly decremented after the last usage. Detected by coccinelle with the following warnings: ./drivers/pinctrl/pinctrl-st.c:1188:3-9: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 1175, but without a corresponding object release within this function. ./drivers/pinctrl/pinctrl-st.c:1188:3-9: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 1175, but without a corresponding object release within this function. ./drivers/pinctrl/pinctrl-st.c:1199:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 1175, but without a corresponding object release within this function. ./drivers/pinctrl/pinctrl-st.c:1199:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 1175, but without a corresponding object release within this function. Signed-off-by: Wen Yang <wen.yang99@zte.com.cn> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Cc: linux-kernel@vger.kernel.org (open list) Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23pinctrl: samsung: fix leaked of_node referencesWen Yang
The call to of_find_compatible_node returns a node pointer with refcount incremented thus it must be explicitly decremented after the last usage. Detected by coccinelle with the following warnings: ./drivers/pinctrl/samsung/pinctrl-exynos-arm.c:76:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 66, but without a corresponding object release within this function. ./drivers/pinctrl/samsung/pinctrl-exynos-arm.c:82:1-7: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 66, but without a corresponding object release within this function. Signed-off-by: Wen Yang <wen.yang99@zte.com.cn> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: linux-samsung-soc@vger.kernel.org Cc: linux-gpio@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23pinctrl: stm32: align stm32mp157 pin namesAlexandre Torgue
Align pins names with names provided in official stm32mp157 datasheet available on st.com. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23pinctrl: stm32: add package information for stm32mp157cAlexandre Torgue
This patch adds four new packages support for stm32mp157c die: STM32MP_PKG_AA: LFBGA448 (18*18), 176 IOs STM32MP_PKG_AB: LFBGA354 (16*16), 98 IOs STM32MP_PKG_AC: TFBGA361 (12*12), 148 IOs STM32MP_PKG_AD: TFBGA257 (10*10), 98 IOs Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23pinctrl: stm32: introduce package supportAlexandre Torgue
A same SoC can be available in several packages. Differences between packages are only the numbers of available balls. In order not to write a driver for each new package, same driver (ex: pinctrl-stm32mp157.c) will be used. This patch introduces the "package" property for each pin. So on a same driver, it will be possible to indicate on which package the pin is available. The package information will be got from the device tree. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-11pinctrl: imx8mq: Add suspend/resume opsAbel Vesa
To support pinctl hog restore after LPSR resume back, add the generic suspend/resume in pinctrl-imx along with the generic pm ops to be used by platform specific drivers. Then make use of the newly added ops in i.MX8MQ platform specific driver. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-11pinctrl: artpec6: Drop unused function and renameLinus Walleij
The pincontrol callbacks used to be symmetric: enable/disable. However for a while we only have one function that set the muxing, no disabling. Drop the unused disable function, and rename the *enable() function to *set(). Reported-by: Nathan Chancellor <natechancellor@gmail.com> Cc: YueHaibing <yuehaibing@huawei.com> Reviewed-by: Nathan Chancellor <natechancellor@gmail.com> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-09pinctrl: pinctrl-intel: move gpio suspend/resume to noirq phaseBinbin Wu
In current driver, SET_LATE_SYSTEM_SLEEP_PM_OPS is used to install the callbacks for suspend/resume. GPIO pin may be used as the interrupt pin by some device. However, using SET_LATE_SYSTEM_SLEEP_PM_OPS() to install the callbacks, the resume callback is called after resume_device_irqs(). Unintended interrupts may arrive due to resuming device irqs first, but the GPIO controller is not properly restored. Normally, for a SMP system, there are multiple cores, so even when there are unintended interrupts, BSP gets the chance to initialize the GPIO chip soon. But when there is only 1 core is active (other cores are offlined or single core) during resume, it is more easily to observe the unintended interrupts. This patch renames the suspend/resume function by adding suffix "_noirq", and installs the callbacks using SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(). Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-04-08pinctrl: Added IRQF_SHARED flag for amd-pinctrl driverSandeep Singh
Some of the AMD reference boards used single GPIO line for multiple devices. So added IRQF_SHARED flag in amd pinctrl driver. Signed-off-by: Sandeep Singh <Sandeep.Singh@amd.com> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> cc: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-08pinctrl: freescale: use devm_platform_ioremap_resource() to simplify codeAnson Huang
Use the new helper devm_platform_ioremap_resource() which wraps the platform_get_resource() and devm_ioremap_resource() together, to simplify the code. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Mukesh Ojha <mojha@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-08pinctrl: imx: remove an unnecessary NULL checkDan Carpenter
The address of "ipctl->pin_regs[pin_id]" can't be NULL. It's the offset into an array in the middle of a struct. This patch removes the check. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-08pinctrl: add drive for I2C related pins on MT8183Zhiyong Tao
This patch provides the advanced drive for I2C used pins on MT8183. The detail strength specification description of the I2C pin: When E1=0/E0=0, the strength is 0.125mA. When E1=0/E0=1, the strength is 0.25mA. When E1=1/E0=0, the strength is 0.5mA. When E1=1/E0=1, the strength is 1mA. For I2C pins, there are existing generic driving setup and the above specific driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA driving adjustment in generic driving setup. But in specific driving setup, they can support 0.125/0.25/0.5/1mA adjustment. If we enable specific driving setup for I2C pins, the existing generic driving setup will be disabled. For some special features, we need the I2C pins specific driving setup. The specific driving setup is controlled by E1E0EN. So we need add extra vendor driving preperty instead of the generic driving property. We can add "mediatek,drive-strength-adv = <XXX>;" to describe the specific driving setup property. "XXX" means the value of E1E0EN. So the valid arguments of "mediatek,drive-strength-adv" are from 0 to 7. Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-08pinctrl: axp209: Fix NULL pointer dereference after allocationAditya Pakki
axp20x_build_funcs_groups allocates groups via devm_kcalloc and tries to dereference without checking for NULL. This patch avoids such a scenario. Signed-off-by: Aditya Pakki <pakki001@umn.edu> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-05pinctrl: mcp23s08: debugfs: remove custom printerJan Kundrát
The comment for this dbg_show says that it is supposed to return more than what the generic code is showing, including de-glitching. That's wrong because: - this chip does not support deglitching, - the code does not print anything extra compared to the generic handler, - its behavior is different because it skips unrequested GPIOs; the generic code prints their names if they're assigned There is an important difference, though. Previously, dbg_show would re-check some registers to see if they still match what the regmap thinks should be in there. This was semi-useful when develpoing the HW board because it immediately pointed to SPI wiring problem if a CS connection was missing (0xffs are easy to see). However, I do not think that this makes much sense -- and one could always do this in some other way if needed. Signed-off-by: Jan Kundrát <jan.kundrat@cesnet.cz> Cc: Phil Reid <preid@electromag.com.au> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-04pinctrl: artpec6: Make two functions staticYueHaibing
Fix sparse warnings: drivers/pinctrl/pinctrl-artpec6.c:691:5: warning: symbol 'artpec6_pmx_enable' was not declared. Should it be static? drivers/pinctrl/pinctrl-artpec6.c:705:6: warning: symbol 'artpec6_pmx_disable' was not declared. Should it be static? Signed-off-by: YueHaibing <yuehaibing@huawei.com> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Reviewed-by: Mukesh Ojha <mojha@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-04Merge tag 'sh-pfc-for-v5.2-tag1' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.2 - Add HSCIF (serial) pin groups on R-Car H1, - Add I2C[035] pin groups on R-Car M3-N, - Add CANFD pin groups on RZ/G2M and RZ/G2E, - Retain SDHI/MMC clock return path delay configuration across suspend/resume on R-Car Gen3, - More validation of pinmux tables at build and runtime, including compile-test coverage of all drivers, - Small fixes, improvements, and cleanups.
2019-04-04pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functionsTakeshi Kihara
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC. These pins are physically muxed with other pins. Therefore, setup of MOD_SEL is needed for exclusive control with other pins. [takeshi.kihara.df: add blank lines after function declarations] Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [uli: use standard macros PINMUX_IPSR_PHYS and PINMUX_IPSR_PHYS_MSEL] Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-04pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin dataUlrich Hecht
Pin data for I2C controllers 0, 3 and 5 is properly defined already. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-04pinctrl: sh-pfc: r8a77970: Fix spacingGeert Uytterhoeven
Replace "F_(0,0)" by "F_(0, 0)". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-04pinctrl: fsl: Make pinctrl_ipc_handle staticYueHaibing
Fix sparse warning: drivers/pinctrl/freescale/pinctrl-scu.c:38:19: warning: symbol 'pinctrl_ipc_handle' was not declared. Should it be static? Signed-off-by: YueHaibing <yuehaibing@huawei.com> Reviewed-by: Mukesh Ojha <mojha@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-04pinctrl: lochnagar: Add support for the Cirrus Logic LochnagarCharles Keepax
Lochnagar is an evaluation and development board for Cirrus Logic Smart CODEC and Amp devices. It allows the connection of most Cirrus Logic devices on mini-cards, as well as allowing connection of various application processor systems to provide a full evaluation platform. This driver supports the board controller chip on the Lochnagar board. Lochnagar provides many pins which can generally be used for an audio function such as an AIF or a PDM interface, but also as GPIOs. Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-04pinctrl: sunxi: Allow to disable pinctrl driversMaxime Ripard
Our pinctrl drivers are consisting of some common code, and big pin tables that are SoC-specific. This is fine in most cases, but when you want to reduce the size of the particular kernel image, those big tables are, well, quite big. We haven't had the option to disable them in the past since they were hidden Kconfig options based on the SoC support. However, that granularity isn't great since we don't have one Kconfig option per-SoC, but rather one by family. Make those options selectable by the user so that they can disable it if needed, while keeping the current default to not change the standard case. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-04pinctrl: sunxi: Declare set_config on the GPIO chipMaxime Ripard
Our pin controller can configure the pins no matter how they are muxed, so it makes sense to allow this for GPIOs as well. Add the generic set_config function so that we can rely on the existing pinctrl code we have. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-04pinctrl: sunxi: Fix variable assignment syntaxMaxime Ripard
Lines are usually ended with a semi-column in C, yet this was copied from a structure declaration to the init variant while keeping the comma at the end. Make sure we have a normal syntax, instead of multiple assignments. Fixes: d83c82ce7ccd ("pinctrl: sunxi: support multiple pin controller") Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-04pinctrl: sunxi: implement pin_config_setMaxime Ripard
The sunxi pinctrl only implements the pin_config_group_set callback at the moment, whereas the gpiochip_generic_config function relies on pin_config_set. Rework the functions a little to support pin_config_set, and rely on it for pin_config_group_set. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-03pinctrl: cedarfork: Update pin names according to v1.13cAndy Shevchenko
Version 1.13c of pin list has some changes in pin names for Intel Cedarfork. Update the driver accordingly. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linar.org>
2019-04-02pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDFTakeshi Kihara
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50 of Feb 12, 2019, the sel_ndfc MOD_SEL register bit is renamed to sel_ndf. Update the pin control drivers to reflect this. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Update R-Car E3] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}Takeshi Kihara
According to the R-Car Gen3 Hardware Manual Errata for Rev 0.80 of Dec 22, 2017, and the Errata for Rev 1.50 of Dec 25, 2018, MOD_SEL0 register bits 3, 4, 17, and 18 are renamed from SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}. Update the pin control drivers to reflect this. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-03 05:07:34 +0000