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path: root/drivers/pinctrl
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2017-08-14pinctrl: bcm2835: constify gpio_chip structureGustavo A. R. Silva
This structure is only used to copy into other structure, so declare it as const. This issue was detected using Coccinelle and the following semantic patch: @r disable optional_qualifier@ identifier i; position p; @@ static struct gpio_chip i@p = { ... }; @ok@ identifier r.i; expression e; position p; @@ e = i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct gpio_chip e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct gpio_chip i = { ... }; In the following log you can see a significant difference in the code size and data segment, hence in the dec segment. This log is the output of the size command, before and after the code change: before: text data bss dec hex filename 18958 9000 128 28086 6db6 drivers/pinctrl/bcm/pinctrl-bcm2835.o after: text data bss dec hex filename 18764 8912 128 27804 6c9c drivers/pinctrl/bcm/pinctrl-bcm2835.o Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: zynq: Fix warnings in the driverNava kishore Manne
This patch fixes the below warning --> Prefer 'unsigned int' to bare use of 'unsigned'. --> line over 80 characters. --> Prefer 'unsigned int **' to bare use of 'unsigned **'. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: zynq: Fix kernel doc warningsNava kishore Manne
This patch fixes the kernel doc warnings in the driver. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: st: constify gpio_chip structureGustavo A. R. Silva
This structure is only used to copy into other structure, so declare it as const. This issue was detected using Coccinelle and the following semantic patch: @r disable optional_qualifier@ identifier i; position p; @@ static struct gpio_chip i@p = { ... }; @ok@ identifier r.i; expression e; position p; @@ e = i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct gpio_chip e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct gpio_chip i = { ... }; In the following log you can see a significant difference in the code size and data segment, hence in the dec segment. This log is the output of the size command, before and after the code change: before: text data bss dec hex filename 21671 3632 128 25431 6357 drivers/pinctrl/pinctrl-st.o after: text data bss dec hex filename 21366 3576 128 25070 61ee drivers/pinctrl/pinctrl-st.o Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: baytrail: Do not call WARN_ON for a firmware bugHans de Goede
WARN_ON causes a backtrace to get logged which is only useful for kernel bugs. For signalling a firmware bug dev_warn(dev, FW_BUG "...") should be used. This fixes users running userspace software to monitor kernel oopses getting a false positive bug-report every boot because of the wrong use of WARN_ON. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: pinctrl-imx7ulp: add gpio_set_direction supportDong Aisheng
Add gpio_set_direction support. This makes the driver support GPIO input/output dynamically change from userspace. Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Stefan Agner <stefan@agner.ch> Cc: Fugang Duan <fugang.duan@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: imx: make imx_pmx_ops.gpio_set_direction platform specific callbacksDong Aisheng
Various IMX platforms may have different imx_pmx_ops.gpio_set_direction implementations, so let's make it platform specific callbacks instead of the fixed common one. Currently only VF610 platform implements it. No function level changes. Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: imx: remove gpio_request_enable and gpio_disable_freeDong Aisheng
gpio_request_enable/disable_free actually are not quite necessary as standard IMX pinctrl binding already sets GPIO mux from device tree, e.g. VF610_PAD_PTB20__GPIO_42 or MX7D_PAD_SD2_CD_B__GPIO5_IO9 No need to do it again in gpio_request_enable. And according to Stefan: "For all GPIO I checked in upstream device trees we assign a pinctrl to the same node, so in all cases gpio_request_enable/disable is really unnecessary." So it should be safe to simply remove it. Note that this changes semantics for Vybrid, e.g. "The two functions have been introduced for Vybrid (through SHARE_MUX_CONF_REG) and mux pins as GPIOs automatically when a GPIO gets requested. The automatic mux is optional by the pinmux/gpio subsystem semantics, and other NXP devices do not use it, instead an explicit pinctrl node is added in the device tree to mux GPIOs where required. Hence this change aligns Vybrid to other NXP (i.MX) devices. Note that all upstream device tree assign proper pinctrl properties where GPIOs are used so no change is necessary for device trees." Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fugang Duan <fugang.duan@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: imx: add imx7ulp driverDong Aisheng
i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface. This patch adds the IOMUXC1 support for A7. It only supports generic pin config. Cc: Bai Ping <ping.bai@nxp.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: imx: switch to use the generic pinmux propertyDong Aisheng
The generic pinmux property seems to be more suitable for IMX. So we change to use 'pinmux' instead of 'pins'. Cc: Bai Ping <ping.bai@nxp.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: uniphier: add UniPhier PXs3 pinctrl driverMasahiro Yamada
Add pin configuration and pinmux support for UniPhier PXs3 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: uniphier: add suspend / resume supportMasahiro Yamada
Save registers lost in the sleep when suspending, and restore them when resuming. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: uniphier: omit redundant input enable bit informationMasahiro Yamada
For LD11/20 SoCs (capable of per-pin input enable), the iectrl bit number matches its pin number. So, this is redundant information. Instead, we just need a flag to know if the iectrl gating exists or not. With this refactoring, 5 bits in pin data will be saved. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: uniphier: clean up GPIO port muxingMasahiro Yamada
There are a bunch of GPIO muxing data, but most of them are actually unneeded because GPIO-to-pin mapping can be specified by "gpio-ranges" DT properties. Tables that contain a set of GPIO pins are still needed for the named mapping by "gpio-ranges-group-names". This is a much cleaner way for UniPhier SoC family where GPIO numbers are not straight mapped to pin numbers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: uniphier: fix pin_config_get() for input-enableMasahiro Yamada
For LD11/LD20 SoCs (capable of per-pin input enable), iectrl bits are located across multiple registers. So, the register offset must be taken into account. Otherwise, wrong input-enable status is displayed. While we here, rename the macro because it is a base address. Fixes: aa543888ca8c ("pinctrl: uniphier: support per-pin input enable for new SoCs") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: uniphier: remove unneeded EXPORT_SYMBOL_GPL()Masahiro Yamada
All UniPhier pinctrl drivers are built-in. Exporting the symbol is meaningless. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: qcom: msm: constify gpio_chip structureGustavo A. R. Silva
This structure is only used to copy into other structure, so declare it as const. This issue was detected using Coccinelle and the following semantic patch: @r disable optional_qualifier@ identifier i; position p; @@ static struct gpio_chip i@p = { ... }; @ok@ identifier r.i; expression e; position p; @@ e = i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct gpio_chip e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct gpio_chip i = { ... }; In the following log you can see a significant difference in the code size and data segment, hence in the dec segment. This log is the output of the size command, before and after the code change: before: text data bss dec hex filename 13129 2808 192 16129 3f01 drivers/pinctrl/qcom/pinctrl-msm.o after: text data bss dec hex filename 12839 2720 192 15751 3d87 drivers/pinctrl/qcom/pinctrl-msm.o Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: qcom: ssbi-gpio: constify gpio_chip structureGustavo A. R. Silva
This structure is only used to copy into other structure, so declare it as const. This issue was detected using Coccinelle and the following semantic patch: @r disable optional_qualifier@ identifier i; position p; @@ static struct gpio_chip i@p = { ... }; @ok@ identifier r.i; expression e; position p; @@ e = i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct gpio_chip e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct gpio_chip i = { ... }; In the following log you can see a significant difference in the code size and data segment, hence in the dec segment. This log is the output of the size command, before and after the code change: before: text data bss dec hex filename 17061 6992 0 24053 5df5 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.o after: text data bss dec hex filename 16777 6904 0 23681 5c81 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.o Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: coh901: constify gpio_chip structureGustavo A. R. Silva
This structure is only used to copy into another structure, so declare it as const. This issue was detected using Coccinelle and the following semantic patch: @r disable optional_qualifier@ identifier i; position p; @@ static struct gpio_chip i@p = { ... }; @ok@ identifier r.i; expression e; position p; @@ e = i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct gpio_chip e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct gpio_chip i = { ... }; In the following log you can see a significant difference in the code size and data segment, hence in the dec segment. This log is the output of the size command, before and after the code change: before: text data bss dec hex filename 12775 3696 64 16535 4097 drivers/pinctrl/pinctrl-coh901.o after: bss dec hex filename 12440 3640 64 16144 3f10 drivers/pinctrl/pinctrl-coh901.o Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: nomadik: abx500: constify gpio_chip structureGustavo A. R. Silva
This structure is only used to copy into another structure, so declare it as const. This issue was detected using Coccinelle and the following semantic patch: @r disable optional_qualifier@ identifier i; position p; @@ static struct gpio_chip i@p = { ... }; @ok@ identifier r.i; expression e; position p; @@ e = i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct gpio_chip e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct gpio_chip i = { ... }; In the following log you can see a significant difference in the code size and data segment, hence in the dec segment. This log is the output of the size command, before and after the code change: before: text data bss dec hex filename 17545 5376 0 22921 5989 drivers/pinctrl/nomadik/pinctrl-abx500.o after: bss dec hex filename 17273 5320 0 22593 5841 drivers/pinctrl/nomadik/pinctrl-abx500.o Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: vt8500: wmt: constify gpio_chip structureGustavo A. R. Silva
This structure is only used to copy into other structure, so declare it as const. This issue was detected using Coccinelle and the following semantic patch: @r disable optional_qualifier@ identifier i; position p; @@ static struct gpio_chip i@p = { ... }; @ok@ identifier r.i; expression e; position p; @@ e = i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct gpio_chip e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct gpio_chip i = { ... }; In the following log you can see a significant difference in the code size and data segment, hence in the dec segment. This log is the output of the size command, before and after the code change: before: text data bss dec hex filename 7754 2328 0 10082 2762 drivers/pinctrl/vt8500/pinctrl-wmt.o after: text data bss dec hex filename 7472 2272 0 9744 2610 drivers/pinctrl/vt8500/pinctrl-wmt.o Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: rza1: constify gpio_chip structureGustavo A. R. Silva
This structure is only used to copy into other structure, so declare it as const. This issue was detected using Coccinelle and the following semantic patch: @r disable optional_qualifier@ identifier i; position p; @@ static struct gpio_chip i@p = { ... }; @ok@ identifier r.i; expression e; position p; @@ e = i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct gpio_chip e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct gpio_chip i = { ... }; In the following log you can see a significant difference in the code size and data segment, hence in the dec segment. This log is the output of the size command, before and after the code change: before: text data bss dec hex filename 11866 3520 128 15514 3c9a drivers/pinctrl/pinctrl-rza1.o after: text data bss dec hex filename 11539 3464 128 15131 3b1b drivers/pinctrl/pinctrl-rza1.o Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: sunxi: rename R_PIO i2c pin function nameIcenowy Zheng
The I2C pin functions in R_PIO used to be named "s_twi". As we usually use the name "i2c" instead of "twi" in the mainline kernel, change these names to "s_i2c" for consistency. The "s_twi" functions are not yet referenced by any device trees in mainline kernel so I think it's safe to change the name. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: sunxi: add support of R40 to A10 pinctrl driverIcenowy Zheng
R40 is said to be an upgrade of A20, and its pin configuration is also similar to A20 (and thus similar to A10). Add support for R40 to the A10 pinctrl driver. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: msm: add support to configure ipq40xx GPIO_PULL bitsRam Chandra Jangir
GPIO_PULL bits configurations in TLMM_GPIO_CFG register differs for IPQ40xx from rest of the other qcom SoCs. As it does not support the keeper state and therefore can't support bias-bus-hold property. This patch adds a pull_no_keeper setting which configures the msm_gpio_pull bits for ipq40xx. This is required to fix the proper configurations of gpio-pull bits for nand pins mux. IPQ40xx SoC: 2'b10: Internal pull up enable. 2'b11: Unsupport For other SoC's: 2'b10: Keeper 2'b11: Pull-Up Note: Due to pull_no_keeper length, all kerneldoc entries in the msm_pinctrl_soc_data struct had to be realigned. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org> Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: qcom: ipq4019: add most remaining pin definitionsRam Chandra Jangir
This patch adds multiple pinctrl functions and mappings for SDIO, NAND, I2S, WIFI, PCIE, LEDs, etc... that have been missing from the current minimal version. This patch has been updated from the original version that was posted by Ram Chandra Jangir on the LEDE-DEV ML: <https://patchwork.ozlabs.org/patch/752962/>. A short summary of the changes are documented in the device-tree patch of this series: "dt-bindings: pinctrl: add most other IPQ4019 pin functions and groups" Cc: John Crispin <john@phrozen.org> Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org> Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-09Merge tag 'pinctrl-v4.13-2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control fixes from Linus Walleij: "These are the pin control fixes I have gathered since the return from my vacation. They boiled in -next a while so let's get them in. Apart from the documentation build it is purely driver fixes. Which is nice. The Intel fixes seem kind of important. - Fix the documentation build as the docs were moved - Correct the UART pin list on the Intel Merrifield - Fix pin assignment and number of pins on the Marvell Armada 37xx pin controller - Cover the Setzer models in the Chromebook DMI quirk in the Intel cheryview driver so they start working - Add the missing "sim" function to the sunxi driver - Fix USB pin definitions on Uniphier Pro4 - Smatch fix for invalid reference in the zx pin control driver" * tag 'pinctrl-v4.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: generic: update references to Documentation/pinctrl.txt pinctrl: intel: merrifield: Correct UART pin lists pinctrl: armada-37xx: Fix number of pin in south bridge pinctrl: armada-37xx: Fix the pin 23 on south bridge pinctrl: cherryview: Add Setzer models to the Chromebook DMI quirk pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver pinctrl: uniphier: fix USB3 pin assignment for Pro4 pinctrl: zte: fix dereference of 'data' in zx_set_mux()
2017-08-07pinctrl: intel: merrifield: Correct UART pin listsAndy Shevchenko
UART pin lists consist GPIO numbers which is simply wrong. Replace it by pin numbers. Fixes: 4e80c8f50574 ("pinctrl: intel: Add Intel Merrifield pin controller support") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-07pinctrl: armada-37xx: Fix number of pin in south bridgeGregory CLEMENT
On the south bridge we have pin from to 29, so it gives 30 pins (and not 29). Without this patch the kernel complain with the following traces: cat /sys/kernel/debug/pinctrl/d0018800.pinctrl/pingroups [ 154.530205] armada-37xx-pinctrl d0018800.pinctrl: failed to get pin(29) name [ 154.537567] ------------[ cut here ]------------ [ 154.542348] WARNING: CPU: 1 PID: 1347 at /home/gclement/open/kernel/marvell-mainline-linux/drivers/pinctrl/core.c:1610 pinctrl_groups_show+0x15c/0x1a0 [ 154.555918] Modules linked in: [ 154.558890] CPU: 1 PID: 1347 Comm: cat Tainted: G W 4.13.0-rc1-00001-g19e1b9fa219d #525 [ 154.568316] Hardware name: Marvell Armada 3720 Development Board DB-88F3720-DDR3 (DT) [ 154.576311] task: ffff80001d32d100 task.stack: ffff80001bdc0000 [ 154.583048] PC is at pinctrl_groups_show+0x15c/0x1a0 [ 154.587816] LR is at pinctrl_groups_show+0x148/0x1a0 [ 154.592847] pc : [<ffff0000083e3adc>] lr : [<ffff0000083e3ac8>] pstate: 00000145 [ 154.600840] sp : ffff80001bdc3c80 [ 154.604255] x29: ffff80001bdc3c80 x28: 00000000f7750000 [ 154.609825] x27: ffff80001d05d198 x26: 0000000000000009 [ 154.615224] x25: ffff0000089ead20 x24: 0000000000000002 [ 154.620705] x23: ffff000008c8e1d0 x22: ffff80001be55700 [ 154.626187] x21: ffff80001d05d100 x20: 0000000000000005 [ 154.631667] x19: 0000000000000006 x18: 0000000000000010 [ 154.637238] x17: 0000000000000000 x16: ffff0000081fc4b8 [ 154.642726] x15: 0000000000000006 x14: ffff0000899e537f [ 154.648214] x13: ffff0000099e538d x12: 206f742064656c69 [ 154.653613] x11: 6166203a6c727463 x10: 0000000005f5e0ff [ 154.659094] x9 : ffff80001bdc38c0 x8 : 286e697020746567 [ 154.664576] x7 : ffff000008551870 x6 : 000000000000011b [ 154.670146] x5 : 0000000000000000 x4 : 0000000000000000 [ 154.675544] x3 : 0000000000000000 x2 : 0000000000000000 [ 154.681025] x1 : ffff000008c8e1d0 x0 : ffff80001be55700 [ 154.686507] Call trace: [ 154.688668] Exception stack(0xffff80001bdc3ab0 to 0xffff80001bdc3be0) [ 154.695224] 3aa0: 0000000000000006 0001000000000000 [ 154.703310] 3ac0: ffff80001bdc3c80 ffff0000083e3adc ffff80001bdc3bb0 00000000ffffffd8 [ 154.711304] 3ae0: 4554535953425553 6f6674616c703d4d 4349564544006d72 6674616c702b3d45 [ 154.719478] 3b00: 313030643a6d726f 6e69702e30303838 ffff80006c727463 ffff0000089635d8 [ 154.727562] 3b20: ffff80001d1ca0cb ffff000008af0fa4 ffff80001bdc3b40 ffff000008c8e1dc [ 154.735648] 3b40: ffff80001bdc3bc0 ffff000008223174 ffff80001be55700 ffff000008c8e1d0 [ 154.743731] 3b60: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 [ 154.752354] 3b80: 000000000000011b ffff000008551870 286e697020746567 ffff80001bdc38c0 [ 154.760446] 3ba0: 0000000005f5e0ff 6166203a6c727463 206f742064656c69 ffff0000099e538d [ 154.767910] 3bc0: ffff0000899e537f 0000000000000006 ffff0000081fc4b8 0000000000000000 [ 154.776085] [<ffff0000083e3adc>] pinctrl_groups_show+0x15c/0x1a0 [ 154.782823] [<ffff000008222abc>] seq_read+0x184/0x460 [ 154.787505] [<ffff000008344120>] full_proxy_read+0x60/0xa8 [ 154.793431] [<ffff0000081f9bec>] __vfs_read+0x1c/0x110 [ 154.799001] [<ffff0000081faff4>] vfs_read+0x84/0x140 [ 154.803860] [<ffff0000081fc4fc>] SyS_read+0x44/0xa0 [ 154.808983] [<ffff000008082f30>] el0_svc_naked+0x24/0x28 [ 154.814459] ---[ end trace 4cbb00a92d616b95 ]--- Cc: stable@vger.kernel.org Fixes: 87466ccd9401 ("pinctrl: armada-37xx: Add pin controller support for Armada 37xx") Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-07pinctrl: armada-37xx: Fix the pin 23 on south bridgeGregory CLEMENT
Pin 23 on South bridge does not belong to the rgmii group. It belongs to a separate group which can have 3 functions. Due to this the fix also have to update the way the functions are managed. Until now each groups used NB_FUNCS(which was 2) functions. For the mpp23, 3 functions are available but it is the only group which needs it, so on the loop involving NB_FUNCS an extra test was added to handle only the functions added. The bug was visible with the merge of the commit 07d065abf93d "arm64: dts: marvell: armada-3720-db: Add vqmmc regulator for SD slot", the gpio regulator used the gpio 23, due to this the whole rgmii group was setup to gpio which broke the Ethernet support on the Armada 3720 DB board. Thanks to this patch, the UHS SD cards (which need the vqmmc) _and_ the Ethernet work again. Cc: stable@vger.kernel.org Fixes: 87466ccd9401 ("pinctrl: armada-37xx: Add pin controller support for Armada 37xx") Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-03pinctrl: cherryview: Add Setzer models to the Chromebook DMI quirkAndy Shevchenko
Add one more model to the Chromebook DMI quirk to make it working again. Link: https://bugzilla.kernel.org/show_bug.cgi?id=194945 Fixes: 2a8209fa6823 ("pinctrl: cherryview: Extend the Chromebook DMI quirk to Intel_Strago systems") Reported-by: mail@abhishek.geek.nz Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-01pinctrl: stm32: select IRQ_DOMAIN_HIERARCHY instead of depends onMasahiro Yamada
Drivers that need IRQ_DOMAIN_HIERARCHY should "select" it, but drivers/pinctrl/stm32/Kconfig is the only exception that uses "depends on" syntax. This prevents GPIO drivers from select'ing IRQ_DOMAIN_HIERARCHY. For example, if I add "select IRQ_DOMAIN_HIERARCHY" to GPIO_XGENE_SB, I get the following recursive dependency error. drivers/gpio/Kconfig:13:error: recursive dependency detected! For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/gpio/Kconfig:13: symbol GPIOLIB is selected by PINCTRL_STM32 For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/pinctrl/stm32/Kconfig:3: symbol PINCTRL_STM32 is selected by PINCTRL_STM32F429 For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/pinctrl/stm32/Kconfig:11: symbol PINCTRL_STM32F429 depends on IRQ_DOMAIN_HIERARCHY For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" kernel/irq/Kconfig:67: symbol IRQ_DOMAIN_HIERARCHY is selected by GPIO_XGENE_SB For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/gpio/Kconfig:502: symbol GPIO_XGENE_SB depends on GPIOLIB Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-07-31pinctrl: sunxi: add a missing function of A10/A20 pinctrl driverIcenowy Zheng
The PH16 pin has a function with mux id 0x5, which is the DET pin of the "sim" (smart card reader) IP block. This function is missing in old versions of A10/A20 SoCs' datasheets and user manuals, so it's also missing in the old drivers. The newest A10 Datasheet V1.70 and A20 Datasheet V1.41 contain this pin function, and it's discovered during implementing R40 pinctrl driver. Add it to the driver. As we now merged A20 pinctrl driver to the A10 one, we need to only fix the A10 driver now. Fixes: f2821b1ca3a2 ("pinctrl: sunxi: Move Allwinner A10 pinctrl driver to a driver of its own") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-07-31pinctrl: uniphier: fix USB3 pin assignment for Pro4Kunihiko Hayashi
According to pinctrl assignment for Pro4, each definition of USB#2 and USB#3 are as follows. 184: USB2VBUS 185: USB2OD 186: USB2ID 187: USB3VBUS 188: USB3OD USB#2 has an additional pin "USB2ID", but the chip doesn't use this pin while in host-mode. Considering this pin, the pin definitions for USB#3 should be {187, 188}. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-07-31pinctrl: zte: fix dereference of 'data' in zx_set_mux()Shawn Guo
It fixes the following Smatch complaint: drivers/pinctrl/zte/pinctrl-zx.c:76 zx_set_mux() warn: variable dereferenced before check 'data' (see line 67) Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Fixes: cbff0c4d27f4 ("pinctrl: add ZTE ZX pinctrl driver support") Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-07-24pinctrl: samsung: Remove unneeded local variable initializationKrzysztof Kozlowski
Two local variables (shift and reg_con) were initialized to unused values - they were overwritten just few lines after. Getting rid of this unused initialization allows dropping other variables and compacting slightly the code. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-07-19pinctrl: samsung: Consistently use unsigned instead of u32 for nr_banksKrzysztof Kozlowski
Unlike for other countable members, the driver used u32 for number of banks (nr_banks). There is no specific need for using fixed-width integer in this particular place. Make it consistent. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-07-19pinctrl: samsung: Use unsigned int for number of controller IO mem resourcesKrzysztof Kozlowski
Number of IO memory resources cannot be negative obviously and the driver depends silently on this (by iterating from 0 to nr_ext_resources+1). Make this requirement explicit. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-07-18pinctrl: samsung: Use define from dt-bindings for pin mux functionKrzysztof Kozlowski
We already have macros for values used by driver and Device Tree sources for pin mux configuration. Use them instead of duplicating defines. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-07-18pinctrl: samsung: Fix invalid register offset used for Exynos5433 external ↵Krzysztof Kozlowski
interrupts When setting the pin function for external interrupts, the driver used wrong IO memory address base. The pin function register is always under pctl_base, not the eint_base. By updating wrong register, the external interrupts for chosen GPIO would not work at all and some other GPIO might be configured to wrong value. For example on Exynos5433-based boards, the external interrupts for gpf{1-5}-X GPIOs should not work at all (driver toggled reserved registers from ALIVE bank instead). Platforms other than Exynos5433 should not be affected as eint_base equals pctl_base in such case. Fixes: 8b1bd11c1f8f ("pinctrl: samsung: Add the support the multiple IORESOURCE_MEM for one pin-bank") Cc: <stable@vger.kernel.org> Reported-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-07-18pinctrl: samsung: Fix NULL pointer exception on external interrupts on S3C24xxKrzysztof Kozlowski
After commit 8b1bd11c1f8f ("pinctrl: samsung: Add the support the multiple IORESOURCE_MEM for one pin-bank"), the S3C24xx (and probably S3C64xx as well) fails: Unable to handle kernel NULL pointer dereference at virtual address 000000a8 ... (s3c24xx_demux_eint4_7) from [<c004469c>] (__handle_domain_irq+0x6c/0xcc) (__handle_domain_irq) from [<c0009444>] (s3c24xx_handle_irq+0x6c/0x12c) (s3c24xx_handle_irq) from [<c000e5fc>] (__irq_svc+0x5c/0x78) Mentioned commit moved the pointer to controller's base IO memory address from each controller's driver data (samsung_pinctrl_drv_data) to per-bank structure (samsung_pin_bank). The external interrupt demux handlers (s3c24xx_demux_eint()) tried to get this base address from opaque pointer stored under irq_chip data: struct irq_data *irqd = irq_desc_get_irq_data(desc); struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); ... pend = readl(bank->eint_base + EINTPEND_REG); which is wrong because this is hardware irq and it bank was never set for this irq_chip. For S3C24xx and S3C64xx, this partially reverts mentioned commit by bringing back the virt_base stored under each controller's driver data (samsung_pinctrl_drv_data). This virt_base address will be now duplicated: - samsung_pinctrl_drv_data->virt_base: used on S3C24xx and S3C64xx, - samsung_pin_bank->pctl_base: used on Exynos. Fixes: 8b1bd11c1f8f ("pinctrl: samsung: Add the support the multiple IORESOURCE_MEM for one pin-bank") Cc: <stable@vger.kernel.org> Cc: Sergio Prado <sergio.prado@e-labworks.com> Reported-by: Sergio Prado <sergio.prado@e-labworks.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Lihua Yao <ylhuajnu@163.com>
2017-07-17pinctrl: sh-pfc: r8a7796: Rename CS1# pin function definitionsTakeshi Kihara
This patch renames the pin function macro definitions of the GPSR1 and IPSR4 registers value for the CS1# pin. This is a correction because GPSR and IPSR register specification for R8A7796 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.54E. Fixes: f9aece7344bd81ce ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-07-17pinctrl: sh-pfc: r8a7796: Fix IPSR and MOD_SEL register pin assignment for ↵Takeshi Kihara
FSO pins group This patch fixes IPSR{12,17,18} and MOD_SEL0 pin assignment for FSO pins group. This is a correction because GPSR and IPSR register specification for R8A7796 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.54E. Fixes: f9aece7344bd81ce ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-07-17pinctrl: sh-pfc: r8a7796: Fix to delete MOD_SEL0 bit2 register definitionsTakeshi Kihara
This patch fixes the macro definitions of MOD_SEL0 bit2 register deleted. This is a correction because MOD_SEL register specification for R8A7796 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E. Fixes: f9aece7344bd81ce ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-07-17pinctrl: sh-pfc: r8a7796: Fix to delete SATA_DEVSLP_B pins function definitionsTakeshi Kihara
This patch fixes the macro definitions of SATA_DEVSLP_B pins function deleted. This is a correction to the incorrect implementation of IPSR register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: f9aece7344bd81ce ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-07-17pinctrl: sh-pfc: r8a7796: Fix to delete FSCLKST pin and IPSR7 bit[15:12] ↵Takeshi Kihara
register definitions This patch fixes the macro definitions of FSCLKST pins function and IPSR7 bit[15:12] register deleted. This is a correction because IPSR register specification for R8A7796 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E or later. Fixes: f9aece7344bd81ce ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-07-17pinctrl: sh-pfc: r8a7796: Fix MOD_SEL register pin assignment for ↵Takeshi Kihara
TCLK{1,2}_{A,B} pins group This patch fixes to set MOD_SEL2 bit19 when using TCLK2_A pin function is selected for IPSR16 bit[23:20] or using TCLK2_B pin function is selected for IPSR17 bit[27:24]. This is a correction to the incorrect implementation of MOD_SEL register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: f9aece7344bd81ce ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-07-17pinctrl: sh-pfc: r8a7796: Fix NFDATA{0..13} and NF{ALE,CLE,WE_N,RE_N} pin ↵Takeshi Kihara
function definitions This patch fixes the implementation incorrect of IPSR register value definitions for NFDATA{0..13} and NF{ALE,CLE,WE_N,RE_N} pins function. This is a correction to the incorrect implementation of IPSR register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: f9aece7344bd81ce ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-07-17pinctrl: sh-pfc: r8a7796: Fix FMCLK{_C,_D} and FMIN{_C,_D} pin function ↵Takeshi Kihara
definitions This patch fixes the implementation incorrect of IPSR register value definitions for FMCLK{_C,_D} and FMIN{_C,_D} pins function. This is a correction to the incorrect implementation of IPSR register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: f9aece7344bd81ce ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-07-17pinctrl: sh-pfc: r8a7796: Fix SCIF_CLK_{A,B} pin's MOD_SEL assignment to ↵Takeshi Kihara
MOD_SEL1 bit10 This patch fixes SCIF_CLK_{A,B} pin's MOD_SEL assignment from MOD_SEL1 bit11 to MOD_SEL1 bit10. This is a correction to the incorrect implementation of IPSR register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: f9aece7344bd81ce ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 01:55:30 +0000