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2015-11-02Merge tag 'gpio-v4.4-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull GPIO updates from Linus Walleij: "Here is the bulk of GPIO changes for the v4.4 development cycle. The only changes hitting outside drivers/gpio are in the pin control subsystem and these seem to have settled nicely in linux-next. Development mistakes and catfights are nicely documented in the reverts as you can see. The outcome of the ABI fight is that we're working on a chardev ABI for GPIO now, where hope to show results for the v4.5 kernel. Summary of changes: GPIO core: - Define and handle flags for open drain/open collector and open source/open emitter, also know as "single-ended" configurations. - Generic request/free operations that handle calling out to the (optional) pin control backend. - Some refactoring related to an ABI change that did not happen, yet provide useful. - Added a real-time compliance checklist. Many GPIO chips have irqchips, and need to think this over with the RT patches going upstream. - Restructure, fix and clean up Kconfig menus a bit. New drivers: - New driver for AMD Promony. - New driver for ACCES 104-IDIO-16, a port-mapped I/O card, ISA-style. Very retro. Subdriver changes: - OMAP changes to handle real time requirements. - Handle trigger types for edge and level IRQs on PL061 properly. As this hardware is very common it needs to set a proper example for others to follow. - Some container_of() cleanups. - Delete the unused MSM driver in favor of the driver that is embedded inside the pin control driver. - Cleanup of the ath79 GPIO driver used by many, many OpenWRT router targets. - A consolidated IT87xx driver replacing the earlier very specific IT8761e driver. - Handle the TI TCA9539 in the PCA953x driver. Also handle ACPI devices in this subdriver. - Drop xilinx arch dependencies as these FPGAs seem to profilate over a few different architectures. MIPS and ARM come to mind" * tag 'gpio-v4.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (57 commits) gpio: fix up SPI submenu gpio: drop surplus I2C dependencies gpio: drop surplus X86 dependencies gpio: dt-bindings: document the official use of "ngpios" gpio: MAINTAINERS: Add an entry for the ATH79 GPIO driver gpio / ACPI: Allow shared GPIO event to be read via operation region gpio: group port-mapped I/O drivers in a menu gpio: Add ACCES 104-IDIO-16 driver maintainer entry gpio: zynq: Document interrupt-controller DT binding gpio: xilinx: Drop architecture dependencies gpio: generic: Revert to old error handling in bgpio_map gpio: add a real time compliance notes Revert "gpio: add a real time compliance checklist" gpio: Add GPIO support for the ACCES 104-IDIO-16 gpio: driver for AMD Promontory gpio: xlp: Convert to use gpiolib irqchip helpers gpio: add a real time compliance checklist gpio/xilinx: enable for MIPS gpiolib: Add and use OF_GPIO_SINGLE_ENDED flag gpiolib: Split GPIO flags parsing and GPIO configuration ...
2015-11-02Merge tag 'pinctrl-v4.4-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the big bulk of pin control changes for the v4.4 kernel development cycle. Development pace is high in pin control again this merge window. 28 contributors, 83 patches. It hits a few sites outside the pin control subsystem: - Device tree bindings in Documentation (as usual) - MAINTAINERS - drivers/base/* for the "init" state handling by Doug Anderson. This has been ACKed by Greg. - drivers/usb/renesas_usbhs/rcar2.c, for a dependent Renesas change in the USB subsystem. This has been ACKed by both Greg and Felipe. - arch/arm/boot/dts/sama5d2.dtsi - this should ideally have gone through the ARM SoC tree but ended up here. This time I am using Geert Uytterhoeven as submaintainer for SH PFC since the are three-four people working in parallel with new Renesas ASICs. Summary of changes: Infrastructure: - Doug Anderson wrote a patch adding an "init" state different from the "default" state for pin control state handling in the core framework. This is applied before the driver's probe() call if defined and takes precedence over "default". If both are defined, "init" will be applied *before* probe() and "default" will be applied *after* probe(). Significant subdriver improvements: - SH PFC is switched to getting GPIO ranges from the device tree ranges property on DT platforms. - Got rid of CONFIG_ARCH_SHMOBILE_LEGACY, we are all modernized. - Got rid of SH PFC hardcoded IRQ numbers. - Allwinner sunxi external interrupt through the "r" controller. - Moved the Cygnus driver to use DT-provided GPIO ranges. New drivers: - Atmel PIO4 pin controller for the SAMA4D2 family New subdrivers: - Rockchip RK3036 subdriver - Renesas SH PFC R8A7795 subdriver - Allwinner sunxi A83T PIO subdriver - Freescale i.MX7d iomux lpsr subdriver - Marvell Berlin BG4CT subdriver - SiRF Atlas 7 step B SoC subdriver - Intel Broxton SoC subdriver Apart from this, the usual slew if syntactic and semantic fixes" * tag 'pinctrl-v4.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (81 commits) pinctrl: pinconf: remove needless loop pinctrl: uniphier: guard uniphier directory with CONFIG_PINCTRL_UNIPHIER pinctrl: zynq: fix UTF-8 errors pinctrl: zynq: Initialize early pinctrl: at91: add missing of_node_put pinctrl: tegra-xusb: Correct lane mux options pinctrl: intel: Add Intel Broxton pin controller support pinctrl: intel: Allow requesting pins which are in ACPI mode as GPIOs pinctrl: intel: Add support for multiple GPIO chips sharing the interrupt drivers/pinctrl: Add the concept of an "init" state pinctrl: uniphier: set input-enable before pin-muxing pinctrl: cygnus: Add new compatible string for gpio controller driver pinctrl: cygnus: Remove GPIO to Pinctrl pin mapping from driver pinctrl: cygnus: Optional DT property to support pin mappings pinctrl: sunxi: Add irq pinmuxing to sun6i "r" pincontroller pinctrl: sunxi: Fix irq_of_xlate for the r_pio pinctrl block pinctrl: sh-pfc: Remove obsolete r8a7778 platform_device_id entry pinctrl: sh-pfc: Remove obsolete r8a7779 platform_device_id entry pinctrl: sh-pfc: Stop including <linux/platform_data/gpio-rcar.h> usb: renesas_usbhs: Remove unneeded #include <linux/platform_data/gpio-rcar.h> ...
2015-10-31pinctrl: pinconf: remove needless loopLaurent Meunier
This removes a needless loop which was caught in pinconf.c. Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Laurent Meunier <laurent.meunier@st.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-31pinctrl: uniphier: guard uniphier directory with CONFIG_PINCTRL_UNIPHIERMasahiro Yamada
CONFIG_PINCTRL_UNIPHIER is more suitable than CONFIG_ARCH_UNIPHIER to guard the drivers/pinctrl/uniphier directory. The current CONFIG_PINCTRL_UNIPHIER_CORE is a bit long (it would break the indentation in drivers/pinctrl/Makefile), so rename it into CONFIG_PINCTRL_UNIPHIER. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-31pinctrl: zynq: fix UTF-8 errorsLinus Walleij
Fix up Sören's name in the Zynq driver. I caused this. I fix it. Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-30pinctrl: zynq: Initialize earlyMike Looijmans
Supplying pinmux configuration for e.g. gpio pins leads to deferred probes because the pinctrl device is probed much later than gpio. Move the init call to a much earlier stage so it probes before the devices that may need it. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Tested-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-27pinctrl: at91: add missing of_node_putJulia Lawall
for_each_child_of_node performs an of_node_get on each iteration, so a break out of the loop requires an of_node_put. A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ expression root,e; local idexpression child; @@ for_each_child_of_node(root, child) { ... when != of_node_put(child) when != e = child ( return child; | + of_node_put(child); ? return ...; ) ... } // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-27pinctrl: tegra-xusb: Correct lane mux optionsJon Hunter
The description of the XUSB_PADCTL_USB3_PAD_MUX_0 register in the Tegra124 documentation implies that all functions (pcie, usb3 and sata) can be muxed onto to all lanes (pcie lanes 0-4 and sata lane 0). However, it has been confirmed that this is not the case and the mux'ing options much more limited. Unfortunately, the public documentation has not been updated to reflect this and so detail the actual mux'ing options here by function: Function: Lanes: pcie1 x2: pcie3, pcie4 pcie1 x4: pcie1, pcie2, pcie3, pcie4 pcie2 x1 (option1): pcie0 pcie2 x1 (option2): pcie2 usb3 port 0: pcie0 usb3 port 1 (option 1): pcie1 usb3 port 1 (option 2): sata0 sata: sata0 Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-27pinctrl: intel: Add Intel Broxton pin controller supportMika Westerberg
This driver adds pinctrl/GPIO support for Intel Broxton. The GPIO controller is based on the same hardware design that is already used in Intel Sunrisepoint so we leverage the core driver here. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-27pinctrl: intel: Allow requesting pins which are in ACPI mode as GPIOsMika Westerberg
Reserved for ACPI actually means that in such case the GPIO hardware will not update the interrupt status register (GPI_IS) even if the pin is configured to trigger an interrupt. It will update GPI_GPE_STS instead and does not trigger an interrupt. Allow using such pins as GPIOs, only prevent their usage as interrupts. We also rename function intel_pad_reserved_for_acpi() to be intel_pad_acpi_mode() which reflects the actual meaning better. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-27pinctrl: intel: Add support for multiple GPIO chips sharing the interruptMika Westerberg
On Intel Broxton the GPIO hardware consists of several chips that all share the parent interrupt. It is not possible to handle this by setting chained handler for each chip (as they will overwrite each other). To overcome this we need to request the interrupt using devm_request_irq() and pass IRQF_SHARED with the flags. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-27drivers/pinctrl: Add the concept of an "init" stateDouglas Anderson
For pinctrl the "default" state is applied to pins before the driver's probe function is called. This is normally a sensible thing to do, but in some cases can cause problems. That's because the pins will change state before the driver is given a chance to program how those pins should behave. As an example you might have a regulator that is controlled by a PWM (output high = high voltage, output low = low voltage). The firmware might leave this pin as driven high. If we allow the driver core to reconfigure this pin as a PWM pin before the PWM's probe function runs then you might end up running at too low of a voltage while we probe. Let's introudce a new "init" state. If this is defined we'll set pinctrl to this state before probe and then "default" after probe (unless the driver explicitly changed states already). An alternative idea that was thought of was to use the pre-existing "sleep" or "idle" states and add a boolean property that we should start in that mode. This was not done because the "init" state is needed for correctness and those other states are only present (and only transitioned in to and out of) when (optional) power management is enabled. Changes in v3: - Moved declarations to pinctrl/devinfo.h - Fixed author/SoB Changes in v2: - Added comment to pinctrl_init_done() as per Linus W. Signed-off-by: Douglas Anderson <dianders@chromium.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Tested-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-27pinctrl: uniphier: set input-enable before pin-muxingMasahiro Yamada
While IECTRL is disabled, input signals are pulled-down internally. If pin-muxing is set up first, glitch signals (Low to High transition) might be input to hardware blocks. Bad case scenario: [1] The hardware block is already running before pinctrl is handled. (the reset is de-asserted by default or by a firmware, for example) [2] The pin-muxing is set up. The input signals to hardware block are pulled-down by the chip-internal biasing. [3] The pins are input-enabled. The signals from the board reach the hardware block. Actually, one invalid character is input to the UART blocks for such SoCs as PH1-LD4, PH1-sLD8, where UART devices start to run at the power on reset. To avoid such problems, pins should be input-enabled before muxing. Fixes: 6e9088920258 ("pinctrl: UniPhier: add UniPhier pinctrl core support") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Dai Okamura <okamura.dai@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-27pinctrl: cygnus: Remove GPIO to Pinctrl pin mapping from driverPramod Kumar
Remove gpio to pinctrl pin mapping code from driver and address this through standard property "gpio-ranges". Signed-off-by: Pramod Kumar <pramodku@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-26Merge branch 'sh-pfc-for-v4.4' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
2015-10-23pinctrl: sunxi: Add irq pinmuxing to sun6i "r" pincontrollerHans de Goede
Add pinmuxing for external interrupt functionality through the sun6i "r" pincontroller. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-23pinctrl: sunxi: Fix irq_of_xlate for the r_pio pinctrl blockHans de Goede
The r_pio gpio / pin controller has a pin_base of non 0, we need to adjust for this before calling sunxi_pinctrl_desc_find_function_by_pin. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-20pinctrl: sh-pfc: Remove obsolete r8a7778 platform_device_id entryGeert Uytterhoeven
Since the removal of the r8a7778 legacy SoC code in commit 4baadb9e05c68962 ("ARM: shmobile: r8a7778: remove obsolete setup code"), r8a7778 is only supported in generic DT-only ARM multi-platform builds. The driver doesn't need to match platform devices by name anymore, hence remove the corresponding platform_device_id entry. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-20pinctrl: sh-pfc: Remove obsolete r8a7779 platform_device_id entryGeert Uytterhoeven
Since the removal of the r8a7779 legacy SoC code in commit c99cd90d98a98aa1 ("ARM: shmobile: r8a7779: Remove legacy SoC code"), r8a7779 is only supported in generic DT-only ARM multi-platform builds. The driver doesn't need to match platform devices by name anymore, hence remove the corresponding platform_device_id entry. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-20pinctrl: sh-pfc: Stop including <linux/platform_data/gpio-rcar.h>Geert Uytterhoeven
This header file will be removed soon. Copy the helper macro RCAR_GP_PIN(), which is used by the pinctrl drivers only, to sh_pfc.h, and drop the #include. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-20pinctrl: sh-pfc: Rename .gpio_data[] to .pinmux_data[]Geert Uytterhoeven
The sh_pfc_soc_info.gpio_data[] array contains not only GPIO data, but also various other pinmux-related data (functions and marks). Every single driver already calls its local array pinmux_data[]. Hence rename the sh_pfc_soc_info member to "pinmux_data". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-10-20pinctrl: sh-pfc: r8a7778: Add bias (pull-up) pinconf supportUlrich Hecht
On this SoC there is no simple mapping of GP pins to pull-up register bits, so we need a table. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-10-20pinctrl: sh-pfc: Add macros defining GP ports with config flagsUlrich Hecht
PORT_GP_CFG_1 and PORT_GP_CFG_32 work like their non-CFG counterparts but accept an extra argument with config flags. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-10-20pinctrl: sh-pfc: r8a7794: Add VIN pin groupsKoji Matsuoka
Add VIN0/1 pin groups to R8A7794 PFC driver. Sergei: rebased, renamed, added changelog, gathered 12 VIN1 data pins into a single pin group, added "vin1_data10" pin group, used 'union vin_data' and VIN_DATA_PIN_GROUP() macro to describe VIN1 pins, reversed the order of the VIN1 pin groups, removed unneeded empty lines, fixed VIN1 separator comment. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-10-20pinctrl: sh-pfc: r8a779[01]: Move 'union vin_data' to shared header fileSergei Shtylyov
R8A7790/1 PFC drivers use almost identical 'union vin_data' and completely identical VIN_DATA_PIN_GROUP() macro; we thus can move them into the shared header file... Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-10-16pinctrl: baytrail: Fix compilation warnings when !CONFIG_PMMika Westerberg
When CONFIG_PM is not set we get following compilation warnings: warning: ‘byt_gpio_runtime_suspend’ defined but not used [-Wunused-function] warning: ‘byt_gpio_runtime_resume’ defined but not used [-Wunused-function] Fix this by guarding byt_gpio_runtime_suspend()/byt_gpio_runtime_resume() with #ifdef CONFIG_PM. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-16pinctrl: intel: Fix compilation warning when !CONFIG_PM_SLEEPMika Westerberg
We get following warning when CONFIG_PM_SLEEP is not set warning: ‘intel_gpio_irq_init’ defined but not used [-Wunused-function] Since the function is only called from intel_pinctrl_resume() move it inside CONFIG_PM_SLEEP guard as well. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-16pinctrl: qcom: ssbi: fix compilation with DEBUG_FS=nJonas Gorski
The DEBUG_FS=n #defines for the dbg_show functions were missed when renaming the driver from msm_ to pm8xxx_, causing it to break the build when DEBUG_FS isn't enabled: CC [M] drivers/pinctrl/qcom/pinctrl-ssbi-gpio.o drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c:597:14: error: ‘pm8xxx_gpio_dbg_show’ undeclared here (not in a function) .dbg_show = pm8xxx_gpio_dbg_show, Fix this by renaming them correctly. Fixes: b4c45fe974bc ("pinctrl: qcom: ssbi: Family A gpio & mpp drivers") Signed-off-by: Jonas Gorski <jogo@openwrt.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-16pinctrl: replace trivial implementations of gpio_chip request/freeJonas Gorski
Replace all trivial request/free callbacks that do nothing but call into pinctrl code with the generic versions. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Eric Anholt <eric@anholt.net> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Baruch Siach <baruch@tkos.co.il> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Lee Jones <lee@kernel.org> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-16pinctrl: atlas7: support atlas7 step B changesWei Chen
The the pin groups and pin functions have been changed in atlas7 step B soc. We have to update the driver to support step B chip. Changes: 1. add 5 jtag pins to IOC_TOP: "jtag_tdo", "jtag_tms","jtag_tck", "jtag_tdi", "jtag_trstn" these 5 pins can be mutiplex with other functions, so we have to conver these 5 pins in pinmux. 2. add pin groups for audio digmic, audio spdif, can transceiver en, can transceiver stb, i2s0, i2s1 and jtag. 3. serval pins can be located to more PADs: audio_uart0_urfs, audio_uart1_urfs, audio_uart2_urfs, audio_uart2_urxd, audio_uart2_usclk, audio_uart2_utfs, audio_uart2_utxd, can0_rxd, can0_txd, can1_rxd, can1_txd jtag_ntrst, jtag_swdiotms, jtag_tck, jtag_tdi, jtag_tdo, pw_cko0, pw_cko1, pw_i2s01, pw_pwm0, pw_pwm1, sd2_cdb, sd2_wpb, uart2_cts, uart2_rts, uart2_rxd, uart2_txd, uart3_cts, uart3_rts, uart3_rxd, uart3_txd, uart4_cts, uart4_rts, usb0_drvvbus, usb1_drvvbus. Because of Changes#3, some functions should have more than one pin groups. So we have to split the original pin group to serval pin groups. For example: audio_uart0 has 5 pins, on STEPA, each of these 5 pins only has one related PAD. But on STEPB, audio_uart0_urfs has 4 related PAD. So we place the 4 pins with one PAD into a single pin group: audio_uart0_basic_group. and place urfs pin wtih different PADs to 4 different pin groups: audio_uart0_urfs_group0, ..., audio_uart0_urfs_group3 A full audio_uart0 pin group can be: pinctrl-0 = <&audio_uart0_basic_group &audio_uart0_urfs_group0>; If audio_uart0 pin group encountered some confiction, we only have to change the urfs group: pinctrl-0 = <&audio_uart0_basic_group &audio_uart0_urfs_group2>; Signed-off-by: Wei Chen <Wei.Chen@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-16pinctrl: berlin: fix BG2CD field widthsThomas Hebb
The previous register layout was incorrect, many of the fields having fewer bits than were needed to represent all their modes. The new layout is taken from the bootloader source of a BG2CD device. Signed-off-by: Thomas Hebb <tommyhebb@gmail.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-16pinctrl: berlin: fix my family name spellingAntoine Ténart
My family name contained an accent when I submitted the Berlin pinctrl series in the first place. There was an encoding issue when the series was applied. Fix this. Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> [Je me rendis tous les accents aigus] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-16pinctrl: berlin: add explicit dependency on OFAntoine Tenart
Berlin pinctrl drivers depends on CONFIG_OF. This patch adds this dependency explicitly. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-16pinctrl: berlin: select the pinctrl driver according to the SoC usedAntoine Tenart
This patch prepares to remove the pinctrl driver selection from the mach-berlin Kconfig. To do so, bool is replaced by def_bool. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-16pinctrl: berlin: add the berlin4ct pinctrl driverJisheng Zhang
Add the pin-controller driver for Marvell Berlin BG4CT SoC, with definition of its groups and functions. This uses the core Berlin pinctrl driver. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-16pinctrl: berlin: Make berlin pinctrl driver visible if COMPILE_TEST=yJisheng Zhang
It is good to allow berlin pinctrl driver to build with COMPILE_TEST, so make the it menu visible when compile-testing. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-16pinctrl: berlin: introduce berlin_pinctrl_probe_regmap()Jisheng Zhang
This is to prepare for the next berlin4ct support, where we won't use simple-mfd any more. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-02pinctrl: pinconf-generic: add "input-schmitt" DT propertyMasahiro Yamada
PIN_CONFIG_INPUT_SCHMITT is defined in enum_pin_config_param, but the corresponding DT property is missing. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-02pinctrl: pinconf-generic: sort pin configuration params alphabeticallyMasahiro Yamada
Currently, the dt_params array in drivers/pinctrl/pinconf-generic.c is not sorted in the same order as the enum pin_config_param in include/linux/pinctrl/pinconf-generic.h. Sort enum pin_config_param, conf_items, dt_params, alphabetically for consistency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-02pinctrl: at91-pio4: irq argument as been removed from irq flow handlersLudovic Desroches
Irq argument as been removed from irq flow handlers so use the irq descriptor to retrieve data we need. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-02pinctrl: at91-pio4: use irq_set_handler_lockedLudovic Desroches
Use irq_set_handler_locked() as it avoids a redundant lookup of the irq descriptor. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-02pinctrl: freescale: imx7d: support iomux lpsr controllerAdrian Alonso
iMX7D has two iomuxc controllers, iomuxc controller similar as previous iMX SoC generation and iomuxc-lpsr which provides low power state rentetion capabilities on gpios that are part of iomuxc-lpsr Add iomuxc-lpsr gpio group id's Signed-off-by: Adrian Alonso <aalonso@freescale.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-02pinctrl: freescale: imx: add shared input select reg supportAdrian Alonso
- Add shared input select register support - imx7d has two iomux controllers iomuxc and iomuxc-lpsr which share select_input register for daisy chain settings Signed-off-by: Adrian Alonso <aalonso@freescale.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-02pinctrl: freescale: imx: allow mux_reg offset zeroAdrian Alonso
Allow mux_reg offset zero to be a valid pin_id, on imx7d mux_conf reg offset is zero for iomuxc-lspr controller Signed-off-by: Adrian Alonso <aalonso@freescale.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-02pinctrl: freescale: imx: fix system crash if enable two pinctl instancesRobin Gong
Fix system chrash caused by groups whose number is smaller than the number of groups of the last pinctl instance which is not initialized. iMX7D supports two iomux controllers (iomuxc-lpsr and iomuxc) on probing the second instance (iomuxc) the chrash below occurs. Uncompressing Linux... done, booting the kernel. [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 4.2.0-next-20150901-00006-gebfa43c (aalonso@bluefly) [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7) [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasin instruction cache [ 0.000000] Machine model: Freescale i.MX7 SabreSD Board [ 0.661012] [<802a6cb0>] (strcmp) from [<802cc80c>] (imx_dt_node_to_map+0x58/0x208) [ 0.668879] [<802cc80c>] (imx_dt_node_to_map) from [<802cbe24>] (pinctrl_dt_to_map+0x174/0x2b0) [ 0.677654] [<802cbe24>] (pinctrl_dt_to_map) from [<802c8f18>] (pinctrl_get+0x100/0x424) [ 0.685878] [<802c8f18>] (pinctrl_get) from [<802c9510>] (pinctrl_register+0x26c/0x480) [ 0.694104] [<802c9510>] (pinctrl_register) from [<802ccf3c>] (imx_pinctrl_probe+0x580/0x6e8) [ 0.702706] [<802ccf3c>] (imx_pinctrl_probe) from [<80351b58>] (platform_drv_probe+0x44/0xa4) [ 0.711455] [<80351b58>] (platform_drv_probe) from [<803503ec>] (driver_probe_device+0x174/0x2b4) [ 0.720405] [<803503ec>] (driver_probe_device) from [<803505fc>] (__driver_attach+0x8c/0x90) [ 0.728982] [<803505fc>] (__driver_attach) from [<8034e930>] (bus_for_each_dev+0x6c/0xa0) [ 0.737381] [<8034e930>] (bus_for_each_dev) from [<8034fb88>] (bus_add_driver+0x148/0x1f0) [ 0.745804] [<8034fb88>] (bus_add_driver) from [<80350c00>] (driver_register+0x78/0xf8) [ 0.753880] [<80350c00>] (driver_register) from [<800097d0>] (do_one_initcall+0x8c/0x1d4) [ 0.762282] [<800097d0>] (do_one_initcall) from [<80987dac>] (kernel_init_freeable+0x144/0x1e4) [ 0.771061] [<80987dac>] (kernel_init_freeable) from [<806d9c7c>] (kernel_init+0x8/0xe8) [ 0.779285] [<806d9c7c>] (kernel_init) from [<8000f628>] (ret_from_fork+0x14/0x2c) [ 0.786981] Code: e3520000 e5e32001 1afffffb e12fff1e (e4d03001) Signed-off-by: Robin Gong <b38343@freescale.com> Signed-off-by: Adrian Alonso <aalonso@freescale.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-02pinctrl: at91-pio4: add PM stuffLudovic Desroches
Allow GPIOs to be configured as wakeup sources. When going to suspend, disable all GPIO irqs excepting the one configured as wakeup sources. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-02pinctrl: sunxi: add allwinner A83T PIO controller supportVishnu Patekar
Allwinner A83T soc port controller has 8 ports. It has 3 IRQ banks namely PB, PG, PH. Pinmuxing are different for some pins as compared to sun8i A23 and A33. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-02pinctrl: uniphier: add SD card pinmux settingsMasahiro Yamada
Add SD card pinmux settings for PH1-LD4, PH1-Pro4, PH1-sLD8, PH1-Pro5, ProXstream2, and PH1-LD6b SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-02pinctrl: samsung: Remove unneded semicolonJavier Martinez Canillas
It's not needed an is just creating a null statement, so remove it. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-02pinctrl: mediatek: Remove unneded semicolonJavier Martinez Canillas
It's not needed an is just creating a null statement, so remove it. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 06:59:26 +0000