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path: root/drivers/pinctrl/pinctrl-ingenic.c
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2021-05-09linux/kconfig.h: replace IF_ENABLED() with PTR_IF() in <linux/kernel.h>Masahiro Yamada
<linux/kconfig.h> is included from all the kernel-space source files, including C, assembly, linker scripts. It is intended to contain a minimal set of macros to evaluate CONFIG options. IF_ENABLED() is an intruder here because (x ? y : z) is C code, which should not be included from assembly files or linker scripts. Also, <linux/kconfig.h> is no longer self-contained because NULL is defined in <linux/stddef.h>. Move IF_ENABLED() out to <linux/kernel.h> as PTR_IF(). PTF_IF() takes the general boolean expression instead of a CONFIG option so that it fits better in <linux/kernel.h>. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Kees Cook <keescook@chromium.org>
2021-04-22pinctrl: Ingenic: Add pinctrl driver for X2000.周琰杰 (Zhou Yanjie)
Add support for probing the pinctrl-ingenic driver on the X2000 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-13-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-04-22pinctrl: Ingenic: Add pinctrl driver for JZ4775.周琰杰 (Zhou Yanjie)
Add support for probing the pinctrl-ingenic driver on the JZ4775 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-12-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-04-22pinctrl: Ingenic: Add pinctrl driver for JZ4755.周琰杰 (Zhou Yanjie)
Add support for probing the pinctrl-ingenic driver on the JZ4755 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-11-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-04-22pinctrl: Ingenic: Add pinctrl driver for JZ4750.周琰杰 (Zhou Yanjie)
Add support for probing the pinctrl-ingenic driver on the JZ4750 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-10-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-04-22pinctrl: Ingenic: Add pinctrl driver for JZ4730.周琰杰 (Zhou Yanjie)
Add support for probing the pinctrl-ingenic driver on the JZ4730 SoC from Ingenic. This driver is derived from Paul Boddie. It is worth to noting that the JZ4730 SoC is special in having two control registers (upper/lower), so add code to handle the JZ4730 specific register offsets and some register pairs which have 2 bits for each GPIO pin. Tested-by: H. Nikolaus Schaller <hns@goldelico.com> # on Letux400 Co-developed-by: Paul Boddie <paul@boddie.org.uk> Signed-off-by: Paul Boddie <paul@boddie.org.uk> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-9-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-04-22pinctrl: Ingenic: Reformat the code.周琰杰 (Zhou Yanjie)
1.Move the "INGENIC_PIN_GROUP_FUNCS" to the macro definition section. 2.Add tabs before values to align the code in the macro definition section. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-7-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-04-22pinctrl: Ingenic: Add DMIC pins support for Ingenic SoCs.周琰杰 (Zhou Yanjie)
1.Add DMIC pins support for the JZ4780 SoC. 2.Add DMIC pins support for the X1000 SoC. 3.Add DMIC pins support for the X1500 SoC. 4.Add DMIC pins support for the X1830 SoC. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-6-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-04-22pinctrl: Ingenic: Improve LCD pins related code.周琰杰 (Zhou Yanjie)
1.In the JZ4740 part, remove pointless "lcd-no-pins", use "lcd-special" and "lcd-generic" instead "lcd-18bit-tft". Currently, in the mainline, no other devicetree out there is using the "lcd-18bit-tft" ABI, so we should be able to replace it safely. 2.In the JZ4725B part, adjust the location of the LCD pins related code to keep them consistent with the style of other parts. 3.In the JZ4760 part, add the missing comma and adjust element order in "jz4760_lcd_special_pins[]", keep them in the order of CLS/SPL/PS/REV like other "lcd_special_pins" arrays. And adjust the location of the "jz4760_lcd_generic" related code to keep them consistent with the style of other parts. 4.In the JZ4770 part, remove pointless "lcd-no-pins", add the missing "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic". 5.In the X1000 part and the X1500 part, remove pointless "lcd-no-pins". 6.In the X1830 part, replace "lcd-rgb-18bit" with "lcd-tft-8bit" and "lcd-tft-24bit", because of the description of the TRANS_CONFIG.MODE register bits in the PM manual of the X1830, shows that the X1830 only supppots 24bit mode and 8bit mode for tft interface, only 18 pins in the GPIO table are because of the data[17:16], the data[9:8], and the data[1:0] has not been connected. And according to the description, the two interfaces supported by X1830 are respectively referred to as "TFT interface" and "SLCD interface", so the "lcd-rgb-xxx" is replaced with "lcd-tft-xxx" to avoid confusion. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-5-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-04-22pinctrl: Ingenic: Adjust the sequence of X1830 SSI pin groups.周琰杰 (Zhou Yanjie)
Adjust the sequence of X1830's SSI related codes to make it consistent with other Ingenic SoCs. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-4-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-04-22pinctrl: Ingenic: Add support for read the pin configuration of X1830.周琰杰 (Zhou Yanjie)
Add X1830 support in "ingenic_pinconf_get()", so that it can read the configuration of X1830 SoC correctly. Fixes: d7da2a1e4e08 ("pinctrl: Ingenic: Add pinctrl driver for X1830.") Cc: <stable@vger.kernel.org> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-3-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-04-22pinctrl: Ingenic: Add missing pins to the JZ4770 MAC MII group.周琰杰 (Zhou Yanjie)
The MII group of JZ4770's MAC should have 7 pins, add missing pins to the MII group. Fixes: 5de1a73e78ed ("Pinctrl: Ingenic: Add missing parts for JZ4770 and JZ4780.") Cc: <stable@vger.kernel.org> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-2-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-10pinctrl: ingenic: add missing call to of_node_put()Yang Li
In one of the error paths of the for_each_child_of_node() loop in ingenic_gpio_probe, add missing call to of_node_put(). Fix the following coccicheck warning: ./drivers/pinctrl/pinctrl-ingenic.c:2485:1-23: WARNING: Function "for_each_child_of_node" should have of_node_put() before return around line 2489. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Acked-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1614303297-24178-1-git-send-email-yang.lee@linux.alibaba.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-02-22Merge tag 'pinctrl-v5.12-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.12 kernel. This time a calm set with no core changes. New drivers/subdrivers: - Renesas R8A7790A0 pin controller. - Allwinner H616 and H616-R pin controllers. - Qualcomm SM8350 and SC8180x pin controllers. Improvements: - Redo the DT bindings for Ralink RT2880. - A common Qualcomm TLMM DT binding in YAML. - Delete the unused drivers for U300, COH901, Sirf Atlas, and ZTE ZX" * tag 'pinctrl-v5.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (71 commits) pinctrl: mediatek: Fix trigger type setting follow for unexpected interrupt dt-bindings: pinctrl: Group tuples in pin control properties pinctrl: nuvoton: npcm7xx: Fix alignment of table header comment pinctrl: at91-pio4: fix "Prefer 'unsigned int' to bare use of 'unsigned'" pinctrl: at91-pio4: add support for slew-rate dt-bindings: pinctrl: at91-pio4: add slew-rate pinctrl: actions: Add depends on || COMPILE_TEST pinctrl: single: set function name when adding function pinctrl: qcom: Add sc8180x TLMM driver dt-bindings: pinctrl: qcom: Add sc8180x binding dt-bindings: pinctrl: qcom: Define common TLMM binding pinctrl: qcom: Add SM8350 pinctrl driver dt-bindings: pinctrl: qcom: Add SM8350 pinctrl bindings pinctrl: samsung: use raw_spinlock for s3c64xx dt-bindings: mediatek: mt8192: Fix dt_binding_check warning pinctrl: qcom: spmi-mpp: Add PM8019 compatible pinctrl: pinmux: add function selector to pinmux-functions pinctrl: samsung: use raw_spinlock for locking pinctrl: clarify #pinctrl-cells for pinctrl-single,pins pinctrl: actions: Add the platform dependency to drivers ...
2021-01-21pinctrl: ingenic: Improve JZ4760 supportPaul Cercueil
- Add otg function and otg-vbus group. - Add lcd-8bit, lcd-16bit, lcd-18bit, lcd-generic and lcd-special groups. Change the lcd-24bit group so that it only selects the pins that aren't in the lcd-18bit and lcd-generic groups (which breaks Device Tree in theory, but there is none out there for any JZ4760 based board, yet). Remove the lcd-no-pins group which is just useless. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210120110722.20133-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-18pinctrl: ingenic: Only support SoCs enabled in configPaul Cercueil
Tested on a JZ4740 system (ARCH=mips make qi_lb60_defconfig), this saves about 14 KiB, by allowing the compiler to garbage-collect all the functions and tables that correspond to SoCs that were disabled in the config. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20201213235447.138271-2-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-04pinctrl: ingenic: Rename registers from JZ4760_GPIO_* to JZ4770_GPIO_*Paul Cercueil
Now that JZ4760 support has been fixed, it looks wrong to have JZ4760_GPIO_* registers being written if the SoC is a JZ4770 or later. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20201211232810.261565-2-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-04pinctrl: ingenic: Fix JZ4760 supportPaul Cercueil
- JZ4760 and JZ4760B have a similar register layout as the JZ4740, and don't use the new register layout, which was introduced with the JZ4770 SoC and not the JZ4760 or JZ4760B SoCs. - The JZ4740 code path only expected two function modes to be configurable for each pin, and wouldn't work with more than two. Fix it for the JZ4760, which has four configurable function modes. Fixes: 0257595a5cf4 ("pinctrl: Ingenic: Add pinctrl driver for JZ4760 and JZ4760B.") Cc: <stable@vger.kernel.org> # 5.3 Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20201211232810.261565-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-12-16Merge tag 'pinctrl-v5.11-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.11 kernel. Drivers, drivers and drivers. Not a single core change. Some new stuff, especially a bunch of new Intel, Qualcomm and Ocelot SoCs. As part of the modularization attempt, I applied one patch affecting the firmware subsystem as a functional (not syntactic/semantic) dependency and then it blew up in our face, so I had to revert it, bummer. It will come in later, through that subsystem, I guess. New drivers: - New driver for the Microchip Serial GPIO "SGPIO". - Qualcomm SM8250 LPASS (Low Power Audio Subsystem) GPIO driver. New subdrivers: - Intel Lakefield subdriver. - Intel Elkhart Lake subdriver. - Intel Alder Lake-S subdriver. - Qualcomm MSM8953 subdriver. - Qualcomm SDX55 subdriver. - Qualcomm SDX55 PMIC subdriver. - Ocelot Luton SoC subdriver. - Ocelot Serval SoC subdriver. Modularization: - The Meson driver can now be built as modules. - The Qualcomm driver(s) can now be built as modules. Incremental improvements: - The Intel driver now supports pin configuration for GPIO-related configurations. - A bunch of Renesas PFC drivers have been augmented with support for QSPI pins, groups and functions. - Non-critical fixes to the irq handling in the Allwinner Sunxi driver" * tag 'pinctrl-v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits) pinctrl/spear: simplify the return expression of spear300_pinctrl_probe() pinctrl: mediatek: simplify the return expression of mtk_pinconf_bias_disable_set_rev1() dt-bindings: pinctrl: pinctrl-microchip-sgpio: Add irq support pinctrl: pinctrl-microchip-sgpio: Add irq support (for sparx5) pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings pinctrl: qcom-pmic-gpio: Add support for pmx55 dt-bindings: pinctrl: qcom-pmic-gpio: Add pmx55 support pinctrl: pinctrl-microchip-sgpio: Mark some symbols with static keyword pinctrl: at91-pio4: Make PINCTRL_AT91PIO4 depend on HAS_IOMEM to fix build error pinctrl: mtk: Fix low level output voltage issue pinctrl: falcon: add missing put_device() call in pinctrl_falcon_probe() pinctrl: actions: pinctrl-s500: Constify s500_padinfo[] pinctrl: pinctrl-microchip-sgpio: Add OF config dependency pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO dt-bindings: pinctrl: Add bindings for pinctrl-microchip-sgpio driver pinctrl: at91-pio4: add support for fewer lines on last PIO bank pinctrl: sunxi: Always call chained_irq_{enter, exit} in sunxi_pinctrl_irq_handler pinctrl: sunxi: Mark the irq bank not found in sunxi_pinctrl_irq_handler() with WARN_ON pinctrl: sunxi: fix irq bank map for the Allwinner A100 pin controller ...
2020-11-10pinctrl: ingenic: Add lcd-8bit group for JZ4770Paul Cercueil
Add the "lcd-8bit" group to the "lcd" function. As "lcd-24bit" is a superset of "lcd-8bit", in theory the former could be modified to only contain the pins not already included in "lcd-8bit", just like how it's done for the JZ4740 and JZ4725B platforms. However, we can't do that without breaking Device Tree ABI, so in that case we have no choice but to have two groups containing the same pins. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20201101090104.5088-3-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-11-10pinctrl: ingenic: Get rid of repetitive dataPaul Cercueil
Abuse the pin function pointer to store the pin function value directly, when all the pins of a group have the same function value. Now when the pointer value is <= 3 (unsigned), the pointer value is used as the pin function; otherwise it is used as a regular pointer. This drastically reduces the number of pin function tables needed, and drops .data usage by about 2 KiB. Additionally, the few pin function tables that are still around now contain u8 instead of int, since the largest number that will be stored is 3. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20201101090104.5088-2-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-10-28pinctrl: ingenic: Fix invalid SSI pinsPaul Cercueil
The values for the SSI pins on GPIO chips D and E were off by 0x20. Fixes: d3ef8c6b2286 ("pinctrl: Ingenic: Add SSI pins support for JZ4770 and JZ4780.") Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reported-by: Artur Rojek <contact@artur-rojek.eu> Link: https://lore.kernel.org/r/20201010192509.9098-1-paul@crapouillou.net Reviewed-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-09-29pinctrl: Ingenic: Add I2S pins support for Ingenic SoCs.周琰杰 (Zhou Yanjie)
1.Add I2S pins support for the JZ4780 SoC. 2.Add I2S pins support for the X1000 SoC. 3.Add I2S pins support for the X1500 SoC. 4.Add I2S pins support for the X1830 SoC. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200913065836.12156-4-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-09-29pinctrl: Ingenic: Correct the pullup and pulldown parameters of JZ4780.周琰杰 (Zhou Yanjie)
Correct the pullup and pulldown parameters of JZ4780 to make them consistent with the parameters on the datasheet. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200913065836.12156-3-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-09-29pinctrl: Ingenic: Add SSI pins support for JZ4770 and JZ4780.周琰杰 (Zhou Yanjie)
Add SSI pins support for the JZ4770 SoC and the JZ4780 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200913065836.12156-2-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-07-07pinctrl: ingenic: Properly detect GPIO direction when configured for IRQPaul Cercueil
The PAT1 register contains information about the IRQ type (edge/level) for input GPIOs with IRQ enabled, and the direction for non-IRQ GPIOs. So it makes sense to read it only if the GPIO has no interrupt configured, otherwise input GPIOs configured for level IRQs are misdetected as output GPIOs. Fixes: ebd6651418b6 ("pinctrl: ingenic: Implement .get_direction for GPIO chips") Reported-by: João Henrique <johnnyonflame@hotmail.com> Signed-off-by: Paul Cercueil <paul@crapouillou.net> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200622214548.265417-2-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-07-07pinctrl: ingenic: Enhance support for IRQ_TYPE_EDGE_BOTHPaul Cercueil
Ingenic SoCs don't natively support registering an interrupt for both rising and falling edges. This has to be emulated in software. Until now, this was emulated by switching back and forth between IRQ_TYPE_EDGE_RISING and IRQ_TYPE_EDGE_FALLING according to the level of the GPIO. While this worked most of the time, when used with GPIOs that need debouncing, some events would be lost. For instance, between the time a falling-edge interrupt happens and the interrupt handler configures the hardware for rising-edge, the level of the pin may have already risen, and the rising-edge event is lost. To address that issue, instead of switching back and forth between IRQ_TYPE_EDGE_RISING and IRQ_TYPE_EDGE_FALLING, we now switch back and forth between IRQ_TYPE_LEVEL_LOW and IRQ_TYPE_LEVEL_HIGH. Since we always switch in the interrupt handler, they actually permit to detect level changes. In the example above, if the pin level rises before switching the IRQ type from IRQ_TYPE_LEVEL_LOW to IRQ_TYPE_LEVEL_HIGH, a new interrupt will raise as soon as the handler exits, and the rising-edge event will be properly detected. Fixes: e72394e2ea19 ("pinctrl: ingenic: Merge GPIO functionality") Reported-by: João Henrique <johnnyonflame@hotmail.com> Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: João Henrique <johnnyonflame@hotmail.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200622214548.265417-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-06-20pinctrl: ingenic: Add ingenic,jz4725b-gpio compatible stringPaul Cercueil
Add a compatible string to support the GPIO chips on the JZ4725B SoC. There was already a compatible string for the pinctrl node, but not for the individual GPIO chip nodes. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200612120609.12730-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-06-16pinctrl: ingenic: Add NAND FRE/FWE pins for JZ4740Paul Cercueil
Add the FRE/FWE pins for the JZ4740. These pins must be in function #0 for the NAND to work. The reason it worked before was because the bootloader did set these pins to the correct function beforehand. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200607174243.2361664-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-05-12pinctrl: ingenic: Add irq_{request,release}_resources callbacksPaul Cercueil
These are called when a GPIO is to be used as IRQ. Without these custom callbacks, when an interrupt is requested directly and not through gpiod_to_irq(), the request fails because the GPIO is not necesarily in input mode. These callbacks simply enforce that the requested GPIO is in input mode. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200503164549.163884-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-04-04Merge tag 'gpio-v5.7-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull GPIO updates from Linus Walleij: "This is the bulk of GPIO development for the v5.7 kernel cycle. Core and userspace API: - The userspace API KFIFOs have been imoproved with locks that do not block interrupts. This makes us better at getting events to userspace without blocking or disturbing new events arriving in the same time. This was reviewed by the KFIFO maintainer Stefani. This is a generic improvement which paves the road for similar improvements in other subsystems. - We provide a new ioctl() for monitoring changes in the line information, such as when multiple clients are taking lines and giving them back, possibly reconfiguring them in the process: we can now monitor that and not get stuck with stale static information. - An example tool 'gpio-watch' is provided to showcase this functionality. - Timestamps for events are switched to ktime_get_ns() which is monotonic. We previously had a 'realtime' stamp which could move forward and *backward* in time, which probably would just cause silent bugs and weird behaviour. In the long run we see two relevant timestamps: ktime_get_ns() or the timestamp sometimes provided by the GPIO hardware itself, if that exists. - Device Tree overlay support for GPIO hogs. On systems that load overlays, these overlays can now contain hogs, and will then be respected. - Handle pin control interaction with nonexisting pin ranges in the GPIO library core instead of in the individual drivers. New drivers: - New driver for the Mellanox BlueField 2 GPIO controller. Driver improvements: - Introduce the BGPIOF_NO_SET_ON_INPUT flag to the generic MMIO GPIO library and use this flag in the MT7621 driver. - Texas Instruments OMAP CPU power management improvements, such as blocking of idle on pending GPIO interrupts" * tag 'gpio-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (59 commits) Revert "gpio: eic-sprd: Use devm_platform_ioremap_resource()" pinctrl: Unconditionally assign .request()/.free() gpio: Unconditionally assign .request()/.free() gpio: export of_pinctrl_get to modules pinctrl: Define of_pinctrl_get() dummy for !PINCTRL gpio: Rename variable in core APIs gpio: Avoid using pin ranges with !PINCTRL gpiolib: Remove unused gpio_chip parameter from gpio_set_bias() gpiolib: Pass gpio_desc to gpio_set_config() gpiolib: Introduce gpiod_set_config() tools: gpio: Fix out-of-tree build regression gpio: gpiolib: fix a doc warning gpio: tegra186: Add Tegra194 pin ranges for GG.0 and GG.1 gpio: tegra186: Add support for pin ranges gpio: Support GPIO controllers without pin-ranges ARM: integrator: impd1: Use GPIO_LOOKUP() helper macro gpio: brcmstb: support gpio-line-names property tools: gpio: Fix typo in gpio-utils tools: gpio-hammer: Apply scripts/Lindent and retain good changes gpiolib: gpio_name_to_desc: factor out !name check ...
2020-04-02pinctrl: Unconditionally assign .request()/.free()Thierry Reding
The gpiochip_generic_request() and gpiochip_generic_free() functions can now deal properly with chips that don't have any pin-ranges defined, so they can be assigned unconditionally. Suggested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200401200527.2982450-2-thierry.reding@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-03-02pinctrl: ingenic: add hdmi-ddc pin control groupPaul Boddie
Signed-off-by: Paul Boddie <paul@boddie.org.uk> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Link: https://lore.kernel.org/r/010d6ad3473fb4b1f1041888a071796180cdd838.1582913973.git.hns@goldelico.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-02-21pinctrl: ingenic: Improve unreachable code generationJosh Poimboeuf
In the second loop of ingenic_pinconf_set(), it annotates the switch default case as unreachable(). The annotation is technically correct, because that same case would have resulted in an early function return in the previous loop. However, the compiled code is suboptimal. GCC seems to work extra hard to ensure that the unreachable code path triggers undefined behavior. The function would fall through to start executing whatever function happens to be next in the compilation unit. This is problematic because: a) it adds unnecessary 'ensure undefined behavior' logic, and corresponding i-cache footprint; and b) it's less robust -- if a bug were to be introduced, falling through to the next function would be catastrophic. Yet another issue is that, while objtool normally understands unreachable() annotations, there's one special case where it doesn't: when the annotation occurs immediately after a 'ret' instruction. That happens to be the case here because unreachable() is immediately before the return. Remove the unreachable() annotation and replace it with a comment. This simplifies the code generation and changes the unreachable error path to just silently return instead of corrupting execution. This fixes the following objtool warning: drivers/pinctrl/pinctrl-ingenic.o: warning: objtool: ingenic_pinconf_set() falls through to next function ingenic_pinconf_group_set() Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com> Link: https://lore.kernel.org/r/bc20fdbcb826512cf76b7dfd0972740875931b19.1582212881.git.jpoimboe@redhat.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-02-21pinctrl: Ingenic: Add missing parts for X1830.周琰杰 (Zhou Yanjie)
Add lcd pinctrl driver for X1830. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/1581851828-3493-3-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-02-21pinctrl: Use new GPIO_LINE_DIRECTIONMatti Vaittinen
Use newly added GPIO defines GPIO_LINE_DIRECTION_IN and GPIO_LINE_DIRECTION_OUT instead of using hard-coded 1 and 0. Main benefit is to make it easier to see which values mean IN and which OUT. As a side effect this helps GPIO framework to change the direction defines to something else if ever needed. Please note that return value from get_direction call on pinctrl-axp209 driver was changed. Previously pinctrl-axp209 might have returned value 2 for direction INPUT. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Reported-by: kbuild test robot <lkp@intel.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Link: https://lore.kernel.org/r/20200214135712.GA14557@localhost.localdomain Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-07pinctrl: ingenic: Use devm_platform_ioremap_resource()Paul Cercueil
Use devm_platform_ioremap_resource() instead of platform_get_resource + devm_ioremap_resource. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200106232711.559727-6-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-07pinctrl: ingenic: Factorize irq_set_type functionPaul Cercueil
Simplify the code of the driver's irq_set_type() function by doing some factorization. The behaviour is unchanged. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200106232711.559727-5-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-07pinctrl: ingenic: Remove duplicated ingenic_chip_info structuresPaul Cercueil
Until there is the need to handle the JZ4760B and X1000E differently there is no reason to use a separate ingenic_chip_info since the data it contains is the same than for the JZ4760 and X1000 respectively. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200106232711.559727-4-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-07pinctrl: ingenic: Put ingenic_chip_info pointer in match dataPaul Cercueil
Instead of passing a numeric ID as match data, and retrieve a pointer to the ingenic_chip_info structure in an ugly succession of if/else in the probe function, get the pointer to the ingenic_chip_info structure directly from the match data, and store the numeric ID inside the ingenic_chip_info structure. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200106232711.559727-3-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-07pinctrl: ingenic: Remove platform ID tablePaul Cercueil
We enforce devicetree support in the Kconfig and all Ingenic boards without exception probe their drivers from devicetree. The code path to probe the driver from arch code can then be considered as dead code and removed. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200106232711.559727-2-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-06pinctrl: Ingenic: Add pinctrl driver for X1830.周琰杰 (Zhou Yanjie)
Add support for probing the pinctrl-ingenic driver on the X1830 Soc from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/1576426864-35348-7-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-06pinctrl: Ingenic: Introduce reg_offset and use it instead hard code.周琰杰 (Zhou Yanjie)
Introduce "reg_offset", use it instead hard code "0x100", it will also be used for subsequent X1830 pinctrl driver. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/1576426864-35348-5-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-06pinctrl: Ingenic: Add missing parts for X1000 and X1500.周琰杰 (Zhou Yanjie)
1.Add pinctrl drivers for the SPI flash controller (SFC) of X1000 and X1500. 2.Add pinctrl driver for the synchronous serial interface (SSI) of X1000. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/1576426864-35348-4-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-06pinctrl: Ingenic: Fix bugs in X1000 and X1500.周琰杰 (Zhou Yanjie)
1.Fix the pullup parameter of X1000. 2.X1000 and X1500 have only one set of uart1 hwflow pin mapping, so modify "uart1_hwflow_d" to "uart1_hwflow". 3.X1000 has only one set of mmc1 pin mapping, so modify "mmc1-1bit-e/mmc1-4bit-e" to "mmc1-1bit/mmc1-4bit". 4.X1000 has only one regular externel memory controller that does not support nand flash, so change "nemc_" to "emc_". 5.X1500 has only one set of mmc, so modify "mmc0_" to "mmc_". Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/1576426864-35348-3-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-16pinctrl: ingenic: Fixup PIN_CONFIG_OUTPUT configPaul Cercueil
JZ4760 support was added in parallel of the previous patch so this one slipped through. The first SoC to use the new register is the JZ4760 and not the JZ4770, fix it here. Fixes: 7009d046a601 ("pinctrl: ingenic: Handle PIN_CONFIG_OUTPUT config") Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20191210164446.53912-1-paul@crapouillou.net [Folded into OF dependency] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-21pinctrl: ingenic: Add OTG VBUS pin for the JZ4770Paul Cercueil
Add pin mux configuration for the OTG VBUS pin of the JZ4770. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20191119155211.102527-2-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-21pinctrl: ingenic: Handle PIN_CONFIG_OUTPUT configPaul Cercueil
This makes the driver support the 'output-low' and 'output-high' devicetree properties in gpio-hog sub-nodes. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20191119155211.102527-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16pinctrl: ingenic: Pass irqchip when adding gpiochipLinus Walleij
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Thierry Reding <thierry.reding@gmail.com> Acked-by: Zhou Yanjie <zhouyanjie@zoho.com> Acked-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191001133209.17164-1-linus.walleij@linaro.org
2019-07-29pinctrl: Ingenic: Add pinctrl driver for X1500.Zhou Yanjie
Add support for probing the pinctrl-ingenic driver on the X1500 Soc from Ingenic. Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com> Link: https://lore.kernel.org/r/1563076436-5338-7-git-send-email-zhouyanjie@zoho.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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