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2021-04-29Merge tag 'net-next-5.13' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Jakub Kicinski: "Core: - bpf: - allow bpf programs calling kernel functions (initially to reuse TCP congestion control implementations) - enable task local storage for tracing programs - remove the need to store per-task state in hash maps, and allow tracing programs access to task local storage previously added for BPF_LSM - add bpf_for_each_map_elem() helper, allowing programs to walk all map elements in a more robust and easier to verify fashion - sockmap: support UDP and cross-protocol BPF_SK_SKB_VERDICT redirection - lpm: add support for batched ops in LPM trie - add BTF_KIND_FLOAT support - mostly to allow use of BTF on s390 which has floats in its headers files - improve BPF syscall documentation and extend the use of kdoc parsing scripts we already employ for bpf-helpers - libbpf, bpftool: support static linking of BPF ELF files - improve support for encapsulation of L2 packets - xdp: restructure redirect actions to avoid a runtime lookup, improving performance by 4-8% in microbenchmarks - xsk: build skb by page (aka generic zerocopy xmit) - improve performance of software AF_XDP path by 33% for devices which don't need headers in the linear skb part (e.g. virtio) - nexthop: resilient next-hop groups - improve path stability on next-hops group changes (incl. offload for mlxsw) - ipv6: segment routing: add support for IPv4 decapsulation - icmp: add support for RFC 8335 extended PROBE messages - inet: use bigger hash table for IP ID generation - tcp: deal better with delayed TX completions - make sure we don't give up on fast TCP retransmissions only because driver is slow in reporting that it completed transmitting the original - tcp: reorder tcp_congestion_ops for better cache locality - mptcp: - add sockopt support for common TCP options - add support for common TCP msg flags - include multiple address ids in RM_ADDR - add reset option support for resetting one subflow - udp: GRO L4 improvements - improve 'forward' / 'frag_list' co-existence with UDP tunnel GRO, allowing the first to take place correctly even for encapsulated UDP traffic - micro-optimize dev_gro_receive() and flow dissection, avoid retpoline overhead on VLAN and TEB GRO - use less memory for sysctls, add a new sysctl type, to allow using u8 instead of "int" and "long" and shrink networking sysctls - veth: allow GRO without XDP - this allows aggregating UDP packets before handing them off to routing, bridge, OvS, etc. - allow specifing ifindex when device is moved to another namespace - netfilter: - nft_socket: add support for cgroupsv2 - nftables: add catch-all set element - special element used to define a default action in case normal lookup missed - use net_generic infra in many modules to avoid allocating per-ns memory unnecessarily - xps: improve the xps handling to avoid potential out-of-bound accesses and use-after-free when XPS change race with other re-configuration under traffic - add a config knob to turn off per-cpu netdev refcnt to catch underflows in testing Device APIs: - add WWAN subsystem to organize the WWAN interfaces better and hopefully start driving towards more unified and vendor- independent APIs - ethtool: - add interface for reading IEEE MIB stats (incl. mlx5 and bnxt support) - allow network drivers to dump arbitrary SFP EEPROM data, current offset+length API was a poor fit for modern SFP which define EEPROM in terms of pages (incl. mlx5 support) - act_police, flow_offload: add support for packet-per-second policing (incl. offload for nfp) - psample: add additional metadata attributes like transit delay for packets sampled from switch HW (and corresponding egress and policy-based sampling in the mlxsw driver) - dsa: improve support for sandwiched LAGs with bridge and DSA - netfilter: - flowtable: use direct xmit in topologies with IP forwarding, bridging, vlans etc. - nftables: counter hardware offload support - Bluetooth: - improvements for firmware download w/ Intel devices - add support for reading AOSP vendor capabilities - add support for virtio transport driver - mac80211: - allow concurrent monitor iface and ethernet rx decap - set priority and queue mapping for injected frames - phy: add support for Clause-45 PHY Loopback - pci/iov: add sysfs MSI-X vector assignment interface to distribute MSI-X resources to VFs (incl. mlx5 support) New hardware/drivers: - dsa: mv88e6xxx: add support for Marvell mv88e6393x - 11-port Ethernet switch with 8x 1-Gigabit Ethernet and 3x 10-Gigabit interfaces. - dsa: support for legacy Broadcom tags used on BCM5325, BCM5365 and BCM63xx switches - Microchip KSZ8863 and KSZ8873; 3x 10/100Mbps Ethernet switches - ath11k: support for QCN9074 a 802.11ax device - Bluetooth: Broadcom BCM4330 and BMC4334 - phy: Marvell 88X2222 transceiver support - mdio: add BCM6368 MDIO mux bus controller - r8152: support RTL8153 and RTL8156 (USB Ethernet) chips - mana: driver for Microsoft Azure Network Adapter (MANA) - Actions Semi Owl Ethernet MAC - can: driver for ETAS ES58X CAN/USB interfaces Pure driver changes: - add XDP support to: enetc, igc, stmmac - add AF_XDP support to: stmmac - virtio: - page_to_skb() use build_skb when there's sufficient tailroom (21% improvement for 1000B UDP frames) - support XDP even without dedicated Tx queues - share the Tx queues with the stack when necessary - mlx5: - flow rules: add support for mirroring with conntrack, matching on ICMP, GTP, flex filters and more - support packet sampling with flow offloads - persist uplink representor netdev across eswitch mode changes - allow coexistence of CQE compression and HW time-stamping - add ethtool extended link error state reporting - ice, iavf: support flow filters, UDP Segmentation Offload - dpaa2-switch: - move the driver out of staging - add spanning tree (STP) support - add rx copybreak support - add tc flower hardware offload on ingress traffic - ionic: - implement Rx page reuse - support HW PTP time-stamping - octeon: support TC hardware offloads - flower matching on ingress and egress ratelimitting. - stmmac: - add RX frame steering based on VLAN priority in tc flower - support frame preemption (FPE) - intel: add cross time-stamping freq difference adjustment - ocelot: - support forwarding of MRP frames in HW - support multiple bridges - support PTP Sync one-step timestamping - dsa: mv88e6xxx, dpaa2-switch: offload bridge port flags like learning, flooding etc. - ipa: add IPA v4.5, v4.9 and v4.11 support (Qualcomm SDX55, SM8350, SC7280 SoCs) - mt7601u: enable TDLS support - mt76: - add support for 802.3 rx frames (mt7915/mt7615) - mt7915 flash pre-calibration support - mt7921/mt7663 runtime power management fixes" * tag 'net-next-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (2451 commits) net: selftest: fix build issue if INET is disabled net: netrom: nr_in: Remove redundant assignment to ns net: tun: Remove redundant assignment to ret net: phy: marvell: add downshift support for M88E1240 net: dsa: ksz: Make reg_mib_cnt a u8 as it never exceeds 255 net/sched: act_ct: Remove redundant ct get and check icmp: standardize naming of RFC 8335 PROBE constants bpf, selftests: Update array map tests for per-cpu batched ops bpf: Add batched ops support for percpu array bpf: Implement formatted output helpers with bstr_printf seq_file: Add a seq_bprintf function sfc: adjust efx->xdp_tx_queue_count with the real number of initialized queues net:nfc:digital: Fix a double free in digital_tg_recv_dep_req net: fix a concurrency bug in l2tp_tunnel_register() net/smc: Remove redundant assignment to rc mpls: Remove redundant assignment to err llc2: Remove redundant assignment to rc net/tls: Remove redundant initialization of record rds: Remove redundant assignment to nr_sig dt-bindings: net: mdio-gpio: add compatible for microchip,mdio-smi0 ...
2021-04-16phy: Revert "phy: ti: j721e-wiz: add missing of_node_put"Vinod Koul
This reverts commit 00f2e6f668b0 ("phy: ti: j721e-wiz: add missing of_node_put") as it erroneously adds the of_node_put() as incorrect place. Reported-by: Junlin Yang <yangjunlin@yulong.com> Link: https://lore.kernel.org/r/20210408062914.3813102-1-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-04-16phy: ti: j721e-wiz: Add missing include linux/slab.hShixin Liu
When compiling with CONFIG_PHY_J721E_WIZ, Hulk Robot reported: drivers/phy/ti/phy-j721e-wiz.c: In function ‘wiz_mux_clk_register’: drivers/phy/ti/phy-j721e-wiz.c:659:17: error: implicit declaration of function ‘kzalloc’; did you mean ‘vzalloc’? [-Werror=implicit-function-declaration] 659 | parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); | ^~~~~~~ | vzalloc drivers/phy/ti/phy-j721e-wiz.c:659:15: warning: assignment to ‘const char **’ from ‘int’ makes pointer from integer without a cast [-Wint-conversion] 659 | parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); | ^ drivers/phy/ti/phy-j721e-wiz.c:697:2: error: implicit declaration of function ‘kfree’; did you mean ‘vfree’? [-Werror=implicit-function-declaration] 697 | kfree(parent_names); | ^~~~~ | vfre Fixes: 040cbe768731 ("phy: ti: j721e-wiz: Model the internal clocks without device tree input") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Shixin Liu <liushixin2@huawei.com> Link: https://lore.kernel.org/r/20210408012829.432938-1-liushixin2@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-04-16phy: phy-twl4030-usb: Fix possible use-after-free in twl4030_usb_remove()Yang Yingliang
This driver's remove path calls cancel_delayed_work(). However, that function does not wait until the work function finishes. This means that the callback function may still be running after the driver's remove function has finished, which would result in a use-after-free. Fix by calling cancel_delayed_work_sync(), which ensures that the work is properly cancelled, no longer running, and unable to re-schedule itself. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20210407092716.3270248-1-yangyingliang@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-04-06time64.h: Consolidated PSEC_PER_SEC definitionAndy Shevchenko
We have currently three users of the PSEC_PER_SEC each of them defining it individually. Instead, move it to time64.h to be available for everyone. There is a new user coming with the same constant in use. It will also make its life easier. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-06phy: fix resource_size.cocci warningskernel test robot
drivers/phy/microchip/sparx5_serdes.c:2440:54-57: ERROR: Missing resource_size with iores Use resource_size function on resource object instead of explicit computation. Generated by: scripts/coccinelle/api/resource_size.cocci Fixes: 2ff8a1eeb5aa ("phy: Add Sparx5 ethernet serdes PHY driver") CC: Steen Hegelund <steen.hegelund@microchip.com> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20210318232844.GA65886@63b0c5462fda Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-06phy: Sparx5 Eth SerDes: Use direct register operationsSteen Hegelund
Use direct register operations instead of a table of register information to lower the stack usage. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20210329141309.612459-2-steen.hegelund@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-06phy: hisilicon: Use the correct HiSilicon copyrightHao Fang
s/Hisilicon/HiSilicon/g. It should use capital S, according to the official website. Signed-off-by: Hao Fang <fanghao11@huawei.com> Link: https://lore.kernel.org/r/1617278537-26102-1-git-send-email-fanghao11@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-06phy: marvell: phy-mvebu-cp11i-utmi needs USB_COMMONRandy Dunlap
When USB and USB_COMMON are not enabled, phy-mvebu-cp110-utmi suffers a build error due to a missing interface that is provided by CONFIG_USB_COMMON, so make the driver depend on USB_COMMON. ld: drivers/phy/marvell/phy-mvebu-cp110-utmi.o: in function `mvebu_cp110_utmi_phy_probe': phy-mvebu-cp110-utmi.c:(.text+0x152): undefined reference to `of_usb_get_dr_mode_by_phy' Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: linux-phy@lists.infradead.org Link: https://lore.kernel.org/r/20210401210045.23525-1-rdunlap@infradead.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: qcom-qmp: add support for sm8250-usb3-dp phyDmitry Baryshkov
Add support for QMP V4 Combo USB3+DP PHY (for SM8250 platform). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210331151614.3810197-6-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: qcom-qmp: rename common registersDmitry Baryshkov
A plenty of DP PHY registers are common between V3 and V4. To simplify V4 code, rename all common registers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210331151614.3810197-5-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: qcom-qmp: move DP functions to callbacksDmitry Baryshkov
In preparation to adding support for V4 DP PHY move DP functions to callbacks at struct qmp_phy_cfg. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210331151614.3810197-4-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: ti: j721e-wiz: Configure 'p_standard_mode' only for DP/QSGMIIKishon Vijay Abraham I
Configure 'p_standard_mode' only for DP/QSGMII as for other modes it's not used as per the programming sequence. Add "continue" in the else to prevent random value from being written to p_standard_mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210331131417.15596-1-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: zynqmp: Handle the clock enable/disable properlyManish Narani
The current driver is not handling the clock enable/disable operations properly. The clocks need to be handled correctly by enabling or disabling at appropriate places. This patch adds code to handle the same. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/1616588325-95602-1-git-send-email-manish.narani@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: microchip: PHY_SPARX5_SERDES should depend on ARCH_SPARX5Geert Uytterhoeven
The Microchip Sparx5 SerDes PHY is present only Microchip Sparx5 SoCs. Hence add a dependency on ARCH_SPARX5, to prevent asking the user about this driver when configuring a kernel without support for Sparx5 SoCs. Fixes: 2ff8a1eeb5aa8bb4 ("phy: Add Sparx5 ethernet serdes PHY driver") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210331081937.367408-1-geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence-torrent: Add delay for PIPE clock to be stableKishon Vijay Abraham I
The Torrent spec specifies delay of 660.5us after phy_reset is asserted by the controller. To be on the safe side provide a delay of 5ms to 10ms in ->phy_on() callback where the SERDES is already configured in bootloader. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210330110138.24356-6-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence-torrent: Explicitly request exclusive reset controlKishon Vijay Abraham I
No functional change. Since the reset controls obtained in Torrent is exclusively used by the Torrent device, use exclusive reset control request API calls. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210330110138.24356-5-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence-torrent: Do not configure SERDES if it's already configuredKishon Vijay Abraham I
Do not configure torrent SERDES if it's already configured. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210330110138.24356-4-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence-torrent: Group reset APIs and clock APIsKishon Vijay Abraham I
No functional change intended. Group reset APIs and clock APIs in preparation for adding support to skip configuration if the SERDES is already configured by bootloader. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210330110138.24356-3-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: ti: j721e-wiz: Do not configure wiz if its already configuredFaiz Abbas
Serdes lanes might be shared between multiple cores in some usecases and its not possible to lock PLLs for both the lanes independently by the two cores. This requires a bootloader to configure both the lanes at early boot time. To handle this case, skip all configuration if any of the lanes has already been enabled. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210330110138.24356-2-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Enable pll_cmnlc and pll_cmnlc1 clocksKishon Vijay Abraham I
Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them. This will enable REFRCV/1 in case the pll_cmnlc/1 takes input from REFRCV/1 respectively. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-14-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)Kishon Vijay Abraham I
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as clocks so that it's possible to select one of these two inputs from device tree. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-13-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callbackKishon Vijay Abraham I
commit 44d30d622821 ("phy: cadence: Add driver for Sierra PHY") enabled the clock in probe and failed to disable in remove callback. Add missing clk_disable_unprepare() in cdns_sierra_phy_remove(). Fixes: 44d30d622821 ("phy: cadence: Add driver for Sierra PHY") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210319124128.13308-11-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy"Kishon Vijay Abraham I
Instead of having separate structure members for each input clock, add an array for the input clocks within "struct cdns_sierra_phy". This is in preparation for adding more input clocks required for supporting additional clock combination. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-10-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence-torrent: Use a common header file for Cadence SERDESKishon Vijay Abraham I
No functional change. In order to have a single header file for all Cadence SERDES move phy-cadence-torrent.h to phy-cadence.h. This is in preparation for adding Cadence Sierra SERDES specific macros. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210319124128.13308-9-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Explicitly request exclusive reset controlKishon Vijay Abraham I
No functional change. Since the reset controls obtained in Sierra is exclusively used by the Sierra device, use exclusive reset control request API calls. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20210319124128.13308-8-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Move all reset_control_get*() to a separate functionKishon Vijay Abraham I
No functional change. Group devm_reset_control_get() and devm_reset_control_get_optional() to a separate function. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20210319124128.13308-7-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Move all clk_get_*() to a separate functionKishon Vijay Abraham I
No functional change. Group all devm_clk_get_optional() to a separate function. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-6-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link" subnodeKishon Vijay Abraham I
"serdes" node (child node of WIZ) can have sub-nodes for representing links or it can have sub-nodes for representing the various clocks within the serdes. Instead of trying to read "reg" from every child node used for assigning "lane_phy_type", read only if the child node's name is "phy" or "link" subnode. Ideally all PHY dt nodes should have node name as "phy", however existing devicetree used "link" as subnode. So in order to maintain old DT compatibility get PHY properties for "phy" or "link" subnode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210319124128.13308-5-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodesKishon Vijay Abraham I
Cadence Sierra PHY driver registers PHY using devm_phy_create() for all sub-nodes of Sierra device tree node. However Sierra device tree node can have sub-nodes for the various clocks in addtion to the PHY. Use devm_phy_create() only for nodes with name "phy" (or "link" for old device tree) which represent the actual PHY. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-4-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: ti: j721e-wiz: Invoke wiz_init() before of_platform_device_create()Kishon Vijay Abraham I
Invoke wiz_init() before configuring anything else in Sierra/Torrent (invoked as part of of_platform_device_create()). wiz_init() resets the SERDES device and any configuration done in the probe() of Sierra/Torrent will be lost. In order to prevent SERDES configuration from getting reset, invoke wiz_init() immediately before invoking of_platform_device_create(). Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Cc: <stable@vger.kernel.org> # v5.10 Link: https://lore.kernel.org/r/20210319124128.13308-3-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Fix PHY power_on sequenceKishon Vijay Abraham I
Commit 44d30d622821d ("phy: cadence: Add driver for Sierra PHY") de-asserts PHY_RESET even before the configurations are loaded in phy_init(). However PHY_RESET should be de-asserted only after all the configurations has been initialized, instead of de-asserting in probe. Fix it here. Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Cc: <stable@vger.kernel.org> # v5.4+ Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20210319124128.13308-2-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: qcom-qmp: add hbr3_hbr2 voltage and premphasis swing tableKuogee Hsieh
Add hbr3_hbr2 voltage and premphasis swing table to support HBR3 link rate. Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1615914761-12300-1-git-send-email-khsieh@codeaurora.org Fixes: 52e013d0bffa ("phy: qcom-qmp: Add support for DP in USB3+DP combo phy") Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: ingenic: Fix a typo in ingenic_usb_phy_probe()Wei Yongjun
Fix the return value check typo which testing the wrong variable in ingenic_usb_phy_probe(). Fixes: 31de313dfdcf ("PHY: Ingenic: Add USB PHY driver using generic PHY framework.") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Acked-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210305034933.3240914-1-weiyongjun1@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: ralink: phy-mt7621-pci: fix return value check in mt7621_pci_phy_probe()Wei Yongjun
Fix the return value check which testing the wrong variable in mt7621_pci_phy_probe(). Fixes: d87da32372a0 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210305034931.3237558-1-weiyongjun1@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: marvell: ARMADA375_USBCLUSTER_PHY should not default to y, unconditionallyGeert Uytterhoeven
Merely enabling CONFIG_COMPILE_TEST should not enable additional code. To fix this, restrict the automatic enabling of ARMADA375_USBCLUSTER_PHY to MACH_ARMADA_375, and ask the user in case of compile-testing. Fixes: eee47538ec1f2619 ("phy: add support for USB cluster on the Armada 375 SoC") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210208150252.424706-1-geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: ti: j721e-wiz: add missing call to of_node_put()Yang Li
In one of the error paths of the for_each_child_of_node() loop in of_property_read_u32, add missing call to of_node_put(). Fix the following coccicheck warning: ./drivers/phy/ti/phy-j721e-wiz.c:786:1-23: WARNING: Function "for_each_child_of_node" should have of_node_put() before return around line 795. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/1614244674-66556-1-git-send-email-yang.lee@linux.alibaba.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: ralink: phy-mt7621-pci: fix XTAL bitmaskSergio Paracuellos
When this was rewriten to get mainlined and start to use 'linux/bitfield.h' headers, XTAL_MASK was wrong. It must mask three bits but only two were used. Hence properly fix it to make things work. Fixes: d87da32372a0 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY") Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210302105412.16221-1-sergio.paracuellos@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: cadence-torrent: Update PCIe + USB config for correct PLL1 clockSwapnil Jakhade
Update PCIe + USB register sequences for correct PLL1 clock configuration. Also, update sequences for other USB configurations with dependent changes. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/1614838096-32291-5-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: cadence-torrent: Update SGMII/QSGMII configuration specific to TIKishon Vijay Abraham I
Update SGMII/QSGMII configuration specific to TI. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1614838096-32291-4-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: ti: j721e-wiz: Add support for configuring QSGMIIKishon Vijay Abraham I
Configure MAC clock dividers required for QSGMII to be functional. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1614838096-32291-3-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: cadence-torrent: Update PCIe + QSGMII config for correct PLL1 clockSwapnil Jakhade
For PCIe + QSGMII configuration where QSGMII was using PLL1 and was expecting 10GHz clock, configuration was giving 8GHz clock. Update register sequences to get correct PLL1 configuration. Also, update single link PCIe and single link SGMII/QSGMII configurations with related changes. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/1614838096-32291-2-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: cadence-torrent: Add support to drive refclk outKishon Vijay Abraham I
cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external reference clock. cmn_refclk_<p/m> can also be configured to output the reference clock. Model this derived reference clock as a "clock" so that platforms like AM642 EVM can enable it. This is used by PCIe to use the same refclk both in local SERDES and remote device. Add support here to drive refclk out. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210310120840.16447-7-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: ti: j721e-wiz: Enable reference clock output in cmn_refclk_<p/m>Kishon Vijay Abraham I
cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external reference clock. cmn_refclk_<p/m> can also be configured to output the reference clock. In order to drive the refclk out from the SERDES (Cadence Torrent), PHY_EN_REFCLK should be set in SERDES_RST of WIZ. Model PHY_EN_REFCLK as a clock, so that platforms like AM642 EVM can enable it. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210310120840.16447-6-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: ti: j721e-wiz: Model the internal clocks without device tree inputKishon Vijay Abraham I
commit 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") modeled the internal clocks depending on the subnodes that are populated in device tree. However recent discussions in the mailing list [1] suggested to just add #clock cells in the parent DT node and model the clocks within the driver. Model the mux clocks without device tree input for AM64x SoC. Don't remove the earlier design since DT nodes for J7200 and J721e are already upstreamed. [1] -> http://lore.kernel.org/r/20210108025943.GA1790601@robh.at.kernel.org Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210310120840.16447-5-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: ti: j721e-wiz: Configure full rate divider for AM64Kishon Vijay Abraham I
The frequency of the txmclk between PCIe and SERDES has changed to 250MHz from 500MHz. Configure full rate divider for AM64 accordingly. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210310120840.16447-4-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: ti: j721e-wiz: Delete "clk_div_sel" clk provider during cleanupKishon Vijay Abraham I
commit 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") modeled both MUX clocks and DIVIDER clocks in wiz. However during cleanup, it removed only the MUX clock provider. Remove the DIVIDER clock provider here. Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210310120840.16447-3-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: ti: j721e-wiz: Remove "regmap_field" from wiz_clk_{mux|div}_selKishon Vijay Abraham I
Both "struct wiz_clk_div_sel" and "struct wiz_clk_mux_sel" are static data that is common for all wiz instances. Including "struct regmap_field" for each of the wiz instances can yield undesirable results. Move "struct regmap_field" out of "struct wiz_clk_div_sel" and "struct wiz_clk_mux_sel" and make them point to constant data. So far no issues are observed since both these structures are not accessed outside the probe. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210310120840.16447-2-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30drivers: phy: add support for Armada CP110 UTMI PHYKonstantin Porotchkin
Add support for Marvell CP110 UTMI PHY driver allowing the USB2 port configuration independently from the boot loader setup. The CP110/CP115 dies have 2 UTMI PHYs that could be connected to two USB host controllers or to single USB device controller. Since there is only one USB device controller on die, only one of the UTMI PHYs could work in USB device mode. The CONFIG_PHY_MVEBU_CP110_UTMI should be enabled for usage of this driver. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Link: https://lore.kernel.org/r/20210307163343.25684-2-kostap@marvell.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-25phy: qualcomm: remove duplicate argumentZhang Yunkai
'HSUSB_CTRL_DPSEHV_CLAMP' in 'val' is duplicated. Signed-off-by: Zhang Yunkai <zhang.yunkai@zte.com.cn> Link: https://lore.kernel.org/r/20210319113612.494623-1-zhang.yunkai@zte.com.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 19:36:41 +0000