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path: root/drivers/net
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2019-08-29net: hns3: reduce the parameters of some functionsGuojia Liao
This patch simplifies parameters of some functions by deleting unused parameter. Signed-off-by: Guojia Liao <liaoguojia@huawei.com> Signed-off-by: Yufeng Mo <moyufeng@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-29net: hns3: modify base parameter of kstrtouint in hclge_dbg_dump_tm_mapHuazhong Tan
This patch replaces kstrtouint()'s patameter base with 0 in the hclge_dbg_dump_tm_mac(), which makes it more flexible. Also uses a macro to replace string "dump tm map", since it has been used multiple times. Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-29net: hns3: use macro instead of magic numberHuazhong Tan
This patch uses macro to replace some magic number. Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-29net: hns3: code optimization for debugfs related to "dump reg"Zhongzhu Liu
For making the code more readable, this patch uses a array to keep the information about the dumping register, and then uses it to parse the parameter cmd_buf which passing into hclge_dbg_dump_reg_cmd(). Also replaces parameter "base" of kstrtouint with 0 in the hclge_dbg_dump_reg_common(), which makes it more flexible. Signed-off-by: Zhongzhu Liu <liuzhongzhu@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-29dpaa2-eth: Add pause frame supportIoana Radulescu
Starting with firmware version MC10.18.0, we have support for L2 flow control. Asymmetrical configuration (Rx or Tx only) is supported, but not pause frame autonegotioation. Pause frame configuration is done via ethtool. By default, we start with flow control enabled on both Rx and Tx. Changes are propagated to hardware through firmware commands, using two flags (PAUSE, ASYM_PAUSE) to specify Rx and Tx pause configuration, as follows: PAUSE | ASYM_PAUSE | Rx pause | Tx pause ---------------------------------------- 0 | 0 | disabled | disabled 0 | 1 | disabled | enabled 1 | 0 | enabled | enabled 1 | 1 | enabled | disabled The hardware can automatically send pause frames when the number of buffers in the pool goes below a predefined threshold. Due to this, flow control is incompatible with Rx frame queue taildrop (both mechanisms target the case when processing of ingress frames can't keep up with the Rx rate; for large frames, the number of buffers in the pool may never get low enough to trigger pause frames as long as taildrop is enabled). So we set pause frame generation and Rx FQ taildrop as mutually exclusive. Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-29dpaa2-eth: Use stored link settingsIoana Radulescu
Whenever a link state change occurs, we get notified and save the new link settings in the device's private data. In ethtool get_link_ksettings, use the stored state instead of interrogating the firmware each time. Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-29dpaa2-eth: Remove support for changing link settingsIoana Radulescu
We only support fixed-link for now, so there is no point in offering users the option to change link settings via ethtool. Functionally there is no change, since firmware prevents us from changing link parameters anyway. Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-29iwlwifi: pcie: handle switching killer Qu B0 NICs to C0Luca Coelho
We need to use a different firmware for C0 versions of killer Qu NICs. Add structures for them and handle them in the if block that detects C0 revisions. Additionally, instead of having an inclusive check for QnJ devices, make the selection exclusive, so that switching to QnJ is the exception, not the default. This prevents us from having to add all the non-QnJ cards to an exclusion list. To do so, only go into the QnJ block if the device has an RF ID type HR and HW revision QnJ. Cc: stable@vger.kernel.org # 5.2 Signed-off-by: Luca Coelho <luciano.coelho@intel.com> Link: https://lore.kernel.org/r/20190821171732.2266-1-luca@coelho.fi Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2019-08-28mlxsw: spectrum_ptp: Add counters for GC eventsPetr Machata
On Spectrum-1, timestamped PTP packets and the corresponding timestamps need to be kept in caches until both are available, at which point they are matched up and packets forwarded as appropriate. However, not all packets will ever see their timestamp, and not all timestamps will ever see their packet. It is necessary to dispose of such abandoned entries, so a garbage collector was introduced in commit 5d23e4159772 ("mlxsw: spectrum: PTP: Garbage-collect unmatched entries"). If these GC events happen often, it is a sign of a problem. However because this whole mechanism is taking place behind the scenes, there is no direct way to determine whether garbage collection took place. Therefore to fix this, on Spectrum-1 only, expose four artificial ethtool counters for the GC events: GCd timestamps and packets, in TX and RX directions. Cc: Richard Cochran <richardcochran@gmail.com> Signed-off-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-28mlxsw: Bump firmware version to 13.2000.1886Ido Schimmel
The new version supports extended error reporting from firmware via a new TLV in the EMAD packet. Similar to netlink extended ack. It also fixes an issue in the PCI code that can result in false AER errors under high Tx rate. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-28mlxsw: spectrum: Prevent auto negotiation on number of lanesShalom Toledo
After 50G-1-lane and 100G-2-lanes link modes were introduced, the driver is facing situations in which the hardware auto negotiates not only on speed and type, but also on number of lanes. Prevent auto negotiation on number of lanes by allowing only port speeds that can be supported on a given port according to its width. Signed-off-by: Shalom Toledo <shalomt@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-28mlxsw: Remove 56G speed supportAmit Cohen
Commit 275e928f1911 ("mlxsw: spectrum: Prevent force of 56G") prevented the driver from setting a speed of 56G when auto-negotiation is off. This is the only speed supported by mlxsw that cannot be set when auto-negotiation is off, which makes it difficult to write generic tests. Further, the speed is not supported by newer ASICs such as Spectrum-2 and to the best of our knowledge it is not used by current users. Therefore, remove 56G support from mlxsw. Signed-off-by: Amit Cohen <amitc@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-28net: phy: force phy suspend when calling phy_stopJian Shen
Some ethernet drivers may call phy_start() and phy_stop() from ndo_open() and ndo_close() respectively. When network cable is unconnected, and operate like below: step 1: ifconfig ethX up -> ndo_open -> phy_start ->start autoneg, and phy is no link. step 2: ifconfig ethX down -> ndo_close -> phy_stop -> just stop phy state machine. This patch forces phy suspend even phydev->link is off. Signed-off-by: Jian Shen <shenjian15@huawei.com> Reviewed-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-28sky2: Disable MSI on yet another ASUS boards (P6Xxxx)Takashi Iwai
A similar workaround for the suspend/resume problem is needed for yet another ASUS machines, P6X models. Like the previous fix, the BIOS doesn't provide the standard DMI_SYS_* entry, so again DMI_BOARD_* entries are used instead. Reported-and-tested-by: SteveM <swm@swm1.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-28nfp: flower: handle neighbour events on internal portsJohn Hurley
Recent code changes to NFP allowed the offload of neighbour entries to FW when the next hop device was an internal port. This allows for offload of tunnel encap when the end-point IP address is applied to such a port. Unfortunately, the neighbour event handler still rejects events that are not associated with a repr dev and so the firmware neighbour table may get out of sync for internal ports. Fix this by allowing internal port neighbour events to be correctly processed. Fixes: 45756dfedab5 ("nfp: flower: allow tunnels to output to internal port") Signed-off-by: John Hurley <john.hurley@netronome.com> Reviewed-by: Simon Horman <simon.horman@netronome.com> Reviewed-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-28nfp: flower: prevent ingress block binds on internal portsJohn Hurley
Internal port TC offload is implemented through user-space applications (such as OvS) by adding filters at egress via TC clsact qdiscs. Indirect block offload support in the NFP driver accepts both ingress qdisc binds and egress binds if the device is an internal port. However, clsact sends bind notification for both ingress and egress block binds which can lead to the driver registering multiple callbacks and receiving multiple notifications of new filters. Fix this by rejecting ingress block bind callbacks when the port is internal and only adding filter callbacks for egress binds. Fixes: 4d12ba42787b ("nfp: flower: allow offloading of matches on 'internal' ports") Signed-off-by: John Hurley <john.hurley@netronome.com> Reviewed-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-28r8152: remove calling netif_napi_delHayes Wang
Remove unnecessary use of netif_napi_del. This also avoids to call napi_disable() after netif_napi_del(). Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-28Revert "r8152: napi hangup fix after disconnect"Hayes Wang
This reverts commit 0ee1f4734967af8321ecebaf9c74221ace34f2d5. The commit 0ee1f4734967 ("r8152: napi hangup fix after disconnect") adds a check about RTL8152_UNPLUG to determine if calling napi_disable() is invalid in rtl8152_close(), when rtl8152_disconnect() is called. This avoids to use napi_disable() after calling netif_napi_del(). Howver, commit ffa9fec30ca0 ("r8152: set RTL8152_UNPLUG only for real disconnection") causes that RTL8152_UNPLUG is not always set when calling rtl8152_disconnect(). Therefore, I have to revert commit 0ee1f4734967 ("r8152: napi hangup fix after disconnect"), first. And submit another patch to fix it. Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-28Merge branch '100GbE' of ↵David S. Miller
git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue Jeff Kirsher says: ==================== 100GbE Intel Wired LAN Driver Updates 2019-08-26 This series contains updates to ice driver only. Usha fixes the statistics reported on 4 port NICs which were reporting the incorrect statistics due to using the incorrect port identifier. Victor fixes an issue when trying to traverse to the first node of a requested layer by adding a sibling head pointer for each layer per traffic class. Anirudh cleans up the locking and logic for enabling and disabling VSI's to make it more consistent. Updates the driver to do dynamic allocation of queue management bitmaps and arrays, rather than statically allocating them which consumes more memory than required. Refactor the logic in ice_ena_msix_range() for clarity and add additional checks for when requested resources exceed what is available. Jesse updates the debugging print statements to make it more useful when dealing with link and PHY related issues. Krzysztof adds a local variable to the VSI rebuild path to improve readability. Akeem limits the reporting of MDD events from VFs so that the kernel log is not clogged up with MDD events which are duplicate or potentially false positives. Fixed a reset issue that would result in the system getting into a state that could only be resolved by a reboot by testing if the VF is in a disabled state during a reset. Michal adds a check to avoid trying to access memory that has not be allocated by checking the number of queue pairs. Jake fixes a static analysis warning due to a cast of a u8 to unsigned long, so just update ice_is_tc_ena() to take a unsigned long so that a cast is not necessary. Colin Ian King fixes a potential infinite loop where a u8 is being compared to an int. Maciej refactors the queue handling functions that work on queue arrays so that the logic can be done for a single queue. Paul adds support for VFs to enable and disable single queues. Henry fixed the order of operations in ice_remove() which was trying to use adminq operations that were already disabled. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-28ibmvnic: Do not process reset during or after device removalThomas Falcon
Currently, the ibmvnic driver will not schedule device resets if the device is being removed, but does not check the device state before the reset is actually processed. This leads to a race where a reset is scheduled with a valid device state but is processed after the driver has been removed, resulting in an oops. Fix this by checking the device state before processing a queued reset event. Reported-by: Abdul Haleem <abdhalee@linux.vnet.ibm.com> Tested-by: Abdul Haleem <abdhalee@linux.vnet.ibm.com> Signed-off-by: Thomas Falcon <tlfalcon@linux.ibm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-28phy: mdio-sun4i: use devm_platform_ioremap_resource() to simplify codeYueHaibing
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-28phy: mdio-mux-meson-g12a: use devm_platform_ioremap_resource() to simplify codeYueHaibing
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-28phy: mdio-moxart: use devm_platform_ioremap_resource() to simplify codeYueHaibing
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-28phy: mdio-hisi-femac: use devm_platform_ioremap_resource() to simplify codeYueHaibing
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-28phy: mdio-bcm-iproc: use devm_platform_ioremap_resource() to simplify codeYueHaibing
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-28wimax/i2400m: remove redundant assignment to variable resultColin Ian King
Variable result is being assigned a value that is never read and result is being re-assigned a little later on. The assignment is redundant and hence can be removed. Addresses-Coverity: ("Ununsed value") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-28macb: Update compatibility string for SiFive FU540-C000Yash Shah
Update the compatibility string for SiFive FU540-C000 as per the new string updated in the binding doc. Reference: https://lore.kernel.org/netdev/CAJ2_jOFEVZQat0Yprg4hem4jRrqkB72FKSeQj4p8P5KA-+rgww@mail.gmail.com/ Signed-off-by: Yash Shah <yash.shah@sifive.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Reviewed-by: Paul Walmsley <paul.walmsley@sifive.com> Tested-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-28net/mlx5e: Support TSO and TX checksum offloads for IP-in-IPMarina Varshaver
tunnels Add TX offloads support for IP-in-IP tunneled packets by reporting the needed netdev features. Signed-off-by: Marina Varshaver <marinav@mellanox.com> Signed-off-by: Avihu Hagag <avihuh@mellanox.com> Reviewed-by: Aya Levin <ayal@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-08-28net/mlx5e: Improve stateless offload capability checkMarina Varshaver
Use generic function for checking tunnel stateless offload capability instead of separate macros. Signed-off-by: Marina Varshaver <marinav@mellanox.com> Reviewed-by: Aya Levin <ayal@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-08-28net/mlx5e: Support RSS for IP-in-IP and IPv6 tunneled packetsAya Levin
Add support for inner header RSS on IP-in-IP and IPv6 tunneled packets. Add rules to the steering table regarding outer IP header, with IPv4/6->IP-in-IP. Tunneled packets with protocol numbers: 0x4 (IP-in-IP) and 0x29 (IPv6) are RSS-ed on the inner IP header. Separate FW dependencies between flow table inner IP capabilities and GRE offload support. Allowing this feature even if GRE offload is not supported. Tested with multi stream TCP traffic tunneled with IPnIP. Verified that: Without this patch, only a single RX ring was processing the traffic. With this patch, multiple RX rings were processing the traffic. Verified with and without GRE offload support. Signed-off-by: Aya Levin <ayal@mellanox.com> Reviewed-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-08-28net/mlx5e: Change function's position to a more fitting fileAya Levin
Move function which indicates whether tunnel inner flow table is supported from en.h to en_fs.c. It fits better right after tunnel protocol rules definitions. Signed-off-by: Aya Levin <ayal@mellanox.com> Reviewed-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-08-28net/mlx5e: Add device out of buffer counterMoshe Shemesh
Added the following packets drop counter: Device out of buffer - counts packets which were dropped due to full device internal receive queue. This counter will be shown on ethtool as a new counter called dev_out_of_buffer. The counter is read from FW by command QUERY_VNIC_ENV. Signed-off-by: Moshe Shemesh <moshe@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-08-28net/mlx5e: Support LAG TX port affinity distributionMaxim Mikityanskiy
When the VF LAG is in use, round-robin the TX affinity of channels among the different ports, if supported by the firmware. Create a set of TISes per port, while doing round-robin of the channels over the different sets. Let all SQs of a channel share the same set of TISes. If lag_tx_port_affinity HCA cap bit is supported, num_lag_ports > 1 and we aren't the LACP owner (PF in the regular use), assign the affinities, otherwise use tx_affinity == 0 in TIS context to let the FW assign the affinities itself. The TISes of the LACP owner are mapped only to the native physical port. For VFs, the starting port for round-robin is determined by its vhca_id, because a VF may have only one channel if attached to a single-core VM. Signed-off-by: Maxim Mikityanskiy <maximmi@mellanox.com> Signed-off-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: Mark Bloch <markb@mellanox.com> Reviewed-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-08-28net/mlx5e: Expose new function for TIS destroy loopTariq Toukan
For better modularity and code sharing. Function internal change to be introduced in the next patches. Signed-off-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-08-28net/mlx5e: ethtool, Fix a typo in WOL function namesErez Alfasi
Fix a typo in 'mlx5e_refomrat_wol_mode_mlx5_to_linux' and 'mlx5e_refomrat_wol_mode_linux_to_mlx5' function names: "refomrat" -> "reformat". Fixes: 928cfe8745a6 ("net/mlx5e: Wake On LAN support") Signed-off-by: Erez Alfasi <ereza@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-08-28Merge branch 'mlx5-next' of ↵Saeed Mahameed
git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux mlx5 HW spec and bits updates: 1) Aya exposes IP-in-IP capability in mlx5_core. 2) Maxim exposes lag tx port affinity capabilities. 3) Moshe adds VNIC_ENV internal rq counter bits. 4) ODP capabilities for DC transport Misc updates: 5) Saeed, two compiler warnings cleanups 6) Add XRQ legacy commands opcodes 7) Use refcount_t for refcount 8) fix a -Wstringop-truncation warning
2019-08-28net/mlx5: Set ODP capabilities for DC transport to maxMichael Guralnik
In mlx5_core initialization, query max ODP capabilities for DC transport from FW and set as current capabilities. Signed-off-by: Michael Guralnik <michaelgur@mellanox.com> Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
2019-08-27net: stmmac: setup higher frequency clk support for EHL & TGLVoon Weifeng
EHL DW EQOS is running on a 200MHz clock. Setting up stmmac-clk, ptp clock and ptp_max_adj to 200MHz. Signed-off-by: Voon Weifeng <weifeng.voon@intel.com> Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-27net: stmmac: add EHL RGMII 1Gbps PCI info and PCI IDVoon Weifeng
Added EHL RGMII 1Gbps PCI ID. Different MII and speed will have different PCI ID. Signed-off-by: Voon Weifeng <weifeng.voon@intel.com> Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-27net: stmmac: add TGL SGMII 1Gbps PCI info and PCI IDVoon Weifeng
Added TGL SGMII 1Gbps PCI ID. Different MII and speed will have different PCI ID. Signed-off-by: Voon Weifeng <weifeng.voon@intel.com> Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-27net: stmmac: add EHL SGMII 1Gbps PCI info and PCI IDVoon Weifeng
Added EHL SGMII 1Gbps PCI ID. Different MII and speed will have different PCI ID. Signed-off-by: Voon Weifeng <weifeng.voon@intel.com> Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-27net: dsa: mv88e6xxx: fully support SERDES on Topaz familyMarek Behún
Currently we support SERDES on the Topaz family in a limited way: no IRQs and the cmode is not writable, thus the mode is determined by strapping pins. Marvell's examples though show how to make cmode writable on port 5 and support SGMII autonegotiation. It is done by writing hidden registers, for which we already have code. This patch adds support for making the cmode for the SERDES port writable on the Topaz family, via a new chip operation, .port_set_cmode_writable, which is called from mv88e6xxx_port_setup_mac just before .port_set_cmode. SERDES IRQs are also enabled for Topaz. Tested on Turris Mox. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Vivien Didelot <vivien.didelot@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-27net: dsa: mv88e6xxx: rename port cmode macroMarek Behún
This is a cosmetic update. We are removing the last underscore from macros MV88E6XXX_PORT_STS_CMODE_100BASE_X and MV88E6XXX_PORT_STS_CMODE_1000BASE_X. The 2500base-x version does not have that underscore. Also PHY_INTERFACE_MODE_ macros do not have it there. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-27net: dsa: mv88e6xxx: simplify SERDES code for Topaz and PeridotMarek Behún
By adding an additional serdes_get_lane implementation (for Topaz), we can merge the implementations of other SERDES functions (powering and IRQs). We can skip checking port numbers, since the serdes_get_lane() methods inform if there is no lane on a port or if the lane cannot be used for given cmode. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-27net: dsa: mv88e6xxx: create serdes_get_lane chip operationMarek Behún
Create a serdes_get_lane() method in the mv88e6xxx operations structure. Use it instead of calling the different implementations. Also change the methods so that their return value is used only for error. The lane number is put into a place referred to by a pointer given as argument. If the port does not have a lane, return -ENODEV. Lanes are phy addresses, so use u8 as their type. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Vivien Didelot <vivien.didelot@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-27net: dsa: mv88e6xxx: update code operating on hidden registersMarek Behún
This patch moves the functions operating on the hidden debug registers into it's own file, port_hidden.c. The functions prefix is renamed from mv88e6390_hidden_ to mv88e6xxx_port_hidden_, to be consistent with the rest of this driver. The macros are prefixed with MV88E6XXX_ prefix, and are changed not to use the BIT() macro nor bit shifts, since the rest of the port.h file does not use it. We also add the support for setting the Block Address field when operating hidden registers. Marvell's mdio examples for SERDES settings on Topaz use Block Address 0x7 when reading/writing hidden registers, and although the specification says that block must be set to 0xf, those settings are reachable only with Block Address 0x7. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Vivien Didelot <vivien.didelot@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-27net: dsa: mv88e6xxx: support 2500base-x in SGMII IRQ handlerMarek Behún
The mv88e6390_serdes_irq_link_sgmii IRQ handler reads the SERDES PHY status register to determine speed, among other things. If cmode of the port is set to 2500base-x, though, the PHY still reports 1000 Mbps (the PHY register itself does not differentiate between 1000 Mbps and 2500 Mbps - it thinks it is running at 1000 Mbps, although clock is 2.5x faster). Look at the cmode and set SPEED_2500 if cmode is set to 2500base-x. Also tell mv88e6xxx_port_setup_mac the PHY interface mode corresponding to current cmode in terms of phy_interface_t. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Vivien Didelot <vivien.didelot@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-27net: mediatek: remove set but not used variable 'status'Mao Wenan
Fixes gcc '-Wunused-but-set-variable' warning: drivers/net/ethernet/mediatek/mtk_eth_soc.c: In function mtk_handle_irq: drivers/net/ethernet/mediatek/mtk_eth_soc.c:1951:6: warning: variable status set but not used [-Wunused-but-set-variable] Fixes: 296c9120752b ("net: ethernet: mediatek: Add MT7628/88 SoC support") Signed-off-by: Mao Wenan <maowenan@huawei.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-27net: dsa: sja1105: Clear VLAN filtering offload netdev featureVladimir Oltean
The switch barely supports traffic I/O, and it does that by repurposing VLANs when there is no bridge that is taking control of them. Letting DSA declare this netdev feature as supported (see dsa_slave_create) would mean that VLAN sub-interfaces created on sja1105 switch ports will be hardware offloaded. That means that net/8021q/vlan_core.c would install the VLAN into the filter tables of the switch, potentially interfering with the tag_8021q VLANs. We need to prevent that from happening and not let the 8021q core offload VLANs to the switch hardware tables. In vlan_filtering=0 modes of operation, the switch ports can pass through VLAN-tagged frames with no problem. Suggested-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-27Add genphy_c45_config_aneg() function to phy-c45.cMarco Hartmann
Commit 34786005eca3 ("net: phy: prevent PHYs w/o Clause 22 regs from calling genphy_config_aneg") introduced a check that aborts phy_config_aneg() if the phy is a C45 phy. This causes phy_state_machine() to call phy_error() so that the phy ends up in PHY_HALTED state. Instead of returning -EOPNOTSUPP, call genphy_c45_config_aneg() (analogous to the C22 case) so that the state machine can run correctly. genphy_c45_config_aneg() closely resembles mv3310_config_aneg() in drivers/net/phy/marvell10g.c, excluding vendor specific configurations for 1000BaseT. Fixes: 22b56e827093 ("net: phy: replace genphy_10g_driver with genphy_c45_driver") Signed-off-by: Marco Hartmann <marco.hartmann@nxp.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>